1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "SparcInstrInfo.h"
18 #include "SparcTargetMachine.h"
19 #include "MCTargetDesc/SparcBaseInfo.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/Mangler.h"
32 class SparcAsmPrinter : public AsmPrinter {
34 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
35 : AsmPrinter(TM, Streamer) {}
37 virtual const char *getPassName() const {
38 return "Sparc Assembly Printer";
41 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
42 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
43 const char *Modifier = 0);
44 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
46 virtual void EmitInstruction(const MachineInstr *MI) {
48 raw_svector_ostream OS(Str);
49 printInstruction(MI, OS);
50 OutStreamer.EmitRawText(OS.str());
52 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
53 static const char *getRegisterName(unsigned RegNo);
55 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56 unsigned AsmVariant, const char *ExtraCode,
58 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
59 unsigned AsmVariant, const char *ExtraCode,
62 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
64 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
67 } // end of anonymous namespace
69 #include "SparcGenAsmWriter.inc"
71 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
73 const MachineOperand &MO = MI->getOperand (opNum);
74 unsigned TF = MO.getTargetFlags();
76 // Verify the target flags.
77 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
78 if (MI->getOpcode() == SP::CALL)
79 assert(TF == SPII::MO_NO_FLAG &&
80 "Cannot handle target flags on call address");
81 else if (MI->getOpcode() == SP::SETHIi)
82 assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH) &&
83 "Invalid target flags for address operand on sethi");
85 assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44 ||
87 "Invalid target flags for small address operand");
91 bool CloseParen = true;
94 llvm_unreachable("Unknown target flags on operand");
95 case SPII::MO_NO_FLAG:
98 case SPII::MO_LO: O << "%lo("; break;
99 case SPII::MO_HI: O << "%hi("; break;
100 case SPII::MO_H44: O << "%h44("; break;
101 case SPII::MO_M44: O << "%m44("; break;
102 case SPII::MO_L44: O << "%l44("; break;
103 case SPII::MO_HH: O << "%hh("; break;
104 case SPII::MO_HM: O << "%hm("; break;
107 switch (MO.getType()) {
108 case MachineOperand::MO_Register:
109 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
112 case MachineOperand::MO_Immediate:
113 O << (int)MO.getImm();
115 case MachineOperand::MO_MachineBasicBlock:
116 O << *MO.getMBB()->getSymbol();
118 case MachineOperand::MO_GlobalAddress:
119 O << *Mang->getSymbol(MO.getGlobal());
121 case MachineOperand::MO_BlockAddress:
122 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
124 case MachineOperand::MO_ExternalSymbol:
125 O << MO.getSymbolName();
127 case MachineOperand::MO_ConstantPoolIndex:
128 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
132 llvm_unreachable("<unknown operand type>");
134 if (CloseParen) O << ")";
137 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
138 raw_ostream &O, const char *Modifier) {
139 printOperand(MI, opNum, O);
141 // If this is an ADD operand, emit it like normal operands.
142 if (Modifier && !strcmp(Modifier, "arith")) {
144 printOperand(MI, opNum+1, O);
148 if (MI->getOperand(opNum+1).isReg() &&
149 MI->getOperand(opNum+1).getReg() == SP::G0)
150 return; // don't print "+%g0"
151 if (MI->getOperand(opNum+1).isImm() &&
152 MI->getOperand(opNum+1).getImm() == 0)
153 return; // don't print "+0"
156 printOperand(MI, opNum+1, O);
159 bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
161 std::string operand = "";
162 const MachineOperand &MO = MI->getOperand(opNum);
163 switch (MO.getType()) {
164 default: llvm_unreachable("Operand is not a register");
165 case MachineOperand::MO_Register:
166 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
167 "Operand is not a physical register ");
168 assert(MO.getReg() != SP::O7 &&
169 "%o7 is assigned as destination for getpcx!");
170 operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
174 unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
175 unsigned bbNum = MI->getParent()->getNumber();
177 O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
178 O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
181 << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
182 << ")), " << operand << '\n' ;
184 O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
185 O << "\tor\t" << operand
186 << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
187 << ")), " << operand << '\n';
188 O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
193 void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
195 int CC = (int)MI->getOperand(opNum).getImm();
196 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
199 /// PrintAsmOperand - Print out an operand for an inline asm expression.
201 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
203 const char *ExtraCode,
205 if (ExtraCode && ExtraCode[0]) {
206 if (ExtraCode[1] != 0) return true; // Unknown modifier.
208 switch (ExtraCode[0]) {
210 // See if this is a generic print operand
211 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
217 printOperand(MI, OpNo, O);
222 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
223 unsigned OpNo, unsigned AsmVariant,
224 const char *ExtraCode,
226 if (ExtraCode && ExtraCode[0])
227 return true; // Unknown modifier
230 printMemOperand(MI, OpNo, O);
236 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
237 /// exactly one predecessor and the control transfer mechanism between
238 /// the predecessor and this block is a fall-through.
240 /// This overrides AsmPrinter's implementation to handle delay slots.
241 bool SparcAsmPrinter::
242 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
243 // If this is a landing pad, it isn't a fall through. If it has no preds,
244 // then nothing falls through to it.
245 if (MBB->isLandingPad() || MBB->pred_empty())
248 // If there isn't exactly one predecessor, it can't be a fall through.
249 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
251 if (PI2 != MBB->pred_end())
254 // The predecessor has to be immediately before this block.
255 const MachineBasicBlock *Pred = *PI;
257 if (!Pred->isLayoutSuccessor(MBB))
260 // Check if the last terminator is an unconditional branch.
261 MachineBasicBlock::const_iterator I = Pred->end();
262 while (I != Pred->begin() && !(--I)->isTerminator())
264 return I == Pred->end() || !I->isBarrier();
267 // Force static initialization.
268 extern "C" void LLVMInitializeSparcAsmPrinter() {
269 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
270 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);