1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "SparcInstrInfo.h"
18 #include "SparcTargetMachine.h"
19 #include "llvm/CodeGen/AsmPrinter.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Target/Mangler.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
31 class SparcAsmPrinter : public AsmPrinter {
33 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
34 : AsmPrinter(TM, Streamer) {}
36 virtual const char *getPassName() const {
37 return "Sparc Assembly Printer";
40 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
41 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
42 const char *Modifier = 0);
43 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
45 virtual void EmitInstruction(const MachineInstr *MI) {
47 raw_svector_ostream OS(Str);
48 printInstruction(MI, OS);
49 OutStreamer.EmitRawText(OS.str());
51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
52 static const char *getRegisterName(unsigned RegNo);
54 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
55 unsigned AsmVariant, const char *ExtraCode,
57 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
58 unsigned AsmVariant, const char *ExtraCode,
61 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
63 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
66 } // end of anonymous namespace
68 #include "SparcGenAsmWriter.inc"
70 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
72 const MachineOperand &MO = MI->getOperand (opNum);
73 bool CloseParen = false;
74 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) {
77 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) &&
78 !MO.isReg() && !MO.isImm()) {
82 switch (MO.getType()) {
83 case MachineOperand::MO_Register:
84 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
87 case MachineOperand::MO_Immediate:
88 O << (int)MO.getImm();
90 case MachineOperand::MO_MachineBasicBlock:
91 O << *MO.getMBB()->getSymbol();
93 case MachineOperand::MO_GlobalAddress:
94 O << *Mang->getSymbol(MO.getGlobal());
96 case MachineOperand::MO_ExternalSymbol:
97 O << MO.getSymbolName();
99 case MachineOperand::MO_ConstantPoolIndex:
100 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
104 llvm_unreachable("<unknown operand type>");
106 if (CloseParen) O << ")";
109 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
110 raw_ostream &O, const char *Modifier) {
111 printOperand(MI, opNum, O);
113 // If this is an ADD operand, emit it like normal operands.
114 if (Modifier && !strcmp(Modifier, "arith")) {
116 printOperand(MI, opNum+1, O);
120 if (MI->getOperand(opNum+1).isReg() &&
121 MI->getOperand(opNum+1).getReg() == SP::G0)
122 return; // don't print "+%g0"
123 if (MI->getOperand(opNum+1).isImm() &&
124 MI->getOperand(opNum+1).getImm() == 0)
125 return; // don't print "+0"
128 if (MI->getOperand(opNum+1).isGlobal() ||
129 MI->getOperand(opNum+1).isCPI()) {
131 printOperand(MI, opNum+1, O);
134 printOperand(MI, opNum+1, O);
138 bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
140 std::string operand = "";
141 const MachineOperand &MO = MI->getOperand(opNum);
142 switch (MO.getType()) {
143 default: assert(0 && "Operand is not a register ");
144 case MachineOperand::MO_Register:
145 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
146 "Operand is not a physical register ");
147 assert(MO.getReg() != SP::O7 &&
148 "%o7 is assigned as destination for getpcx!");
149 operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
153 unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
154 unsigned bbNum = MI->getParent()->getNumber();
156 O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
157 O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
160 << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
161 << ")), " << operand << '\n' ;
163 O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
164 O << "\tor\t" << operand
165 << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
166 << ")), " << operand << '\n';
167 O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
172 void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
174 int CC = (int)MI->getOperand(opNum).getImm();
175 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
178 /// PrintAsmOperand - Print out an operand for an inline asm expression.
180 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
182 const char *ExtraCode,
184 if (ExtraCode && ExtraCode[0]) {
185 if (ExtraCode[1] != 0) return true; // Unknown modifier.
187 switch (ExtraCode[0]) {
188 default: return true; // Unknown modifier.
194 printOperand(MI, OpNo, O);
199 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
200 unsigned OpNo, unsigned AsmVariant,
201 const char *ExtraCode,
203 if (ExtraCode && ExtraCode[0])
204 return true; // Unknown modifier
207 printMemOperand(MI, OpNo, O);
213 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
214 /// exactly one predecessor and the control transfer mechanism between
215 /// the predecessor and this block is a fall-through.
217 /// This overrides AsmPrinter's implementation to handle delay slots.
218 bool SparcAsmPrinter::
219 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
220 // If this is a landing pad, it isn't a fall through. If it has no preds,
221 // then nothing falls through to it.
222 if (MBB->isLandingPad() || MBB->pred_empty())
225 // If there isn't exactly one predecessor, it can't be a fall through.
226 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
228 if (PI2 != MBB->pred_end())
231 // The predecessor has to be immediately before this block.
232 const MachineBasicBlock *Pred = *PI;
234 if (!Pred->isLayoutSuccessor(MBB))
237 // Check if the last terminator is an unconditional branch.
238 MachineBasicBlock::const_iterator I = Pred->end();
239 while (I != Pred->begin() && !(--I)->isTerminator())
241 return I == Pred->end() || !I->isBarrier();
246 // Force static initialization.
247 extern "C" void LLVMInitializeSparcAsmPrinter() {
248 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
249 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);