1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcFrameLowering.h"
15 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Target/TargetOptions.h"
31 DisableLeafProc("disable-sparc-leaf-proc",
33 cl::desc("Disable Sparc leaf procedure optimization."),
36 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
37 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
38 ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
41 MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MBBI,
45 unsigned ADDri) const {
47 DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
48 const SparcInstrInfo &TII =
49 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
51 if (NumBytes >= -4096 && NumBytes < 4096) {
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53 .addReg(SP::O6).addImm(NumBytes);
57 // Emit this the hard way. This clobbers G1 which we always know is
60 // Emit nonnegative numbers with sethi + or.
61 // sethi %hi(NumBytes), %g1
62 // or %g1, %lo(NumBytes), %g1
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
65 .addImm(HI22(NumBytes));
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67 .addReg(SP::G1).addImm(LO10(NumBytes));
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69 .addReg(SP::O6).addReg(SP::G1);
73 // Emit negative numbers with sethi + xor.
74 // sethi %hix(NumBytes), %g1
75 // xor %g1, %lox(NumBytes), %g1
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
78 .addImm(HIX22(NumBytes));
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82 .addReg(SP::O6).addReg(SP::G1);
85 void SparcFrameLowering::emitPrologue(MachineFunction &MF,
86 MachineBasicBlock &MBB) const {
87 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
89 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
90 MachineFrameInfo *MFI = MF.getFrameInfo();
91 const SparcInstrInfo &TII =
92 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
93 const SparcRegisterInfo &RegInfo =
94 *static_cast<const SparcRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
95 MachineBasicBlock::iterator MBBI = MBB.begin();
96 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
97 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
99 // FIXME: unfortunately, returning false from canRealignStack
100 // actually just causes needsStackRealignment to return false,
101 // rather than reporting an error, as would be sensible. This is
102 // poor, but fixing that bogosity is going to be a large project.
103 // For now, just see if it's lied, and report an error here.
104 if (!NeedsStackRealignment && MFI->getMaxAlignment() > getStackAlignment())
105 report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
106 "stack re-alignment, but LLVM couldn't handle it "
107 "(probably because it has a dynamic alloca).");
109 // Get the number of bytes to allocate from the FrameInfo
110 int NumBytes = (int) MFI->getStackSize();
112 unsigned SAVEri = SP::SAVEri;
113 unsigned SAVErr = SP::SAVErr;
114 if (FuncInfo->isLeafProc()) {
121 // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
122 // (128 in v9) area in the user's stack, starting at %sp. Thus, the
123 // first part of the stack that can actually be used is located at
126 // We therefore need to add that offset to the total stack size
127 // after all the stack objects are placed by
128 // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
129 // aligned *after* the extra size is added, we need to disable
130 // calculateFrameObjectOffsets's built-in stack alignment, by having
131 // targetHandlesStackFrameRounding return true.
134 // Add the extra call frame stack size, if needed. (This is the same
135 // code as in PrologEpilogInserter, but also gets disabled by
136 // targetHandlesStackFrameRounding)
137 if (MFI->adjustsStack() && hasReservedCallFrame(MF))
138 NumBytes += MFI->getMaxCallFrameSize();
140 // Adds the SPARC subtarget-specific spill area to the stack
141 // size. Also ensures target-required alignment.
142 NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes);
144 // Finally, ensure that the size is sufficiently aligned for the
145 // data on the stack.
146 if (MFI->getMaxAlignment() > 0) {
147 NumBytes = RoundUpToAlignment(NumBytes, MFI->getMaxAlignment());
150 // Update stack size with corrected value.
151 MFI->setStackSize(NumBytes);
153 emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
155 MachineModuleInfo &MMI = MF.getMMI();
156 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
158 // Emit ".cfi_def_cfa_register 30".
160 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
162 .addCFIIndex(CFIIndex);
164 // Emit ".cfi_window_save".
165 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
166 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
167 .addCFIIndex(CFIIndex);
169 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
170 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
171 // Emit ".cfi_register 15, 31".
172 CFIIndex = MMI.addFrameInst(
173 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
174 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
175 .addCFIIndex(CFIIndex);
177 if (NeedsStackRealignment) {
178 // andn %o6, MaxAlign-1, %o6
179 int MaxAlign = MFI->getMaxAlignment();
180 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1);
184 void SparcFrameLowering::
185 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator I) const {
187 if (!hasReservedCallFrame(MF)) {
188 MachineInstr &MI = *I;
189 int Size = MI.getOperand(0).getImm();
190 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
194 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
200 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
201 MachineBasicBlock &MBB) const {
202 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
203 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
204 const SparcInstrInfo &TII =
205 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
206 DebugLoc dl = MBBI->getDebugLoc();
207 assert(MBBI->getOpcode() == SP::RETL &&
208 "Can only put epilog before 'retl' instruction!");
209 if (!FuncInfo->isLeafProc()) {
210 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
214 MachineFrameInfo *MFI = MF.getFrameInfo();
216 int NumBytes = (int) MFI->getStackSize();
220 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
223 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
224 // Reserve call frame if there are no variable sized objects on the stack.
225 return !MF.getFrameInfo()->hasVarSizedObjects();
228 // hasFP - Return true if the specified function should have a dedicated frame
229 // pointer register. This is true if the function has variable sized allocas or
230 // if frame pointer elimination is disabled.
231 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
232 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
234 const MachineFrameInfo *MFI = MF.getFrameInfo();
235 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
236 RegInfo->needsStackRealignment(MF) ||
237 MFI->hasVarSizedObjects() ||
238 MFI->isFrameAddressTaken();
242 int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
243 unsigned &FrameReg) const {
244 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
245 const MachineFrameInfo *MFI = MF.getFrameInfo();
246 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
247 const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
248 bool isFixed = MFI->isFixedObjectIndex(FI);
250 // Addressable stack objects are accessed using neg. offsets from
251 // %fp, or positive offsets from %sp.
254 // Sparc uses FP-based references in general, even when "hasFP" is
255 // false. That function is rather a misnomer, because %fp is
256 // actually always available, unless isLeafProc.
257 if (FuncInfo->isLeafProc()) {
258 // If there's a leaf proc, all offsets need to be %sp-based,
259 // because we haven't caused %fp to actually point to our frame.
261 } else if (isFixed) {
262 // Otherwise, argument access should always use %fp.
264 } else if (RegInfo->needsStackRealignment(MF)) {
265 // If there is dynamic stack realignment, all local object
266 // references need to be via %sp, to take account of the
270 // Finally, default to using %fp.
274 int64_t FrameOffset = MF.getFrameInfo()->getObjectOffset(FI) +
275 Subtarget.getStackPointerBias();
278 FrameReg = RegInfo->getFrameRegister(MF);
281 FrameReg = SP::O6; // %sp
282 return FrameOffset + MF.getFrameInfo()->getStackSize();
286 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
289 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
290 if (!MRI->reg_nodbg_empty(reg))
293 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
294 if (!MRI->reg_nodbg_empty(reg))
300 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
303 MachineRegisterInfo &MRI = MF.getRegInfo();
304 MachineFrameInfo *MFI = MF.getFrameInfo();
306 return !(MFI->hasCalls() // has calls
307 || !MRI.reg_nodbg_empty(SP::L0) // Too many registers needed
308 || !MRI.reg_nodbg_empty(SP::O6) // %SP is used
309 || hasFP(MF)); // need %FP
312 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
313 MachineRegisterInfo &MRI = MF.getRegInfo();
314 // Remap %i[0-7] to %o[0-7].
315 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
316 if (MRI.reg_nodbg_empty(reg))
319 unsigned mapped_reg = reg - SP::I0 + SP::O0;
320 assert(MRI.reg_nodbg_empty(mapped_reg));
322 // Replace I register with O register.
323 MRI.replaceRegWith(reg, mapped_reg);
325 // Also replace register pair super-registers.
326 if ((reg - SP::I0) % 2 == 0) {
327 unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
328 unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
329 MRI.replaceRegWith(preg, mapped_preg);
333 // Rewrite MBB's Live-ins.
334 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
336 for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
337 if (!MBB->isLiveIn(reg))
339 MBB->removeLiveIn(reg);
340 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
342 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
343 if (!MBB->isLiveIn(reg))
345 MBB->removeLiveIn(reg);
346 MBB->addLiveIn(reg - SP::I0 + SP::O0);
350 assert(verifyLeafProcRegUse(&MRI));
352 MF.verify(0, "After LeafProc Remapping");
356 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
357 BitVector &SavedRegs,
358 RegScavenger *RS) const {
359 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
360 if (!DisableLeafProc && isLeafProc(MF)) {
361 SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
362 MFI->setLeafProc(true);
364 remapRegsForLeafProc(MF);