1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcISelLowering.h"
15 #include "SparcTargetMachine.h"
16 #include "llvm/Intrinsics.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/Debug.h"
22 //===----------------------------------------------------------------------===//
23 // Instruction Selector Implementation
24 //===----------------------------------------------------------------------===//
26 //===--------------------------------------------------------------------===//
27 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
28 /// instructions for SelectionDAG operations.
31 class SparcDAGToDAGISel : public SelectionDAGISel {
32 SparcTargetLowering Lowering;
34 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
35 /// make the right decision when generating code for different targets.
36 const SparcSubtarget &Subtarget;
38 SparcDAGToDAGISel(TargetMachine &TM)
39 : SelectionDAGISel(Lowering), Lowering(TM),
40 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
43 SDNode *Select(SDOperand Op);
45 // Complex Pattern Selectors.
46 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
47 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
50 /// InstructionSelectBasicBlock - This callback is invoked by
51 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
52 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
54 virtual const char *getPassName() const {
55 return "SPARC DAG->DAG Pattern Instruction Selection";
58 // Include the pieces autogenerated from the target description.
59 #include "SparcGenDAGISel.inc"
61 } // end anonymous namespace
63 /// InstructionSelectBasicBlock - This callback is invoked by
64 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
65 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
68 // Select target instructions for the DAG.
69 DAG.setRoot(SelectRoot(DAG.getRoot()));
70 DAG.RemoveDeadNodes();
72 // Emit machine code to BB.
73 ScheduleAndEmitDAG(DAG);
76 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
77 SDOperand &Base, SDOperand &Offset) {
78 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
79 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
80 Offset = CurDAG->getTargetConstant(0, MVT::i32);
83 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
84 Addr.getOpcode() == ISD::TargetGlobalAddress)
85 return false; // direct calls.
87 if (Addr.getOpcode() == ISD::ADD) {
88 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
89 if (Predicate_simm13(CN)) {
90 if (FrameIndexSDNode *FIN =
91 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 // Constant offset from frame ref.
93 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
95 Base = Addr.getOperand(0);
97 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
102 Base = Addr.getOperand(1);
103 Offset = Addr.getOperand(0).getOperand(0);
106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
107 Base = Addr.getOperand(0);
108 Offset = Addr.getOperand(1).getOperand(0);
113 Offset = CurDAG->getTargetConstant(0, MVT::i32);
117 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
118 SDOperand &R1, SDOperand &R2) {
119 if (Addr.getOpcode() == ISD::FrameIndex) return false;
120 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
121 Addr.getOpcode() == ISD::TargetGlobalAddress)
122 return false; // direct calls.
124 if (Addr.getOpcode() == ISD::ADD) {
125 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
126 Predicate_simm13(Addr.getOperand(1).Val))
127 return false; // Let the reg+imm pattern catch this!
128 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
129 Addr.getOperand(1).getOpcode() == SPISD::Lo)
130 return false; // Let the reg+imm pattern catch this!
131 R1 = Addr.getOperand(0);
132 R2 = Addr.getOperand(1);
137 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
141 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
143 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
144 N->getOpcode() < SPISD::FIRST_NUMBER)
145 return NULL; // Already selected.
147 switch (N->getOpcode()) {
151 // FIXME: should use a custom expander to expose the SRA to the dag.
152 SDOperand DivLHS = N->getOperand(0);
153 SDOperand DivRHS = N->getOperand(1);
154 AddToISelQueue(DivLHS);
155 AddToISelQueue(DivRHS);
157 // Set the Y register to the high-part.
159 if (N->getOpcode() == ISD::SDIV) {
160 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
161 CurDAG->getTargetConstant(31, MVT::i32)), 0);
163 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
165 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
166 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
168 // FIXME: Handle div by immediate.
169 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
170 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
175 // FIXME: Handle mul by immediate.
176 SDOperand MulLHS = N->getOperand(0);
177 SDOperand MulRHS = N->getOperand(1);
178 AddToISelQueue(MulLHS);
179 AddToISelQueue(MulRHS);
180 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
181 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
183 // The high part is in the Y register.
184 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
189 return SelectCode(Op);
193 /// createSparcISelDag - This pass converts a legalized DAG into a
194 /// SPARC-specific DAG, ready for instruction scheduling.
196 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
197 return new SparcDAGToDAGISel(TM);