1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcTargetMachine.h"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/IR/Intrinsics.h"
17 #include "llvm/Support/Compiler.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
23 //===----------------------------------------------------------------------===//
24 // Instruction Selector Implementation
25 //===----------------------------------------------------------------------===//
27 //===--------------------------------------------------------------------===//
28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29 /// instructions for SelectionDAG operations.
32 class SparcDAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const SparcSubtarget &Subtarget;
36 SparcTargetMachine& TM;
38 explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
39 : SelectionDAGISel(tm),
40 Subtarget(tm.getSubtarget<SparcSubtarget>()),
44 SDNode *Select(SDNode *N);
46 // Complex Pattern Selectors.
47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
50 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
51 /// inline asm expressions.
52 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
54 std::vector<SDValue> &OutOps);
56 virtual const char *getPassName() const {
57 return "SPARC DAG->DAG Pattern Instruction Selection";
60 // Include the pieces autogenerated from the target description.
61 #include "SparcGenDAGISel.inc"
64 SDNode* getGlobalBaseReg();
66 } // end anonymous namespace
68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
69 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
70 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
73 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
74 SDValue &Base, SDValue &Offset) {
75 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
76 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI.getPointerTy());
77 Offset = CurDAG->getTargetConstant(0, MVT::i32);
80 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
81 Addr.getOpcode() == ISD::TargetGlobalAddress)
82 return false; // direct calls.
84 if (Addr.getOpcode() == ISD::ADD) {
85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
86 if (isInt<13>(CN->getSExtValue())) {
87 if (FrameIndexSDNode *FIN =
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
89 // Constant offset from frame ref.
90 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
93 Base = Addr.getOperand(0);
95 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
99 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
100 Base = Addr.getOperand(1);
101 Offset = Addr.getOperand(0).getOperand(0);
104 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
105 Base = Addr.getOperand(0);
106 Offset = Addr.getOperand(1).getOperand(0);
111 Offset = CurDAG->getTargetConstant(0, MVT::i32);
115 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
116 if (Addr.getOpcode() == ISD::FrameIndex) return false;
117 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
118 Addr.getOpcode() == ISD::TargetGlobalAddress)
119 return false; // direct calls.
121 if (Addr.getOpcode() == ISD::ADD) {
122 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
123 if (isInt<13>(CN->getSExtValue()))
124 return false; // Let the reg+imm pattern catch this!
125 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
126 Addr.getOperand(1).getOpcode() == SPISD::Lo)
127 return false; // Let the reg+imm pattern catch this!
128 R1 = Addr.getOperand(0);
129 R2 = Addr.getOperand(1);
134 R2 = CurDAG->getRegister(SP::G0, TLI.getPointerTy());
138 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
140 if (N->isMachineOpcode())
141 return NULL; // Already selected.
143 switch (N->getOpcode()) {
145 case SPISD::GLOBAL_BASE_REG:
146 return getGlobalBaseReg();
150 // sdivx / udivx handle 64-bit divides.
151 if (N->getValueType(0) == MVT::i64)
153 // FIXME: should use a custom expander to expose the SRA to the dag.
154 SDValue DivLHS = N->getOperand(0);
155 SDValue DivRHS = N->getOperand(1);
157 // Set the Y register to the high-part.
159 if (N->getOpcode() == ISD::SDIV) {
160 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
161 CurDAG->getTargetConstant(31, MVT::i32)), 0);
163 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
165 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
166 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
168 // FIXME: Handle div by immediate.
169 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
170 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
175 // FIXME: Handle mul by immediate.
176 SDValue MulLHS = N->getOperand(0);
177 SDValue MulRHS = N->getOperand(1);
178 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
179 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
181 // The high part is in the Y register.
182 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
186 return SelectCode(N);
190 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
191 /// inline asm expressions.
193 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
195 std::vector<SDValue> &OutOps) {
197 switch (ConstraintCode) {
198 default: return true;
200 if (!SelectADDRrr(Op, Op0, Op1))
201 SelectADDRri(Op, Op0, Op1);
205 OutOps.push_back(Op0);
206 OutOps.push_back(Op1);
210 /// createSparcISelDag - This pass converts a legalized DAG into a
211 /// SPARC-specific DAG, ready for instruction scheduling.
213 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
214 return new SparcDAGToDAGISel(TM);