1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcTargetMachine.h"
15 #include "llvm/Intrinsics.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/Support/Compiler.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
23 //===----------------------------------------------------------------------===//
24 // Instruction Selector Implementation
25 //===----------------------------------------------------------------------===//
27 //===--------------------------------------------------------------------===//
28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29 /// instructions for SelectionDAG operations.
32 class SparcDAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const SparcSubtarget &Subtarget;
36 SparcTargetMachine& TM;
38 explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
39 : SelectionDAGISel(tm),
40 Subtarget(tm.getSubtarget<SparcSubtarget>()),
44 SDNode *Select(SDNode *N);
46 // Complex Pattern Selectors.
47 bool SelectADDRrr(SDNode *Op, SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDNode *Op, SDValue N, SDValue &Base,
51 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
52 /// inline asm expressions.
53 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
55 std::vector<SDValue> &OutOps);
57 virtual const char *getPassName() const {
58 return "SPARC DAG->DAG Pattern Instruction Selection";
61 // Include the pieces autogenerated from the target description.
62 #include "SparcGenDAGISel.inc"
65 SDNode* getGlobalBaseReg();
67 } // end anonymous namespace
69 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
70 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
71 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
74 bool SparcDAGToDAGISel::SelectADDRri(SDNode *Op, SDValue Addr,
75 SDValue &Base, SDValue &Offset) {
76 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
77 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
78 Offset = CurDAG->getTargetConstant(0, MVT::i32);
81 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
82 Addr.getOpcode() == ISD::TargetGlobalAddress)
83 return false; // direct calls.
85 if (Addr.getOpcode() == ISD::ADD) {
86 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
87 if (Predicate_simm13(CN)) {
88 if (FrameIndexSDNode *FIN =
89 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
90 // Constant offset from frame ref.
91 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
93 Base = Addr.getOperand(0);
95 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
99 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
100 Base = Addr.getOperand(1);
101 Offset = Addr.getOperand(0).getOperand(0);
104 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
105 Base = Addr.getOperand(0);
106 Offset = Addr.getOperand(1).getOperand(0);
111 Offset = CurDAG->getTargetConstant(0, MVT::i32);
115 bool SparcDAGToDAGISel::SelectADDRrr(SDNode *Op, SDValue Addr,
116 SDValue &R1, SDValue &R2) {
117 if (Addr.getOpcode() == ISD::FrameIndex) return false;
118 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
119 Addr.getOpcode() == ISD::TargetGlobalAddress)
120 return false; // direct calls.
122 if (Addr.getOpcode() == ISD::ADD) {
123 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
124 Predicate_simm13(Addr.getOperand(1).getNode()))
125 return false; // Let the reg+imm pattern catch this!
126 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
127 Addr.getOperand(1).getOpcode() == SPISD::Lo)
128 return false; // Let the reg+imm pattern catch this!
129 R1 = Addr.getOperand(0);
130 R2 = Addr.getOperand(1);
135 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
139 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
140 DebugLoc dl = N->getDebugLoc();
141 if (N->isMachineOpcode())
142 return NULL; // Already selected.
144 switch (N->getOpcode()) {
146 case SPISD::GLOBAL_BASE_REG:
147 return getGlobalBaseReg();
151 // FIXME: should use a custom expander to expose the SRA to the dag.
152 SDValue DivLHS = N->getOperand(0);
153 SDValue DivRHS = N->getOperand(1);
155 // Set the Y register to the high-part.
157 if (N->getOpcode() == ISD::SDIV) {
158 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
159 CurDAG->getTargetConstant(31, MVT::i32)), 0);
161 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
163 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Flag, TopPart,
164 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
166 // FIXME: Handle div by immediate.
167 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
168 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
173 // FIXME: Handle mul by immediate.
174 SDValue MulLHS = N->getOperand(0);
175 SDValue MulRHS = N->getOperand(1);
176 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
177 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
179 // The high part is in the Y register.
180 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
185 return SelectCode(N);
189 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
190 /// inline asm expressions.
192 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
194 std::vector<SDValue> &OutOps) {
196 switch (ConstraintCode) {
197 default: return true;
199 if (!SelectADDRrr(Op.getNode(), Op, Op0, Op1))
200 SelectADDRri(Op.getNode(), Op, Op0, Op1);
204 OutOps.push_back(Op0);
205 OutOps.push_back(Op1);
209 /// createSparcISelDag - This pass converts a legalized DAG into a
210 /// SPARC-specific DAG, ready for instruction scheduling.
212 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
213 return new SparcDAGToDAGISel(TM);