1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
31 //===----------------------------------------------------------------------===//
32 // TargetLowering Implementation
33 //===----------------------------------------------------------------------===//
37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
38 CMPICC, // Compare two GPR operands, set icc.
39 CMPFCC, // Compare two FP operands, set fcc.
40 BRICC, // Branch to dest on icc condition
41 BRFCC, // Branch to dest on fcc condition
42 SELECT_ICC, // Select between two values using the current ICC flags.
43 SELECT_FCC, // Select between two values using the current FCC flags.
45 Hi, Lo, // Hi/Lo operations, typically on a global address.
47 FTOI, // FP to Int within a FP register.
48 ITOF, // Int to FP within a FP register.
50 CALL, // A call instruction.
51 RET_FLAG // Return with a flag operand.
55 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
57 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
59 default: assert(0 && "Unknown integer condition code!");
60 case ISD::SETEQ: return SPCC::ICC_E;
61 case ISD::SETNE: return SPCC::ICC_NE;
62 case ISD::SETLT: return SPCC::ICC_L;
63 case ISD::SETGT: return SPCC::ICC_G;
64 case ISD::SETLE: return SPCC::ICC_LE;
65 case ISD::SETGE: return SPCC::ICC_GE;
66 case ISD::SETULT: return SPCC::ICC_CS;
67 case ISD::SETULE: return SPCC::ICC_LEU;
68 case ISD::SETUGT: return SPCC::ICC_GU;
69 case ISD::SETUGE: return SPCC::ICC_CC;
73 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
75 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
77 default: assert(0 && "Unknown fp condition code!");
79 case ISD::SETOEQ: return SPCC::FCC_E;
81 case ISD::SETUNE: return SPCC::FCC_NE;
83 case ISD::SETOLT: return SPCC::FCC_L;
85 case ISD::SETOGT: return SPCC::FCC_G;
87 case ISD::SETOLE: return SPCC::FCC_LE;
89 case ISD::SETOGE: return SPCC::FCC_GE;
90 case ISD::SETULT: return SPCC::FCC_UL;
91 case ISD::SETULE: return SPCC::FCC_ULE;
92 case ISD::SETUGT: return SPCC::FCC_UG;
93 case ISD::SETUGE: return SPCC::FCC_UGE;
94 case ISD::SETUO: return SPCC::FCC_U;
95 case ISD::SETO: return SPCC::FCC_O;
96 case ISD::SETONE: return SPCC::FCC_LG;
97 case ISD::SETUEQ: return SPCC::FCC_UE;
102 class SparcTargetLowering : public TargetLowering {
103 int VarArgsFrameOffset; // Frame offset to start of varargs area.
105 SparcTargetLowering(TargetMachine &TM);
106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
109 /// in Mask are known to be either zero or one and return them in the
110 /// KnownZero/KnownOne bitsets.
111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
115 const SelectionDAG &DAG,
116 unsigned Depth = 0) const;
118 virtual std::vector<SDOperand>
119 LowerArguments(Function &F, SelectionDAG &DAG);
120 virtual std::pair<SDOperand, SDOperand>
121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
122 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
123 ArgListTy &Args, SelectionDAG &DAG);
124 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
125 MachineBasicBlock *MBB);
127 virtual const char *getTargetNodeName(unsigned Opcode) const;
131 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
132 : TargetLowering(TM) {
134 // Set up the register classes.
135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
139 // Turn FP extload into load/fextend
140 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
142 // Custom legalize GlobalAddress nodes into LO/HI parts.
143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
144 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
145 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
147 // Sparc doesn't have sext_inreg, replace them with shl/sra
148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
152 // Sparc has no REM operation.
153 setOperationAction(ISD::UREM, MVT::i32, Expand);
154 setOperationAction(ISD::SREM, MVT::i32, Expand);
156 // Custom expand fp<->sint
157 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
158 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
161 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
162 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
164 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
165 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
167 // Sparc has no select or setcc: expand to SELECT_CC.
168 setOperationAction(ISD::SELECT, MVT::i32, Expand);
169 setOperationAction(ISD::SELECT, MVT::f32, Expand);
170 setOperationAction(ISD::SELECT, MVT::f64, Expand);
171 setOperationAction(ISD::SETCC, MVT::i32, Expand);
172 setOperationAction(ISD::SETCC, MVT::f32, Expand);
173 setOperationAction(ISD::SETCC, MVT::f64, Expand);
175 // Sparc doesn't have BRCOND either, it has BR_CC.
176 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
177 setOperationAction(ISD::BRIND, MVT::Other, Expand);
178 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
179 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
181 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
183 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
184 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
185 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
187 // SPARC has no intrinsics for these particular operations.
188 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
189 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
190 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
192 setOperationAction(ISD::FSIN , MVT::f64, Expand);
193 setOperationAction(ISD::FCOS , MVT::f64, Expand);
194 setOperationAction(ISD::FSIN , MVT::f32, Expand);
195 setOperationAction(ISD::FCOS , MVT::f32, Expand);
196 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
197 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
198 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
199 setOperationAction(ISD::ROTL , MVT::i32, Expand);
200 setOperationAction(ISD::ROTR , MVT::i32, Expand);
201 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
202 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
203 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
205 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
206 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
207 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
209 // We don't have line number support yet.
210 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
211 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
212 setOperationAction(ISD::LABEL, MVT::Other, Expand);
214 // RET must be custom lowered, to meet ABI requirements
215 setOperationAction(ISD::RET , MVT::Other, Custom);
217 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
218 setOperationAction(ISD::VASTART , MVT::Other, Custom);
219 // VAARG needs to be lowered to not do unaligned accesses for doubles.
220 setOperationAction(ISD::VAARG , MVT::Other, Custom);
222 // Use the default implementation.
223 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
224 setOperationAction(ISD::VAEND , MVT::Other, Expand);
225 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
226 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
227 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
229 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
230 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
232 setStackPointerRegisterToSaveRestore(SP::O6);
234 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
235 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
238 computeRegisterProperties();
241 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
244 case SPISD::CMPICC: return "SPISD::CMPICC";
245 case SPISD::CMPFCC: return "SPISD::CMPFCC";
246 case SPISD::BRICC: return "SPISD::BRICC";
247 case SPISD::BRFCC: return "SPISD::BRFCC";
248 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
249 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
250 case SPISD::Hi: return "SPISD::Hi";
251 case SPISD::Lo: return "SPISD::Lo";
252 case SPISD::FTOI: return "SPISD::FTOI";
253 case SPISD::ITOF: return "SPISD::ITOF";
254 case SPISD::CALL: return "SPISD::CALL";
255 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
259 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
260 /// be zero. Op is expected to be a target specific node. Used by DAG
262 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
266 const SelectionDAG &DAG,
267 unsigned Depth) const {
268 uint64_t KnownZero2, KnownOne2;
269 KnownZero = KnownOne = 0; // Don't know anything.
271 switch (Op.getOpcode()) {
273 case SPISD::SELECT_ICC:
274 case SPISD::SELECT_FCC:
275 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
277 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
279 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
280 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
282 // Only known if known in both the LHS and RHS.
283 KnownOne &= KnownOne2;
284 KnownZero &= KnownZero2;
289 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
290 /// either one or two GPRs, including FP values. TODO: we should pass FP values
291 /// in FP registers for fastcc functions.
292 std::vector<SDOperand>
293 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
294 MachineFunction &MF = DAG.getMachineFunction();
295 SSARegMap *RegMap = MF.getSSARegMap();
296 std::vector<SDOperand> ArgValues;
298 static const unsigned ArgRegs[] = {
299 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
302 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
303 unsigned ArgOffset = 68;
305 SDOperand Root = DAG.getRoot();
306 std::vector<SDOperand> OutChains;
308 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
309 MVT::ValueType ObjectVT = getValueType(I->getType());
312 default: assert(0 && "Unhandled argument type!");
317 if (I->use_empty()) { // Argument is dead.
318 if (CurArgReg < ArgRegEnd) ++CurArgReg;
319 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
320 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
321 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
322 MF.addLiveIn(*CurArgReg++, VReg);
323 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
324 if (ObjectVT != MVT::i32) {
325 unsigned AssertOp = ISD::AssertSext;
326 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
327 DAG.getValueType(ObjectVT));
328 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
330 ArgValues.push_back(Arg);
332 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
333 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
335 if (ObjectVT == MVT::i32) {
336 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
338 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
340 // Sparc is big endian, so add an offset based on the ObjectVT.
341 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
342 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
343 DAG.getConstant(Offset, MVT::i32));
344 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
346 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
348 ArgValues.push_back(Load);
354 if (I->use_empty()) { // Argument is dead.
355 if (CurArgReg < ArgRegEnd) ++CurArgReg;
356 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
357 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
358 // FP value is passed in an integer register.
359 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
360 MF.addLiveIn(*CurArgReg++, VReg);
361 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
363 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
364 ArgValues.push_back(Arg);
366 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
367 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
368 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
369 ArgValues.push_back(Load);
376 if (I->use_empty()) { // Argument is dead.
377 if (CurArgReg < ArgRegEnd) ++CurArgReg;
378 if (CurArgReg < ArgRegEnd) ++CurArgReg;
379 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
380 } else if (/* FIXME: Apparently this isn't safe?? */
381 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
382 ((CurArgReg-ArgRegs) & 1) == 0) {
383 // If this is a double argument and the whole thing lives on the stack,
384 // and the argument is aligned, load the double straight from the stack.
385 // We can't do a load in cases like void foo([6ints], int,double),
386 // because the double wouldn't be aligned!
387 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
388 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
389 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
392 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
393 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
394 MF.addLiveIn(*CurArgReg++, VRegHi);
395 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
397 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
398 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
399 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
403 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
404 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
405 MF.addLiveIn(*CurArgReg++, VRegLo);
406 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
408 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
409 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
410 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
413 // Compose the two halves together into an i64 unit.
414 SDOperand WholeValue =
415 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
417 // If we want a double, do a bit convert.
418 if (ObjectVT == MVT::f64)
419 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
421 ArgValues.push_back(WholeValue);
428 // Store remaining ArgRegs to the stack if this is a varargs function.
429 if (F.getFunctionType()->isVarArg()) {
430 // Remember the vararg offset for the va_start implementation.
431 VarArgsFrameOffset = ArgOffset;
433 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
434 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
435 MF.addLiveIn(*CurArgReg, VReg);
436 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
438 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
439 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
441 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
446 if (!OutChains.empty())
447 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
448 &OutChains[0], OutChains.size()));
450 // Finally, inform the code generator which regs we return values in.
451 switch (getValueType(F.getReturnType())) {
452 default: assert(0 && "Unknown type!");
453 case MVT::isVoid: break;
458 MF.addLiveOut(SP::I0);
461 MF.addLiveOut(SP::I0);
462 MF.addLiveOut(SP::I1);
465 MF.addLiveOut(SP::F0);
468 MF.addLiveOut(SP::D0);
475 std::pair<SDOperand, SDOperand>
476 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
477 bool RetTyIsSigned, bool isVarArg, unsigned CC,
478 bool isTailCall, SDOperand Callee,
479 ArgListTy &Args, SelectionDAG &DAG) {
480 // Count the size of the outgoing arguments.
481 unsigned ArgsSize = 0;
482 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
483 switch (getValueType(Args[i].Ty)) {
484 default: assert(0 && "Unknown value type!");
499 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
503 // Keep stack frames 8-byte aligned.
504 ArgsSize = (ArgsSize+7) & ~7;
506 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
509 std::vector<SDOperand> Stores;
510 std::vector<SDOperand> RegValuesToPass;
511 unsigned ArgOffset = 68;
512 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
513 SDOperand Val = Args[i].Node;
514 MVT::ValueType ObjectVT = Val.getValueType();
515 SDOperand ValToStore(0, 0);
518 default: assert(0 && "Unhandled argument type!");
522 // Promote the integer to 32-bits. If the input type is signed, use a
523 // sign extend, otherwise use a zero extend.
524 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
526 ExtendKind = ISD::SIGN_EXTEND;
527 else if (Args[i].isZExt)
528 ExtendKind = ISD::ZERO_EXTEND;
529 Val = DAG.getNode(ExtendKind, MVT::i32, Val);
535 if (RegValuesToPass.size() >= 6) {
538 RegValuesToPass.push_back(Val);
543 if (RegValuesToPass.size() >= 6) {
546 // Convert this to a FP value in an int reg.
547 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
548 RegValuesToPass.push_back(Val);
553 // If we can store this directly into the outgoing slot, do so. We can
554 // do this when all ArgRegs are used and if the outgoing slot is aligned.
555 // FIXME: McGill/misr fails with this.
556 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
561 // Otherwise, convert this to a FP value in int regs.
562 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
566 if (RegValuesToPass.size() >= 6) {
567 ValToStore = Val; // Whole thing is passed in memory.
571 // Split the value into top and bottom part. Top part goes in a reg.
572 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
573 DAG.getConstant(1, MVT::i32));
574 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
575 DAG.getConstant(0, MVT::i32));
576 RegValuesToPass.push_back(Hi);
578 if (RegValuesToPass.size() >= 6) {
583 RegValuesToPass.push_back(Lo);
588 if (ValToStore.Val) {
590 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
592 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
593 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
594 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
596 ArgOffset += ObjSize;
599 // Emit all stores, make sure the occur before any copies into physregs.
601 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
603 static const unsigned ArgRegs[] = {
604 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
607 // Build a sequence of copy-to-reg nodes chained together with token chain
608 // and flag operands which copy the outgoing args into O[0-5].
610 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
611 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
612 InFlag = Chain.getValue(1);
615 // If the callee is a GlobalAddress node (quite common, every direct call is)
616 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
617 // Likewise ExternalSymbol -> TargetExternalSymbol.
618 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
619 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
620 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
621 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
623 std::vector<MVT::ValueType> NodeTys;
624 NodeTys.push_back(MVT::Other); // Returns a chain
625 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
626 SDOperand Ops[] = { Chain, Callee, InFlag };
627 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
628 InFlag = Chain.getValue(1);
630 MVT::ValueType RetTyVT = getValueType(RetTy);
632 if (RetTyVT != MVT::isVoid) {
634 default: assert(0 && "Unknown value type to return!");
638 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
639 Chain = RetVal.getValue(1);
641 // Add a note to keep track of whether it is sign or zero extended.
642 ISD::NodeType AssertKind = ISD::AssertZext;
644 AssertKind = ISD::AssertSext;
645 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
646 DAG.getValueType(RetTyVT));
647 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
651 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
652 Chain = RetVal.getValue(1);
655 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
656 Chain = RetVal.getValue(1);
659 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
660 Chain = RetVal.getValue(1);
663 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
664 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
666 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
667 Chain = Hi.getValue(1);
672 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
673 DAG.getConstant(ArgsSize, getPointerTy()));
675 return std::make_pair(RetVal, Chain);
678 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
679 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
680 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
681 ISD::CondCode CC, unsigned &SPCC) {
682 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
684 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
685 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
686 (LHS.getOpcode() == SPISD::SELECT_FCC &&
687 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
688 isa<ConstantSDNode>(LHS.getOperand(0)) &&
689 isa<ConstantSDNode>(LHS.getOperand(1)) &&
690 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
691 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
692 SDOperand CMPCC = LHS.getOperand(3);
693 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
694 LHS = CMPCC.getOperand(0);
695 RHS = CMPCC.getOperand(1);
700 SDOperand SparcTargetLowering::
701 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
702 switch (Op.getOpcode()) {
703 default: assert(0 && "Should not custom lower this!");
704 case ISD::GlobalTLSAddress:
705 assert(0 && "TLS not implemented for Sparc.");
706 case ISD::GlobalAddress: {
707 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
708 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
709 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
710 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
711 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
713 case ISD::ConstantPool: {
714 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
715 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
716 cast<ConstantPoolSDNode>(Op)->getAlignment());
717 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
718 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
719 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
721 case ISD::FP_TO_SINT:
722 // Convert the fp value to integer in an FP register.
723 assert(Op.getValueType() == MVT::i32);
724 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
725 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
726 case ISD::SINT_TO_FP: {
727 assert(Op.getOperand(0).getValueType() == MVT::i32);
728 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
729 // Convert the int value to FP in an FP register.
730 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
733 SDOperand Chain = Op.getOperand(0);
734 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
735 SDOperand LHS = Op.getOperand(2);
736 SDOperand RHS = Op.getOperand(3);
737 SDOperand Dest = Op.getOperand(4);
738 unsigned Opc, SPCC = ~0U;
740 // If this is a br_cc of a "setcc", and if the setcc got lowered into
741 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
742 LookThroughSetCC(LHS, RHS, CC, SPCC);
744 // Get the condition flag.
745 SDOperand CompareFlag;
746 if (LHS.getValueType() == MVT::i32) {
747 std::vector<MVT::ValueType> VTs;
748 VTs.push_back(MVT::i32);
749 VTs.push_back(MVT::Flag);
750 SDOperand Ops[2] = { LHS, RHS };
751 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
752 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
755 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
756 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
759 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
760 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
762 case ISD::SELECT_CC: {
763 SDOperand LHS = Op.getOperand(0);
764 SDOperand RHS = Op.getOperand(1);
765 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
766 SDOperand TrueVal = Op.getOperand(2);
767 SDOperand FalseVal = Op.getOperand(3);
768 unsigned Opc, SPCC = ~0U;
770 // If this is a select_cc of a "setcc", and if the setcc got lowered into
771 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
772 LookThroughSetCC(LHS, RHS, CC, SPCC);
774 SDOperand CompareFlag;
775 if (LHS.getValueType() == MVT::i32) {
776 std::vector<MVT::ValueType> VTs;
777 VTs.push_back(LHS.getValueType()); // subcc returns a value
778 VTs.push_back(MVT::Flag);
779 SDOperand Ops[2] = { LHS, RHS };
780 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
781 Opc = SPISD::SELECT_ICC;
782 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
784 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
785 Opc = SPISD::SELECT_FCC;
786 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
788 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
789 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
792 // vastart just stores the address of the VarArgsFrameIndex slot into the
793 // memory location argument.
794 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
795 DAG.getRegister(SP::I6, MVT::i32),
796 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
797 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
798 return DAG.getStore(Op.getOperand(0), Offset,
799 Op.getOperand(1), SV->getValue(), SV->getOffset());
802 SDNode *Node = Op.Val;
803 MVT::ValueType VT = Node->getValueType(0);
804 SDOperand InChain = Node->getOperand(0);
805 SDOperand VAListPtr = Node->getOperand(1);
806 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
807 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
808 SV->getValue(), SV->getOffset());
809 // Increment the pointer, VAList, to the next vaarg
810 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
811 DAG.getConstant(MVT::getSizeInBits(VT)/8,
813 // Store the incremented VAList to the legalized pointer
814 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
815 VAListPtr, SV->getValue(), SV->getOffset());
816 // Load the actual argument out of the pointer VAList, unless this is an
818 if (VT != MVT::f64) {
819 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
821 // Otherwise, load it as i64, then do a bitconvert.
822 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
823 std::vector<MVT::ValueType> Tys;
824 Tys.push_back(MVT::f64);
825 Tys.push_back(MVT::Other);
826 // Bit-Convert the value to f64.
827 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
829 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
832 case ISD::DYNAMIC_STACKALLOC: {
833 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
834 SDOperand Size = Op.getOperand(1); // Legalize the size.
836 unsigned SPReg = SP::O6;
837 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
838 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
839 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
841 // The resultant pointer is actually 16 words from the bottom of the stack,
842 // to provide a register spill area.
843 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
844 DAG.getConstant(96, MVT::i32));
845 std::vector<MVT::ValueType> Tys;
846 Tys.push_back(MVT::i32);
847 Tys.push_back(MVT::Other);
848 SDOperand Ops[2] = { NewVal, Chain };
849 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
854 switch(Op.getNumOperands()) {
856 assert(0 && "Do not know how to return this many arguments!");
859 return SDOperand(); // ret void is legal
862 switch(Op.getOperand(1).getValueType()) {
863 default: assert(0 && "Unknown type to return!");
864 case MVT::i32: ArgReg = SP::I0; break;
865 case MVT::f32: ArgReg = SP::F0; break;
866 case MVT::f64: ArgReg = SP::D0; break;
868 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
873 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
875 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
878 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
880 // Frame & Return address. Currently unimplemented
881 case ISD::RETURNADDR: break;
882 case ISD::FRAMEADDR: break;
888 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
889 MachineBasicBlock *BB) {
890 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
893 // Figure out the conditional branch opcode to use for this select_cc.
894 switch (MI->getOpcode()) {
895 default: assert(0 && "Unknown SELECT_CC!");
896 case SP::SELECT_CC_Int_ICC:
897 case SP::SELECT_CC_FP_ICC:
898 case SP::SELECT_CC_DFP_ICC:
899 BROpcode = SP::BCOND;
901 case SP::SELECT_CC_Int_FCC:
902 case SP::SELECT_CC_FP_FCC:
903 case SP::SELECT_CC_DFP_FCC:
904 BROpcode = SP::FBCOND;
908 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
910 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
911 // control-flow pattern. The incoming instruction knows the destination vreg
912 // to set, the condition code register to branch on, the true/false values to
913 // select between, and a branch opcode to use.
914 const BasicBlock *LLVM_BB = BB->getBasicBlock();
915 ilist<MachineBasicBlock>::iterator It = BB;
922 // fallthrough --> copy0MBB
923 MachineBasicBlock *thisMBB = BB;
924 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
925 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
926 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
927 MachineFunction *F = BB->getParent();
928 F->getBasicBlockList().insert(It, copy0MBB);
929 F->getBasicBlockList().insert(It, sinkMBB);
930 // Update machine-CFG edges by first adding all successors of the current
931 // block to the new block which will contain the Phi node for the select.
932 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
933 e = BB->succ_end(); i != e; ++i)
934 sinkMBB->addSuccessor(*i);
935 // Next, remove all successors of the current block, and add the true
936 // and fallthrough blocks as its successors.
937 while(!BB->succ_empty())
938 BB->removeSuccessor(BB->succ_begin());
939 BB->addSuccessor(copy0MBB);
940 BB->addSuccessor(sinkMBB);
944 // # fallthrough to sinkMBB
947 // Update machine-CFG edges
948 BB->addSuccessor(sinkMBB);
951 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
954 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
955 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
956 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
958 delete MI; // The pseudo instruction is gone now.
962 //===----------------------------------------------------------------------===//
963 // Instruction Selector Implementation
964 //===----------------------------------------------------------------------===//
966 //===--------------------------------------------------------------------===//
967 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
968 /// instructions for SelectionDAG operations.
971 class SparcDAGToDAGISel : public SelectionDAGISel {
972 SparcTargetLowering Lowering;
974 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
975 /// make the right decision when generating code for different targets.
976 const SparcSubtarget &Subtarget;
978 SparcDAGToDAGISel(TargetMachine &TM)
979 : SelectionDAGISel(Lowering), Lowering(TM),
980 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
983 SDNode *Select(SDOperand Op);
985 // Complex Pattern Selectors.
986 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
987 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
990 /// InstructionSelectBasicBlock - This callback is invoked by
991 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
992 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
994 virtual const char *getPassName() const {
995 return "SPARC DAG->DAG Pattern Instruction Selection";
998 // Include the pieces autogenerated from the target description.
999 #include "SparcGenDAGISel.inc"
1001 } // end anonymous namespace
1003 /// InstructionSelectBasicBlock - This callback is invoked by
1004 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1005 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1008 // Select target instructions for the DAG.
1009 DAG.setRoot(SelectRoot(DAG.getRoot()));
1010 DAG.RemoveDeadNodes();
1012 // Emit machine code to BB.
1013 ScheduleAndEmitDAG(DAG);
1016 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1017 SDOperand &Base, SDOperand &Offset) {
1018 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1019 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1020 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1023 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1024 Addr.getOpcode() == ISD::TargetGlobalAddress)
1025 return false; // direct calls.
1027 if (Addr.getOpcode() == ISD::ADD) {
1028 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1029 if (Predicate_simm13(CN)) {
1030 if (FrameIndexSDNode *FIN =
1031 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1032 // Constant offset from frame ref.
1033 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1035 Base = Addr.getOperand(0);
1037 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1041 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1042 Base = Addr.getOperand(1);
1043 Offset = Addr.getOperand(0).getOperand(0);
1046 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1047 Base = Addr.getOperand(0);
1048 Offset = Addr.getOperand(1).getOperand(0);
1053 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1057 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1058 SDOperand &R1, SDOperand &R2) {
1059 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1060 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1061 Addr.getOpcode() == ISD::TargetGlobalAddress)
1062 return false; // direct calls.
1064 if (Addr.getOpcode() == ISD::ADD) {
1065 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1066 Predicate_simm13(Addr.getOperand(1).Val))
1067 return false; // Let the reg+imm pattern catch this!
1068 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1069 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1070 return false; // Let the reg+imm pattern catch this!
1071 R1 = Addr.getOperand(0);
1072 R2 = Addr.getOperand(1);
1077 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1081 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1083 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1084 N->getOpcode() < SPISD::FIRST_NUMBER)
1085 return NULL; // Already selected.
1087 switch (N->getOpcode()) {
1091 // FIXME: should use a custom expander to expose the SRA to the dag.
1092 SDOperand DivLHS = N->getOperand(0);
1093 SDOperand DivRHS = N->getOperand(1);
1094 AddToISelQueue(DivLHS);
1095 AddToISelQueue(DivRHS);
1097 // Set the Y register to the high-part.
1099 if (N->getOpcode() == ISD::SDIV) {
1100 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1101 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1103 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1105 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1106 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1108 // FIXME: Handle div by immediate.
1109 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1110 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1115 // FIXME: Handle mul by immediate.
1116 SDOperand MulLHS = N->getOperand(0);
1117 SDOperand MulRHS = N->getOperand(1);
1118 AddToISelQueue(MulLHS);
1119 AddToISelQueue(MulRHS);
1120 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1121 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1123 // The high part is in the Y register.
1124 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1129 return SelectCode(Op);
1133 /// createSparcISelDag - This pass converts a legalized DAG into a
1134 /// SPARC-specific DAG, ready for instruction scheduling.
1136 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1137 return new SparcDAGToDAGISel(TM);