1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
32 //===----------------------------------------------------------------------===//
33 // TargetLowering Implementation
34 //===----------------------------------------------------------------------===//
38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
39 CMPICC, // Compare two GPR operands, set icc.
40 CMPFCC, // Compare two FP operands, set fcc.
41 BRICC, // Branch to dest on icc condition
42 BRFCC, // Branch to dest on fcc condition
43 SELECT_ICC, // Select between two values using the current ICC flags.
44 SELECT_FCC, // Select between two values using the current FCC flags.
46 Hi, Lo, // Hi/Lo operations, typically on a global address.
48 FTOI, // FP to Int within a FP register.
49 ITOF, // Int to FP within a FP register.
51 CALL, // A call instruction.
52 RET_FLAG // Return with a flag operand.
56 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
58 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
60 default: assert(0 && "Unknown integer condition code!");
61 case ISD::SETEQ: return SPCC::ICC_E;
62 case ISD::SETNE: return SPCC::ICC_NE;
63 case ISD::SETLT: return SPCC::ICC_L;
64 case ISD::SETGT: return SPCC::ICC_G;
65 case ISD::SETLE: return SPCC::ICC_LE;
66 case ISD::SETGE: return SPCC::ICC_GE;
67 case ISD::SETULT: return SPCC::ICC_CS;
68 case ISD::SETULE: return SPCC::ICC_LEU;
69 case ISD::SETUGT: return SPCC::ICC_GU;
70 case ISD::SETUGE: return SPCC::ICC_CC;
74 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
76 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
78 default: assert(0 && "Unknown fp condition code!");
80 case ISD::SETOEQ: return SPCC::FCC_E;
82 case ISD::SETUNE: return SPCC::FCC_NE;
84 case ISD::SETOLT: return SPCC::FCC_L;
86 case ISD::SETOGT: return SPCC::FCC_G;
88 case ISD::SETOLE: return SPCC::FCC_LE;
90 case ISD::SETOGE: return SPCC::FCC_GE;
91 case ISD::SETULT: return SPCC::FCC_UL;
92 case ISD::SETULE: return SPCC::FCC_ULE;
93 case ISD::SETUGT: return SPCC::FCC_UG;
94 case ISD::SETUGE: return SPCC::FCC_UGE;
95 case ISD::SETUO: return SPCC::FCC_U;
96 case ISD::SETO: return SPCC::FCC_O;
97 case ISD::SETONE: return SPCC::FCC_LG;
98 case ISD::SETUEQ: return SPCC::FCC_UE;
103 class SparcTargetLowering : public TargetLowering {
104 int VarArgsFrameOffset; // Frame offset to start of varargs area.
106 SparcTargetLowering(TargetMachine &TM);
107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
110 /// in Mask are known to be either zero or one and return them in the
111 /// KnownZero/KnownOne bitsets.
112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
116 const SelectionDAG &DAG,
117 unsigned Depth = 0) const;
119 virtual std::vector<SDOperand>
120 LowerArguments(Function &F, SelectionDAG &DAG);
121 virtual std::pair<SDOperand, SDOperand>
122 LowerCallTo(SDOperand Chain, const Type *RetTy,
123 bool RetSExt, bool RetZExt, bool isVarArg,
124 unsigned CC, bool isTailCall, SDOperand Callee,
125 ArgListTy &Args, SelectionDAG &DAG);
126 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
127 MachineBasicBlock *MBB);
129 virtual const char *getTargetNodeName(unsigned Opcode) const;
133 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
134 : TargetLowering(TM) {
136 // Set up the register classes.
137 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
138 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
139 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
141 // Turn FP extload into load/fextend
142 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
143 // Sparc doesn't have i1 sign extending load
144 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
145 // Turn FP truncstore into trunc + store.
146 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
148 // Custom legalize GlobalAddress nodes into LO/HI parts.
149 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
150 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
151 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
153 // Sparc doesn't have sext_inreg, replace them with shl/sra
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
158 // Sparc has no REM or DIVREM operations.
159 setOperationAction(ISD::UREM, MVT::i32, Expand);
160 setOperationAction(ISD::SREM, MVT::i32, Expand);
161 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
162 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
164 // Custom expand fp<->sint
165 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
166 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
169 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
170 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
172 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
173 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
175 // Sparc has no select or setcc: expand to SELECT_CC.
176 setOperationAction(ISD::SELECT, MVT::i32, Expand);
177 setOperationAction(ISD::SELECT, MVT::f32, Expand);
178 setOperationAction(ISD::SELECT, MVT::f64, Expand);
179 setOperationAction(ISD::SETCC, MVT::i32, Expand);
180 setOperationAction(ISD::SETCC, MVT::f32, Expand);
181 setOperationAction(ISD::SETCC, MVT::f64, Expand);
183 // Sparc doesn't have BRCOND either, it has BR_CC.
184 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
185 setOperationAction(ISD::BRIND, MVT::Other, Expand);
186 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
187 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
188 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
189 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
191 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
192 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
193 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
195 // SPARC has no intrinsics for these particular operations.
196 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
197 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
198 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
199 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
201 setOperationAction(ISD::FSIN , MVT::f64, Expand);
202 setOperationAction(ISD::FCOS , MVT::f64, Expand);
203 setOperationAction(ISD::FREM , MVT::f64, Expand);
204 setOperationAction(ISD::FSIN , MVT::f32, Expand);
205 setOperationAction(ISD::FCOS , MVT::f32, Expand);
206 setOperationAction(ISD::FREM , MVT::f32, Expand);
207 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
208 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
209 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
210 setOperationAction(ISD::ROTL , MVT::i32, Expand);
211 setOperationAction(ISD::ROTR , MVT::i32, Expand);
212 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
213 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
214 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
215 setOperationAction(ISD::FPOW , MVT::f64, Expand);
216 setOperationAction(ISD::FPOW , MVT::f32, Expand);
218 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
219 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
220 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
222 // FIXME: Sparc provides these multiplies, but we don't have them yet.
223 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
225 // We don't have line number support yet.
226 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
227 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
228 setOperationAction(ISD::LABEL, MVT::Other, Expand);
230 // RET must be custom lowered, to meet ABI requirements
231 setOperationAction(ISD::RET , MVT::Other, Custom);
233 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
234 setOperationAction(ISD::VASTART , MVT::Other, Custom);
235 // VAARG needs to be lowered to not do unaligned accesses for doubles.
236 setOperationAction(ISD::VAARG , MVT::Other, Custom);
238 // Use the default implementation.
239 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
240 setOperationAction(ISD::VAEND , MVT::Other, Expand);
241 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
242 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
243 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
245 // No debug info support yet.
246 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
247 setOperationAction(ISD::LABEL, MVT::Other, Expand);
248 setOperationAction(ISD::DECLARE, MVT::Other, Expand);
250 setStackPointerRegisterToSaveRestore(SP::O6);
252 if (TM.getSubtarget<SparcSubtarget>().isV9())
253 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
255 computeRegisterProperties();
258 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
261 case SPISD::CMPICC: return "SPISD::CMPICC";
262 case SPISD::CMPFCC: return "SPISD::CMPFCC";
263 case SPISD::BRICC: return "SPISD::BRICC";
264 case SPISD::BRFCC: return "SPISD::BRFCC";
265 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
266 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
267 case SPISD::Hi: return "SPISD::Hi";
268 case SPISD::Lo: return "SPISD::Lo";
269 case SPISD::FTOI: return "SPISD::FTOI";
270 case SPISD::ITOF: return "SPISD::ITOF";
271 case SPISD::CALL: return "SPISD::CALL";
272 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
276 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
277 /// be zero. Op is expected to be a target specific node. Used by DAG
279 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
283 const SelectionDAG &DAG,
284 unsigned Depth) const {
285 APInt KnownZero2, KnownOne2;
286 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
288 switch (Op.getOpcode()) {
290 case SPISD::SELECT_ICC:
291 case SPISD::SELECT_FCC:
292 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
294 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
296 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
297 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
299 // Only known if known in both the LHS and RHS.
300 KnownOne &= KnownOne2;
301 KnownZero &= KnownZero2;
306 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
307 /// either one or two GPRs, including FP values. TODO: we should pass FP values
308 /// in FP registers for fastcc functions.
309 std::vector<SDOperand>
310 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
311 MachineFunction &MF = DAG.getMachineFunction();
312 MachineRegisterInfo &RegInfo = MF.getRegInfo();
313 std::vector<SDOperand> ArgValues;
315 static const unsigned ArgRegs[] = {
316 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
319 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
320 unsigned ArgOffset = 68;
322 SDOperand Root = DAG.getRoot();
323 std::vector<SDOperand> OutChains;
325 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
326 MVT::ValueType ObjectVT = getValueType(I->getType());
329 default: assert(0 && "Unhandled argument type!");
334 if (I->use_empty()) { // Argument is dead.
335 if (CurArgReg < ArgRegEnd) ++CurArgReg;
336 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
337 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
338 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
339 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
340 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
341 if (ObjectVT != MVT::i32) {
342 unsigned AssertOp = ISD::AssertSext;
343 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
344 DAG.getValueType(ObjectVT));
345 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
347 ArgValues.push_back(Arg);
349 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
350 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
352 if (ObjectVT == MVT::i32) {
353 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
355 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
357 // Sparc is big endian, so add an offset based on the ObjectVT.
358 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
359 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
360 DAG.getConstant(Offset, MVT::i32));
361 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
363 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
365 ArgValues.push_back(Load);
371 if (I->use_empty()) { // Argument is dead.
372 if (CurArgReg < ArgRegEnd) ++CurArgReg;
373 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
374 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
375 // FP value is passed in an integer register.
376 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
377 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
378 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
380 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
381 ArgValues.push_back(Arg);
383 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
384 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
385 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
386 ArgValues.push_back(Load);
393 if (I->use_empty()) { // Argument is dead.
394 if (CurArgReg < ArgRegEnd) ++CurArgReg;
395 if (CurArgReg < ArgRegEnd) ++CurArgReg;
396 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
397 } else if (/* FIXME: Apparently this isn't safe?? */
398 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
399 ((CurArgReg-ArgRegs) & 1) == 0) {
400 // If this is a double argument and the whole thing lives on the stack,
401 // and the argument is aligned, load the double straight from the stack.
402 // We can't do a load in cases like void foo([6ints], int,double),
403 // because the double wouldn't be aligned!
404 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
405 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
406 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
409 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
410 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
411 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
412 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
414 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
415 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
416 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
420 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
421 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
422 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
423 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
425 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
426 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
427 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
430 // Compose the two halves together into an i64 unit.
431 SDOperand WholeValue =
432 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
434 // If we want a double, do a bit convert.
435 if (ObjectVT == MVT::f64)
436 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
438 ArgValues.push_back(WholeValue);
445 // Store remaining ArgRegs to the stack if this is a varargs function.
446 if (F.getFunctionType()->isVarArg()) {
447 // Remember the vararg offset for the va_start implementation.
448 VarArgsFrameOffset = ArgOffset;
450 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
451 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
452 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
453 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
455 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
456 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
458 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
463 if (!OutChains.empty())
464 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
465 &OutChains[0], OutChains.size()));
467 // Finally, inform the code generator which regs we return values in.
468 switch (getValueType(F.getReturnType())) {
469 default: assert(0 && "Unknown type!");
470 case MVT::isVoid: break;
475 MF.getRegInfo().addLiveOut(SP::I0);
478 MF.getRegInfo().addLiveOut(SP::I0);
479 MF.getRegInfo().addLiveOut(SP::I1);
482 MF.getRegInfo().addLiveOut(SP::F0);
485 MF.getRegInfo().addLiveOut(SP::D0);
492 std::pair<SDOperand, SDOperand>
493 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
494 bool RetSExt, bool RetZExt, bool isVarArg,
495 unsigned CC, bool isTailCall, SDOperand Callee,
496 ArgListTy &Args, SelectionDAG &DAG) {
497 // Count the size of the outgoing arguments.
498 unsigned ArgsSize = 0;
499 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
500 switch (getValueType(Args[i].Ty)) {
501 default: assert(0 && "Unknown value type!");
516 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
520 // Keep stack frames 8-byte aligned.
521 ArgsSize = (ArgsSize+7) & ~7;
523 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
526 std::vector<SDOperand> Stores;
527 std::vector<SDOperand> RegValuesToPass;
528 unsigned ArgOffset = 68;
529 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
530 SDOperand Val = Args[i].Node;
531 MVT::ValueType ObjectVT = Val.getValueType();
532 SDOperand ValToStore(0, 0);
535 default: assert(0 && "Unhandled argument type!");
539 // Promote the integer to 32-bits. If the input type is signed, use a
540 // sign extend, otherwise use a zero extend.
541 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
543 ExtendKind = ISD::SIGN_EXTEND;
544 else if (Args[i].isZExt)
545 ExtendKind = ISD::ZERO_EXTEND;
546 Val = DAG.getNode(ExtendKind, MVT::i32, Val);
552 if (RegValuesToPass.size() >= 6) {
555 RegValuesToPass.push_back(Val);
560 if (RegValuesToPass.size() >= 6) {
563 // Convert this to a FP value in an int reg.
564 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
565 RegValuesToPass.push_back(Val);
570 // If we can store this directly into the outgoing slot, do so. We can
571 // do this when all ArgRegs are used and if the outgoing slot is aligned.
572 // FIXME: McGill/misr fails with this.
573 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
578 // Otherwise, convert this to a FP value in int regs.
579 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
583 if (RegValuesToPass.size() >= 6) {
584 ValToStore = Val; // Whole thing is passed in memory.
588 // Split the value into top and bottom part. Top part goes in a reg.
589 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
590 DAG.getConstant(1, MVT::i32));
591 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
592 DAG.getConstant(0, MVT::i32));
593 RegValuesToPass.push_back(Hi);
595 if (RegValuesToPass.size() >= 6) {
600 RegValuesToPass.push_back(Lo);
605 if (ValToStore.Val) {
607 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
609 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
610 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
611 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
613 ArgOffset += ObjSize;
616 // Emit all stores, make sure the occur before any copies into physregs.
618 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
620 static const unsigned ArgRegs[] = {
621 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
624 // Build a sequence of copy-to-reg nodes chained together with token chain
625 // and flag operands which copy the outgoing args into O[0-5].
627 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
628 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
629 InFlag = Chain.getValue(1);
632 // If the callee is a GlobalAddress node (quite common, every direct call is)
633 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
634 // Likewise ExternalSymbol -> TargetExternalSymbol.
635 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
636 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
637 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
638 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
640 std::vector<MVT::ValueType> NodeTys;
641 NodeTys.push_back(MVT::Other); // Returns a chain
642 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
643 SDOperand Ops[] = { Chain, Callee, InFlag };
644 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
645 InFlag = Chain.getValue(1);
647 MVT::ValueType RetTyVT = getValueType(RetTy);
649 if (RetTyVT != MVT::isVoid) {
651 default: assert(0 && "Unknown value type to return!");
655 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
656 Chain = RetVal.getValue(1);
658 // Add a note to keep track of whether it is sign or zero extended.
659 ISD::NodeType AssertKind = ISD::DELETED_NODE;
661 AssertKind = ISD::AssertSext;
663 AssertKind = ISD::AssertZext;
665 if (AssertKind != ISD::DELETED_NODE)
666 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
667 DAG.getValueType(RetTyVT));
669 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
673 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
674 Chain = RetVal.getValue(1);
677 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
678 Chain = RetVal.getValue(1);
681 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
682 Chain = RetVal.getValue(1);
685 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
686 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
688 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
689 Chain = Hi.getValue(1);
694 Chain = DAG.getCALLSEQ_END(Chain,
695 DAG.getConstant(ArgsSize, getPointerTy()),
696 DAG.getConstant(0, getPointerTy()),
698 return std::make_pair(RetVal, Chain);
701 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
702 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
703 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
704 ISD::CondCode CC, unsigned &SPCC) {
705 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
707 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
708 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
709 (LHS.getOpcode() == SPISD::SELECT_FCC &&
710 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
711 isa<ConstantSDNode>(LHS.getOperand(0)) &&
712 isa<ConstantSDNode>(LHS.getOperand(1)) &&
713 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
714 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
715 SDOperand CMPCC = LHS.getOperand(3);
716 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
717 LHS = CMPCC.getOperand(0);
718 RHS = CMPCC.getOperand(1);
723 SDOperand SparcTargetLowering::
724 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
725 switch (Op.getOpcode()) {
726 default: assert(0 && "Should not custom lower this!");
727 case ISD::GlobalTLSAddress:
728 assert(0 && "TLS not implemented for Sparc.");
729 case ISD::GlobalAddress: {
730 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
731 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
732 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
733 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
734 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
736 case ISD::ConstantPool: {
737 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
738 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
739 cast<ConstantPoolSDNode>(Op)->getAlignment());
740 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
741 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
742 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
744 case ISD::FP_TO_SINT:
745 // Convert the fp value to integer in an FP register.
746 assert(Op.getValueType() == MVT::i32);
747 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
748 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
749 case ISD::SINT_TO_FP: {
750 assert(Op.getOperand(0).getValueType() == MVT::i32);
751 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
752 // Convert the int value to FP in an FP register.
753 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
756 SDOperand Chain = Op.getOperand(0);
757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
758 SDOperand LHS = Op.getOperand(2);
759 SDOperand RHS = Op.getOperand(3);
760 SDOperand Dest = Op.getOperand(4);
761 unsigned Opc, SPCC = ~0U;
763 // If this is a br_cc of a "setcc", and if the setcc got lowered into
764 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
765 LookThroughSetCC(LHS, RHS, CC, SPCC);
767 // Get the condition flag.
768 SDOperand CompareFlag;
769 if (LHS.getValueType() == MVT::i32) {
770 std::vector<MVT::ValueType> VTs;
771 VTs.push_back(MVT::i32);
772 VTs.push_back(MVT::Flag);
773 SDOperand Ops[2] = { LHS, RHS };
774 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
775 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
778 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
779 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
782 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
783 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
785 case ISD::SELECT_CC: {
786 SDOperand LHS = Op.getOperand(0);
787 SDOperand RHS = Op.getOperand(1);
788 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
789 SDOperand TrueVal = Op.getOperand(2);
790 SDOperand FalseVal = Op.getOperand(3);
791 unsigned Opc, SPCC = ~0U;
793 // If this is a select_cc of a "setcc", and if the setcc got lowered into
794 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
795 LookThroughSetCC(LHS, RHS, CC, SPCC);
797 SDOperand CompareFlag;
798 if (LHS.getValueType() == MVT::i32) {
799 std::vector<MVT::ValueType> VTs;
800 VTs.push_back(LHS.getValueType()); // subcc returns a value
801 VTs.push_back(MVT::Flag);
802 SDOperand Ops[2] = { LHS, RHS };
803 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
804 Opc = SPISD::SELECT_ICC;
805 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
807 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
808 Opc = SPISD::SELECT_FCC;
809 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
811 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
812 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
815 // vastart just stores the address of the VarArgsFrameIndex slot into the
816 // memory location argument.
817 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
818 DAG.getRegister(SP::I6, MVT::i32),
819 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
820 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
821 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
824 SDNode *Node = Op.Val;
825 MVT::ValueType VT = Node->getValueType(0);
826 SDOperand InChain = Node->getOperand(0);
827 SDOperand VAListPtr = Node->getOperand(1);
828 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
829 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0);
830 // Increment the pointer, VAList, to the next vaarg
831 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
832 DAG.getConstant(MVT::getSizeInBits(VT)/8,
834 // Store the incremented VAList to the legalized pointer
835 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
837 // Load the actual argument out of the pointer VAList, unless this is an
839 if (VT != MVT::f64) {
840 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
842 // Otherwise, load it as i64, then do a bitconvert.
843 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
844 std::vector<MVT::ValueType> Tys;
845 Tys.push_back(MVT::f64);
846 Tys.push_back(MVT::Other);
847 // Bit-Convert the value to f64.
848 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
850 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
853 case ISD::DYNAMIC_STACKALLOC: {
854 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
855 SDOperand Size = Op.getOperand(1); // Legalize the size.
857 unsigned SPReg = SP::O6;
858 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
859 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
860 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
862 // The resultant pointer is actually 16 words from the bottom of the stack,
863 // to provide a register spill area.
864 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
865 DAG.getConstant(96, MVT::i32));
866 std::vector<MVT::ValueType> Tys;
867 Tys.push_back(MVT::i32);
868 Tys.push_back(MVT::Other);
869 SDOperand Ops[2] = { NewVal, Chain };
870 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
875 switch(Op.getNumOperands()) {
877 assert(0 && "Do not know how to return this many arguments!");
880 return SDOperand(); // ret void is legal
883 switch(Op.getOperand(1).getValueType()) {
884 default: assert(0 && "Unknown type to return!");
885 case MVT::i32: ArgReg = SP::I0; break;
886 case MVT::f32: ArgReg = SP::F0; break;
887 case MVT::f64: ArgReg = SP::D0; break;
889 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
894 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
896 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
899 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
901 // Frame & Return address. Currently unimplemented
902 case ISD::RETURNADDR: break;
903 case ISD::FRAMEADDR: break;
909 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
910 MachineBasicBlock *BB) {
911 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
914 // Figure out the conditional branch opcode to use for this select_cc.
915 switch (MI->getOpcode()) {
916 default: assert(0 && "Unknown SELECT_CC!");
917 case SP::SELECT_CC_Int_ICC:
918 case SP::SELECT_CC_FP_ICC:
919 case SP::SELECT_CC_DFP_ICC:
920 BROpcode = SP::BCOND;
922 case SP::SELECT_CC_Int_FCC:
923 case SP::SELECT_CC_FP_FCC:
924 case SP::SELECT_CC_DFP_FCC:
925 BROpcode = SP::FBCOND;
929 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
931 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
932 // control-flow pattern. The incoming instruction knows the destination vreg
933 // to set, the condition code register to branch on, the true/false values to
934 // select between, and a branch opcode to use.
935 const BasicBlock *LLVM_BB = BB->getBasicBlock();
936 ilist<MachineBasicBlock>::iterator It = BB;
943 // fallthrough --> copy0MBB
944 MachineBasicBlock *thisMBB = BB;
945 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
946 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
947 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
948 MachineFunction *F = BB->getParent();
949 F->getBasicBlockList().insert(It, copy0MBB);
950 F->getBasicBlockList().insert(It, sinkMBB);
951 // Update machine-CFG edges by first adding all successors of the current
952 // block to the new block which will contain the Phi node for the select.
953 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
954 e = BB->succ_end(); i != e; ++i)
955 sinkMBB->addSuccessor(*i);
956 // Next, remove all successors of the current block, and add the true
957 // and fallthrough blocks as its successors.
958 while(!BB->succ_empty())
959 BB->removeSuccessor(BB->succ_begin());
960 BB->addSuccessor(copy0MBB);
961 BB->addSuccessor(sinkMBB);
965 // # fallthrough to sinkMBB
968 // Update machine-CFG edges
969 BB->addSuccessor(sinkMBB);
972 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
975 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
976 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
977 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
979 delete MI; // The pseudo instruction is gone now.
983 //===----------------------------------------------------------------------===//
984 // Instruction Selector Implementation
985 //===----------------------------------------------------------------------===//
987 //===--------------------------------------------------------------------===//
988 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
989 /// instructions for SelectionDAG operations.
992 class SparcDAGToDAGISel : public SelectionDAGISel {
993 SparcTargetLowering Lowering;
995 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
996 /// make the right decision when generating code for different targets.
997 const SparcSubtarget &Subtarget;
999 SparcDAGToDAGISel(TargetMachine &TM)
1000 : SelectionDAGISel(Lowering), Lowering(TM),
1001 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
1004 SDNode *Select(SDOperand Op);
1006 // Complex Pattern Selectors.
1007 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
1008 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
1011 /// InstructionSelectBasicBlock - This callback is invoked by
1012 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1013 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
1015 virtual const char *getPassName() const {
1016 return "SPARC DAG->DAG Pattern Instruction Selection";
1019 // Include the pieces autogenerated from the target description.
1020 #include "SparcGenDAGISel.inc"
1022 } // end anonymous namespace
1024 /// InstructionSelectBasicBlock - This callback is invoked by
1025 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1026 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1029 // Select target instructions for the DAG.
1030 DAG.setRoot(SelectRoot(DAG.getRoot()));
1031 DAG.RemoveDeadNodes();
1033 // Emit machine code to BB.
1034 ScheduleAndEmitDAG(DAG);
1037 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1038 SDOperand &Base, SDOperand &Offset) {
1039 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1040 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1041 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1044 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1045 Addr.getOpcode() == ISD::TargetGlobalAddress)
1046 return false; // direct calls.
1048 if (Addr.getOpcode() == ISD::ADD) {
1049 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1050 if (Predicate_simm13(CN)) {
1051 if (FrameIndexSDNode *FIN =
1052 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1053 // Constant offset from frame ref.
1054 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1056 Base = Addr.getOperand(0);
1058 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1062 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1063 Base = Addr.getOperand(1);
1064 Offset = Addr.getOperand(0).getOperand(0);
1067 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1068 Base = Addr.getOperand(0);
1069 Offset = Addr.getOperand(1).getOperand(0);
1074 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1078 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1079 SDOperand &R1, SDOperand &R2) {
1080 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1081 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1082 Addr.getOpcode() == ISD::TargetGlobalAddress)
1083 return false; // direct calls.
1085 if (Addr.getOpcode() == ISD::ADD) {
1086 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1087 Predicate_simm13(Addr.getOperand(1).Val))
1088 return false; // Let the reg+imm pattern catch this!
1089 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1090 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1091 return false; // Let the reg+imm pattern catch this!
1092 R1 = Addr.getOperand(0);
1093 R2 = Addr.getOperand(1);
1098 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1102 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1104 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1105 N->getOpcode() < SPISD::FIRST_NUMBER)
1106 return NULL; // Already selected.
1108 switch (N->getOpcode()) {
1112 // FIXME: should use a custom expander to expose the SRA to the dag.
1113 SDOperand DivLHS = N->getOperand(0);
1114 SDOperand DivRHS = N->getOperand(1);
1115 AddToISelQueue(DivLHS);
1116 AddToISelQueue(DivRHS);
1118 // Set the Y register to the high-part.
1120 if (N->getOpcode() == ISD::SDIV) {
1121 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1122 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1124 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1126 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1127 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1129 // FIXME: Handle div by immediate.
1130 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1131 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1136 // FIXME: Handle mul by immediate.
1137 SDOperand MulLHS = N->getOperand(0);
1138 SDOperand MulRHS = N->getOperand(1);
1139 AddToISelQueue(MulLHS);
1140 AddToISelQueue(MulRHS);
1141 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1142 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1144 // The high part is in the Y register.
1145 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1150 return SelectCode(Op);
1154 /// createSparcISelDag - This pass converts a legalized DAG into a
1155 /// SPARC-specific DAG, ready for instruction scheduling.
1157 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1158 return new SparcDAGToDAGISel(TM);