1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcISelLowering.h"
15 #include "SparcTargetMachine.h"
16 #include "llvm/Intrinsics.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
24 //===----------------------------------------------------------------------===//
25 // Instruction Selector Implementation
26 //===----------------------------------------------------------------------===//
28 //===--------------------------------------------------------------------===//
29 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
30 /// instructions for SelectionDAG operations.
33 class SparcDAGToDAGISel : public SelectionDAGISel {
34 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
35 /// make the right decision when generating code for different targets.
36 const SparcSubtarget &Subtarget;
37 SparcTargetMachine& TM;
39 explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
40 : SelectionDAGISel(tm),
41 Subtarget(tm.getSubtarget<SparcSubtarget>()),
45 SDNode *Select(SDNode *N);
47 // Complex Pattern Selectors.
48 bool SelectADDRrr(SDNode *Op, SDValue N, SDValue &R1, SDValue &R2);
49 bool SelectADDRri(SDNode *Op, SDValue N, SDValue &Base,
52 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
53 /// inline asm expressions.
54 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
56 std::vector<SDValue> &OutOps);
58 virtual const char *getPassName() const {
59 return "SPARC DAG->DAG Pattern Instruction Selection";
62 // Include the pieces autogenerated from the target description.
63 #include "SparcGenDAGISel.inc"
66 SDNode* getGlobalBaseReg();
68 } // end anonymous namespace
70 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
71 MachineFunction *MF = BB->getParent();
72 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
73 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
76 bool SparcDAGToDAGISel::SelectADDRri(SDNode *Op, SDValue Addr,
77 SDValue &Base, SDValue &Offset) {
78 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
79 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
80 Offset = CurDAG->getTargetConstant(0, MVT::i32);
83 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
84 Addr.getOpcode() == ISD::TargetGlobalAddress)
85 return false; // direct calls.
87 if (Addr.getOpcode() == ISD::ADD) {
88 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
89 if (Predicate_simm13(CN)) {
90 if (FrameIndexSDNode *FIN =
91 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 // Constant offset from frame ref.
93 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
95 Base = Addr.getOperand(0);
97 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
102 Base = Addr.getOperand(1);
103 Offset = Addr.getOperand(0).getOperand(0);
106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
107 Base = Addr.getOperand(0);
108 Offset = Addr.getOperand(1).getOperand(0);
113 Offset = CurDAG->getTargetConstant(0, MVT::i32);
117 bool SparcDAGToDAGISel::SelectADDRrr(SDNode *Op, SDValue Addr,
118 SDValue &R1, SDValue &R2) {
119 if (Addr.getOpcode() == ISD::FrameIndex) return false;
120 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
121 Addr.getOpcode() == ISD::TargetGlobalAddress)
122 return false; // direct calls.
124 if (Addr.getOpcode() == ISD::ADD) {
125 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
126 Predicate_simm13(Addr.getOperand(1).getNode()))
127 return false; // Let the reg+imm pattern catch this!
128 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
129 Addr.getOperand(1).getOpcode() == SPISD::Lo)
130 return false; // Let the reg+imm pattern catch this!
131 R1 = Addr.getOperand(0);
132 R2 = Addr.getOperand(1);
137 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
141 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
142 DebugLoc dl = N->getDebugLoc();
143 if (N->isMachineOpcode())
144 return NULL; // Already selected.
146 switch (N->getOpcode()) {
148 case SPISD::GLOBAL_BASE_REG:
149 return getGlobalBaseReg();
153 // FIXME: should use a custom expander to expose the SRA to the dag.
154 SDValue DivLHS = N->getOperand(0);
155 SDValue DivRHS = N->getOperand(1);
157 // Set the Y register to the high-part.
159 if (N->getOpcode() == ISD::SDIV) {
160 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
161 CurDAG->getTargetConstant(31, MVT::i32)), 0);
163 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
165 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Flag, TopPart,
166 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
168 // FIXME: Handle div by immediate.
169 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
170 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
175 // FIXME: Handle mul by immediate.
176 SDValue MulLHS = N->getOperand(0);
177 SDValue MulRHS = N->getOperand(1);
178 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
179 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
181 // The high part is in the Y register.
182 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
187 return SelectCode(N);
191 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
192 /// inline asm expressions.
194 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
196 std::vector<SDValue> &OutOps) {
198 switch (ConstraintCode) {
199 default: return true;
201 if (!SelectADDRrr(Op.getNode(), Op, Op0, Op1))
202 SelectADDRri(Op.getNode(), Op, Op0, Op1);
206 OutOps.push_back(Op0);
207 OutOps.push_back(Op1);
211 /// createSparcISelDag - This pass converts a legalized DAG into a
212 /// SPARC-specific DAG, ready for instruction scheduling.
214 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
215 return new SparcDAGToDAGISel(TM);