1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
31 //===----------------------------------------------------------------------===//
32 // TargetLowering Implementation
33 //===----------------------------------------------------------------------===//
37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
38 CMPICC, // Compare two GPR operands, set icc.
39 CMPFCC, // Compare two FP operands, set fcc.
40 BRICC, // Branch to dest on icc condition
41 BRFCC, // Branch to dest on fcc condition
42 SELECT_ICC, // Select between two values using the current ICC flags.
43 SELECT_FCC, // Select between two values using the current FCC flags.
45 Hi, Lo, // Hi/Lo operations, typically on a global address.
47 FTOI, // FP to Int within a FP register.
48 ITOF, // Int to FP within a FP register.
50 CALL, // A call instruction.
51 RET_FLAG // Return with a flag operand.
55 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
57 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
59 default: assert(0 && "Unknown integer condition code!");
60 case ISD::SETEQ: return SPCC::ICC_E;
61 case ISD::SETNE: return SPCC::ICC_NE;
62 case ISD::SETLT: return SPCC::ICC_L;
63 case ISD::SETGT: return SPCC::ICC_G;
64 case ISD::SETLE: return SPCC::ICC_LE;
65 case ISD::SETGE: return SPCC::ICC_GE;
66 case ISD::SETULT: return SPCC::ICC_CS;
67 case ISD::SETULE: return SPCC::ICC_LEU;
68 case ISD::SETUGT: return SPCC::ICC_GU;
69 case ISD::SETUGE: return SPCC::ICC_CC;
73 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
75 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
77 default: assert(0 && "Unknown fp condition code!");
79 case ISD::SETOEQ: return SPCC::FCC_E;
81 case ISD::SETUNE: return SPCC::FCC_NE;
83 case ISD::SETOLT: return SPCC::FCC_L;
85 case ISD::SETOGT: return SPCC::FCC_G;
87 case ISD::SETOLE: return SPCC::FCC_LE;
89 case ISD::SETOGE: return SPCC::FCC_GE;
90 case ISD::SETULT: return SPCC::FCC_UL;
91 case ISD::SETULE: return SPCC::FCC_ULE;
92 case ISD::SETUGT: return SPCC::FCC_UG;
93 case ISD::SETUGE: return SPCC::FCC_UGE;
94 case ISD::SETUO: return SPCC::FCC_U;
95 case ISD::SETO: return SPCC::FCC_O;
96 case ISD::SETONE: return SPCC::FCC_LG;
97 case ISD::SETUEQ: return SPCC::FCC_UE;
102 class SparcTargetLowering : public TargetLowering {
103 int VarArgsFrameOffset; // Frame offset to start of varargs area.
105 SparcTargetLowering(TargetMachine &TM);
106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
109 /// in Mask are known to be either zero or one and return them in the
110 /// KnownZero/KnownOne bitsets.
111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
115 const SelectionDAG &DAG,
116 unsigned Depth = 0) const;
118 virtual std::vector<SDOperand>
119 LowerArguments(Function &F, SelectionDAG &DAG);
120 virtual std::pair<SDOperand, SDOperand>
121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
122 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
123 ArgListTy &Args, SelectionDAG &DAG);
124 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
125 MachineBasicBlock *MBB);
127 virtual const char *getTargetNodeName(unsigned Opcode) const;
131 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
132 : TargetLowering(TM) {
134 // Set up the register classes.
135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
139 // Turn FP extload into load/fextend
140 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
142 // Custom legalize GlobalAddress nodes into LO/HI parts.
143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
144 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
145 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
147 // Sparc doesn't have sext_inreg, replace them with shl/sra
148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
152 // Sparc has no REM or DIVREM operations.
153 setOperationAction(ISD::UREM, MVT::i32, Expand);
154 setOperationAction(ISD::SREM, MVT::i32, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 // Custom expand fp<->sint
159 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
160 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
163 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
164 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
166 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
167 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
169 // Sparc has no select or setcc: expand to SELECT_CC.
170 setOperationAction(ISD::SELECT, MVT::i32, Expand);
171 setOperationAction(ISD::SELECT, MVT::f32, Expand);
172 setOperationAction(ISD::SELECT, MVT::f64, Expand);
173 setOperationAction(ISD::SETCC, MVT::i32, Expand);
174 setOperationAction(ISD::SETCC, MVT::f32, Expand);
175 setOperationAction(ISD::SETCC, MVT::f64, Expand);
177 // Sparc doesn't have BRCOND either, it has BR_CC.
178 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
179 setOperationAction(ISD::BRIND, MVT::Other, Expand);
180 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
181 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
182 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
183 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
185 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
186 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
187 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
189 // SPARC has no intrinsics for these particular operations.
190 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
191 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
192 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
194 setOperationAction(ISD::FSIN , MVT::f64, Expand);
195 setOperationAction(ISD::FCOS , MVT::f64, Expand);
196 setOperationAction(ISD::FREM , MVT::f64, Expand);
197 setOperationAction(ISD::FSIN , MVT::f32, Expand);
198 setOperationAction(ISD::FCOS , MVT::f32, Expand);
199 setOperationAction(ISD::FREM , MVT::f32, Expand);
200 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
201 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
202 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
203 setOperationAction(ISD::ROTL , MVT::i32, Expand);
204 setOperationAction(ISD::ROTR , MVT::i32, Expand);
205 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
206 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
207 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
208 setOperationAction(ISD::FPOW , MVT::f64, Expand);
209 setOperationAction(ISD::FPOW , MVT::f32, Expand);
211 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
212 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
213 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
215 // We don't have line number support yet.
216 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
217 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
218 setOperationAction(ISD::LABEL, MVT::Other, Expand);
220 // RET must be custom lowered, to meet ABI requirements
221 setOperationAction(ISD::RET , MVT::Other, Custom);
223 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
224 setOperationAction(ISD::VASTART , MVT::Other, Custom);
225 // VAARG needs to be lowered to not do unaligned accesses for doubles.
226 setOperationAction(ISD::VAARG , MVT::Other, Custom);
228 // Use the default implementation.
229 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
230 setOperationAction(ISD::VAEND , MVT::Other, Expand);
231 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
232 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
233 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
235 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
236 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
238 setStackPointerRegisterToSaveRestore(SP::O6);
240 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
241 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
244 computeRegisterProperties();
247 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
250 case SPISD::CMPICC: return "SPISD::CMPICC";
251 case SPISD::CMPFCC: return "SPISD::CMPFCC";
252 case SPISD::BRICC: return "SPISD::BRICC";
253 case SPISD::BRFCC: return "SPISD::BRFCC";
254 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
255 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
256 case SPISD::Hi: return "SPISD::Hi";
257 case SPISD::Lo: return "SPISD::Lo";
258 case SPISD::FTOI: return "SPISD::FTOI";
259 case SPISD::ITOF: return "SPISD::ITOF";
260 case SPISD::CALL: return "SPISD::CALL";
261 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
265 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
266 /// be zero. Op is expected to be a target specific node. Used by DAG
268 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
272 const SelectionDAG &DAG,
273 unsigned Depth) const {
274 uint64_t KnownZero2, KnownOne2;
275 KnownZero = KnownOne = 0; // Don't know anything.
277 switch (Op.getOpcode()) {
279 case SPISD::SELECT_ICC:
280 case SPISD::SELECT_FCC:
281 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
283 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
285 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
286 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
288 // Only known if known in both the LHS and RHS.
289 KnownOne &= KnownOne2;
290 KnownZero &= KnownZero2;
295 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
296 /// either one or two GPRs, including FP values. TODO: we should pass FP values
297 /// in FP registers for fastcc functions.
298 std::vector<SDOperand>
299 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
300 MachineFunction &MF = DAG.getMachineFunction();
301 MachineRegisterInfo &RegInfo = MF.getRegInfo();
302 std::vector<SDOperand> ArgValues;
304 static const unsigned ArgRegs[] = {
305 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
308 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
309 unsigned ArgOffset = 68;
311 SDOperand Root = DAG.getRoot();
312 std::vector<SDOperand> OutChains;
314 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
315 MVT::ValueType ObjectVT = getValueType(I->getType());
318 default: assert(0 && "Unhandled argument type!");
323 if (I->use_empty()) { // Argument is dead.
324 if (CurArgReg < ArgRegEnd) ++CurArgReg;
325 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
326 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
327 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
328 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
329 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
330 if (ObjectVT != MVT::i32) {
331 unsigned AssertOp = ISD::AssertSext;
332 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
333 DAG.getValueType(ObjectVT));
334 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
336 ArgValues.push_back(Arg);
338 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
339 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
341 if (ObjectVT == MVT::i32) {
342 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
344 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
346 // Sparc is big endian, so add an offset based on the ObjectVT.
347 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
348 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
349 DAG.getConstant(Offset, MVT::i32));
350 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
352 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
354 ArgValues.push_back(Load);
360 if (I->use_empty()) { // Argument is dead.
361 if (CurArgReg < ArgRegEnd) ++CurArgReg;
362 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
363 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
364 // FP value is passed in an integer register.
365 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
366 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
367 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
369 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
370 ArgValues.push_back(Arg);
372 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
373 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
374 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
375 ArgValues.push_back(Load);
382 if (I->use_empty()) { // Argument is dead.
383 if (CurArgReg < ArgRegEnd) ++CurArgReg;
384 if (CurArgReg < ArgRegEnd) ++CurArgReg;
385 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
386 } else if (/* FIXME: Apparently this isn't safe?? */
387 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
388 ((CurArgReg-ArgRegs) & 1) == 0) {
389 // If this is a double argument and the whole thing lives on the stack,
390 // and the argument is aligned, load the double straight from the stack.
391 // We can't do a load in cases like void foo([6ints], int,double),
392 // because the double wouldn't be aligned!
393 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
394 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
395 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
398 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
399 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
400 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
401 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
403 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
404 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
405 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
409 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
410 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
411 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
412 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
414 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
415 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
416 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
419 // Compose the two halves together into an i64 unit.
420 SDOperand WholeValue =
421 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
423 // If we want a double, do a bit convert.
424 if (ObjectVT == MVT::f64)
425 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
427 ArgValues.push_back(WholeValue);
434 // Store remaining ArgRegs to the stack if this is a varargs function.
435 if (F.getFunctionType()->isVarArg()) {
436 // Remember the vararg offset for the va_start implementation.
437 VarArgsFrameOffset = ArgOffset;
439 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
440 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
441 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
442 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
444 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
445 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
447 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
452 if (!OutChains.empty())
453 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
454 &OutChains[0], OutChains.size()));
456 // Finally, inform the code generator which regs we return values in.
457 switch (getValueType(F.getReturnType())) {
458 default: assert(0 && "Unknown type!");
459 case MVT::isVoid: break;
464 MF.getRegInfo().addLiveOut(SP::I0);
467 MF.getRegInfo().addLiveOut(SP::I0);
468 MF.getRegInfo().addLiveOut(SP::I1);
471 MF.getRegInfo().addLiveOut(SP::F0);
474 MF.getRegInfo().addLiveOut(SP::D0);
481 std::pair<SDOperand, SDOperand>
482 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
483 bool RetTyIsSigned, bool isVarArg, unsigned CC,
484 bool isTailCall, SDOperand Callee,
485 ArgListTy &Args, SelectionDAG &DAG) {
486 // Count the size of the outgoing arguments.
487 unsigned ArgsSize = 0;
488 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
489 switch (getValueType(Args[i].Ty)) {
490 default: assert(0 && "Unknown value type!");
505 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
509 // Keep stack frames 8-byte aligned.
510 ArgsSize = (ArgsSize+7) & ~7;
512 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
515 std::vector<SDOperand> Stores;
516 std::vector<SDOperand> RegValuesToPass;
517 unsigned ArgOffset = 68;
518 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
519 SDOperand Val = Args[i].Node;
520 MVT::ValueType ObjectVT = Val.getValueType();
521 SDOperand ValToStore(0, 0);
524 default: assert(0 && "Unhandled argument type!");
528 // Promote the integer to 32-bits. If the input type is signed, use a
529 // sign extend, otherwise use a zero extend.
530 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
532 ExtendKind = ISD::SIGN_EXTEND;
533 else if (Args[i].isZExt)
534 ExtendKind = ISD::ZERO_EXTEND;
535 Val = DAG.getNode(ExtendKind, MVT::i32, Val);
541 if (RegValuesToPass.size() >= 6) {
544 RegValuesToPass.push_back(Val);
549 if (RegValuesToPass.size() >= 6) {
552 // Convert this to a FP value in an int reg.
553 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
554 RegValuesToPass.push_back(Val);
559 // If we can store this directly into the outgoing slot, do so. We can
560 // do this when all ArgRegs are used and if the outgoing slot is aligned.
561 // FIXME: McGill/misr fails with this.
562 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
567 // Otherwise, convert this to a FP value in int regs.
568 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
572 if (RegValuesToPass.size() >= 6) {
573 ValToStore = Val; // Whole thing is passed in memory.
577 // Split the value into top and bottom part. Top part goes in a reg.
578 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
579 DAG.getConstant(1, MVT::i32));
580 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
581 DAG.getConstant(0, MVT::i32));
582 RegValuesToPass.push_back(Hi);
584 if (RegValuesToPass.size() >= 6) {
589 RegValuesToPass.push_back(Lo);
594 if (ValToStore.Val) {
596 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
598 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
599 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
600 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
602 ArgOffset += ObjSize;
605 // Emit all stores, make sure the occur before any copies into physregs.
607 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
609 static const unsigned ArgRegs[] = {
610 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
613 // Build a sequence of copy-to-reg nodes chained together with token chain
614 // and flag operands which copy the outgoing args into O[0-5].
616 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
617 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
618 InFlag = Chain.getValue(1);
621 // If the callee is a GlobalAddress node (quite common, every direct call is)
622 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
623 // Likewise ExternalSymbol -> TargetExternalSymbol.
624 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
625 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
626 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
627 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
629 std::vector<MVT::ValueType> NodeTys;
630 NodeTys.push_back(MVT::Other); // Returns a chain
631 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
632 SDOperand Ops[] = { Chain, Callee, InFlag };
633 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
634 InFlag = Chain.getValue(1);
636 MVT::ValueType RetTyVT = getValueType(RetTy);
638 if (RetTyVT != MVT::isVoid) {
640 default: assert(0 && "Unknown value type to return!");
644 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
645 Chain = RetVal.getValue(1);
647 // Add a note to keep track of whether it is sign or zero extended.
648 ISD::NodeType AssertKind = ISD::AssertZext;
650 AssertKind = ISD::AssertSext;
651 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
652 DAG.getValueType(RetTyVT));
653 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
657 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
658 Chain = RetVal.getValue(1);
661 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
662 Chain = RetVal.getValue(1);
665 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
666 Chain = RetVal.getValue(1);
669 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
670 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
672 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
673 Chain = Hi.getValue(1);
678 Chain = DAG.getCALLSEQ_END(Chain,
679 DAG.getConstant(ArgsSize, getPointerTy()),
680 DAG.getConstant(0, getPointerTy()),
682 return std::make_pair(RetVal, Chain);
685 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
686 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
687 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
688 ISD::CondCode CC, unsigned &SPCC) {
689 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
691 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
692 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
693 (LHS.getOpcode() == SPISD::SELECT_FCC &&
694 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
695 isa<ConstantSDNode>(LHS.getOperand(0)) &&
696 isa<ConstantSDNode>(LHS.getOperand(1)) &&
697 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
698 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
699 SDOperand CMPCC = LHS.getOperand(3);
700 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
701 LHS = CMPCC.getOperand(0);
702 RHS = CMPCC.getOperand(1);
707 SDOperand SparcTargetLowering::
708 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
709 switch (Op.getOpcode()) {
710 default: assert(0 && "Should not custom lower this!");
711 case ISD::GlobalTLSAddress:
712 assert(0 && "TLS not implemented for Sparc.");
713 case ISD::GlobalAddress: {
714 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
715 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
716 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
717 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
718 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
720 case ISD::ConstantPool: {
721 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
722 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
723 cast<ConstantPoolSDNode>(Op)->getAlignment());
724 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
725 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
726 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
728 case ISD::FP_TO_SINT:
729 // Convert the fp value to integer in an FP register.
730 assert(Op.getValueType() == MVT::i32);
731 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
732 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
733 case ISD::SINT_TO_FP: {
734 assert(Op.getOperand(0).getValueType() == MVT::i32);
735 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
736 // Convert the int value to FP in an FP register.
737 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
740 SDOperand Chain = Op.getOperand(0);
741 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
742 SDOperand LHS = Op.getOperand(2);
743 SDOperand RHS = Op.getOperand(3);
744 SDOperand Dest = Op.getOperand(4);
745 unsigned Opc, SPCC = ~0U;
747 // If this is a br_cc of a "setcc", and if the setcc got lowered into
748 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
749 LookThroughSetCC(LHS, RHS, CC, SPCC);
751 // Get the condition flag.
752 SDOperand CompareFlag;
753 if (LHS.getValueType() == MVT::i32) {
754 std::vector<MVT::ValueType> VTs;
755 VTs.push_back(MVT::i32);
756 VTs.push_back(MVT::Flag);
757 SDOperand Ops[2] = { LHS, RHS };
758 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
759 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
762 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
763 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
766 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
767 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
769 case ISD::SELECT_CC: {
770 SDOperand LHS = Op.getOperand(0);
771 SDOperand RHS = Op.getOperand(1);
772 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
773 SDOperand TrueVal = Op.getOperand(2);
774 SDOperand FalseVal = Op.getOperand(3);
775 unsigned Opc, SPCC = ~0U;
777 // If this is a select_cc of a "setcc", and if the setcc got lowered into
778 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
779 LookThroughSetCC(LHS, RHS, CC, SPCC);
781 SDOperand CompareFlag;
782 if (LHS.getValueType() == MVT::i32) {
783 std::vector<MVT::ValueType> VTs;
784 VTs.push_back(LHS.getValueType()); // subcc returns a value
785 VTs.push_back(MVT::Flag);
786 SDOperand Ops[2] = { LHS, RHS };
787 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
788 Opc = SPISD::SELECT_ICC;
789 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
791 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
792 Opc = SPISD::SELECT_FCC;
793 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
795 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
796 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
799 // vastart just stores the address of the VarArgsFrameIndex slot into the
800 // memory location argument.
801 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
802 DAG.getRegister(SP::I6, MVT::i32),
803 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
804 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
805 return DAG.getStore(Op.getOperand(0), Offset,
806 Op.getOperand(1), SV->getValue(), SV->getOffset());
809 SDNode *Node = Op.Val;
810 MVT::ValueType VT = Node->getValueType(0);
811 SDOperand InChain = Node->getOperand(0);
812 SDOperand VAListPtr = Node->getOperand(1);
813 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
814 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
815 SV->getValue(), SV->getOffset());
816 // Increment the pointer, VAList, to the next vaarg
817 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
818 DAG.getConstant(MVT::getSizeInBits(VT)/8,
820 // Store the incremented VAList to the legalized pointer
821 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
822 VAListPtr, SV->getValue(), SV->getOffset());
823 // Load the actual argument out of the pointer VAList, unless this is an
825 if (VT != MVT::f64) {
826 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
828 // Otherwise, load it as i64, then do a bitconvert.
829 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
830 std::vector<MVT::ValueType> Tys;
831 Tys.push_back(MVT::f64);
832 Tys.push_back(MVT::Other);
833 // Bit-Convert the value to f64.
834 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
836 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
839 case ISD::DYNAMIC_STACKALLOC: {
840 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
841 SDOperand Size = Op.getOperand(1); // Legalize the size.
843 unsigned SPReg = SP::O6;
844 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
845 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
846 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
848 // The resultant pointer is actually 16 words from the bottom of the stack,
849 // to provide a register spill area.
850 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
851 DAG.getConstant(96, MVT::i32));
852 std::vector<MVT::ValueType> Tys;
853 Tys.push_back(MVT::i32);
854 Tys.push_back(MVT::Other);
855 SDOperand Ops[2] = { NewVal, Chain };
856 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
861 switch(Op.getNumOperands()) {
863 assert(0 && "Do not know how to return this many arguments!");
866 return SDOperand(); // ret void is legal
869 switch(Op.getOperand(1).getValueType()) {
870 default: assert(0 && "Unknown type to return!");
871 case MVT::i32: ArgReg = SP::I0; break;
872 case MVT::f32: ArgReg = SP::F0; break;
873 case MVT::f64: ArgReg = SP::D0; break;
875 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
880 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
882 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
885 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
887 // Frame & Return address. Currently unimplemented
888 case ISD::RETURNADDR: break;
889 case ISD::FRAMEADDR: break;
895 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
896 MachineBasicBlock *BB) {
897 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
900 // Figure out the conditional branch opcode to use for this select_cc.
901 switch (MI->getOpcode()) {
902 default: assert(0 && "Unknown SELECT_CC!");
903 case SP::SELECT_CC_Int_ICC:
904 case SP::SELECT_CC_FP_ICC:
905 case SP::SELECT_CC_DFP_ICC:
906 BROpcode = SP::BCOND;
908 case SP::SELECT_CC_Int_FCC:
909 case SP::SELECT_CC_FP_FCC:
910 case SP::SELECT_CC_DFP_FCC:
911 BROpcode = SP::FBCOND;
915 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
917 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
918 // control-flow pattern. The incoming instruction knows the destination vreg
919 // to set, the condition code register to branch on, the true/false values to
920 // select between, and a branch opcode to use.
921 const BasicBlock *LLVM_BB = BB->getBasicBlock();
922 ilist<MachineBasicBlock>::iterator It = BB;
929 // fallthrough --> copy0MBB
930 MachineBasicBlock *thisMBB = BB;
931 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
932 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
933 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
934 MachineFunction *F = BB->getParent();
935 F->getBasicBlockList().insert(It, copy0MBB);
936 F->getBasicBlockList().insert(It, sinkMBB);
937 // Update machine-CFG edges by first adding all successors of the current
938 // block to the new block which will contain the Phi node for the select.
939 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
940 e = BB->succ_end(); i != e; ++i)
941 sinkMBB->addSuccessor(*i);
942 // Next, remove all successors of the current block, and add the true
943 // and fallthrough blocks as its successors.
944 while(!BB->succ_empty())
945 BB->removeSuccessor(BB->succ_begin());
946 BB->addSuccessor(copy0MBB);
947 BB->addSuccessor(sinkMBB);
951 // # fallthrough to sinkMBB
954 // Update machine-CFG edges
955 BB->addSuccessor(sinkMBB);
958 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
961 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
962 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
963 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
965 delete MI; // The pseudo instruction is gone now.
969 //===----------------------------------------------------------------------===//
970 // Instruction Selector Implementation
971 //===----------------------------------------------------------------------===//
973 //===--------------------------------------------------------------------===//
974 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
975 /// instructions for SelectionDAG operations.
978 class SparcDAGToDAGISel : public SelectionDAGISel {
979 SparcTargetLowering Lowering;
981 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
982 /// make the right decision when generating code for different targets.
983 const SparcSubtarget &Subtarget;
985 SparcDAGToDAGISel(TargetMachine &TM)
986 : SelectionDAGISel(Lowering), Lowering(TM),
987 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
990 SDNode *Select(SDOperand Op);
992 // Complex Pattern Selectors.
993 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
994 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
997 /// InstructionSelectBasicBlock - This callback is invoked by
998 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
999 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
1001 virtual const char *getPassName() const {
1002 return "SPARC DAG->DAG Pattern Instruction Selection";
1005 // Include the pieces autogenerated from the target description.
1006 #include "SparcGenDAGISel.inc"
1008 } // end anonymous namespace
1010 /// InstructionSelectBasicBlock - This callback is invoked by
1011 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1012 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1015 // Select target instructions for the DAG.
1016 DAG.setRoot(SelectRoot(DAG.getRoot()));
1017 DAG.RemoveDeadNodes();
1019 // Emit machine code to BB.
1020 ScheduleAndEmitDAG(DAG);
1023 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1024 SDOperand &Base, SDOperand &Offset) {
1025 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1026 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1027 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1030 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1031 Addr.getOpcode() == ISD::TargetGlobalAddress)
1032 return false; // direct calls.
1034 if (Addr.getOpcode() == ISD::ADD) {
1035 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1036 if (Predicate_simm13(CN)) {
1037 if (FrameIndexSDNode *FIN =
1038 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1039 // Constant offset from frame ref.
1040 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1042 Base = Addr.getOperand(0);
1044 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1048 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1049 Base = Addr.getOperand(1);
1050 Offset = Addr.getOperand(0).getOperand(0);
1053 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1054 Base = Addr.getOperand(0);
1055 Offset = Addr.getOperand(1).getOperand(0);
1060 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1064 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1065 SDOperand &R1, SDOperand &R2) {
1066 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1067 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1068 Addr.getOpcode() == ISD::TargetGlobalAddress)
1069 return false; // direct calls.
1071 if (Addr.getOpcode() == ISD::ADD) {
1072 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1073 Predicate_simm13(Addr.getOperand(1).Val))
1074 return false; // Let the reg+imm pattern catch this!
1075 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1076 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1077 return false; // Let the reg+imm pattern catch this!
1078 R1 = Addr.getOperand(0);
1079 R2 = Addr.getOperand(1);
1084 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1088 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1090 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1091 N->getOpcode() < SPISD::FIRST_NUMBER)
1092 return NULL; // Already selected.
1094 switch (N->getOpcode()) {
1098 // FIXME: should use a custom expander to expose the SRA to the dag.
1099 SDOperand DivLHS = N->getOperand(0);
1100 SDOperand DivRHS = N->getOperand(1);
1101 AddToISelQueue(DivLHS);
1102 AddToISelQueue(DivRHS);
1104 // Set the Y register to the high-part.
1106 if (N->getOpcode() == ISD::SDIV) {
1107 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1108 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1110 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1112 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1113 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1115 // FIXME: Handle div by immediate.
1116 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1117 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1122 // FIXME: Handle mul by immediate.
1123 SDOperand MulLHS = N->getOperand(0);
1124 SDOperand MulRHS = N->getOperand(1);
1125 AddToISelQueue(MulLHS);
1126 AddToISelQueue(MulRHS);
1127 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1128 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1130 // The high part is in the Y register.
1131 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1136 return SelectCode(Op);
1140 /// createSparcISelDag - This pass converts a legalized DAG into a
1141 /// SPARC-specific DAG, ready for instruction scheduling.
1143 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1144 return new SparcDAGToDAGISel(TM);