1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
29 //===----------------------------------------------------------------------===//
30 // TargetLowering Implementation
31 //===----------------------------------------------------------------------===//
35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36 CMPICC, // Compare two GPR operands, set icc.
37 CMPFCC, // Compare two FP operands, set fcc.
38 BRICC, // Branch to dest on icc condition
39 BRFCC, // Branch to dest on fcc condition
41 Hi, Lo, // Hi/Lo operations, typically on a global address.
43 FTOI, // FP to Int within a FP register.
44 ITOF, // Int to FP within a FP register.
46 SELECT_ICC, // Select between two values using the current ICC flags.
47 SELECT_FCC, // Select between two values using the current FCC flags.
52 class SparcV8TargetLowering : public TargetLowering {
54 SparcV8TargetLowering(TargetMachine &TM);
55 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
56 virtual std::vector<SDOperand>
57 LowerArguments(Function &F, SelectionDAG &DAG);
58 virtual std::pair<SDOperand, SDOperand>
59 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
61 bool isTailCall, SDOperand Callee, ArgListTy &Args,
64 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
66 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
67 Value *VAListV, SelectionDAG &DAG);
68 virtual std::pair<SDOperand,SDOperand>
69 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
70 const Type *ArgTy, SelectionDAG &DAG);
71 virtual std::pair<SDOperand, SDOperand>
72 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
74 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
75 MachineBasicBlock *MBB);
79 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
80 : TargetLowering(TM) {
82 // Set up the register classes.
83 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
84 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
85 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
87 // Custom legalize GlobalAddress nodes into LO/HI parts.
88 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
89 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
91 // Sparc doesn't have sext_inreg, replace them with shl/sra
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
96 // Sparc has no REM operation.
97 setOperationAction(ISD::UREM, MVT::i32, Expand);
98 setOperationAction(ISD::SREM, MVT::i32, Expand);
100 // Custom expand fp<->sint
101 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
102 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
106 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
108 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
110 // Sparc has no select or setcc: expand to SELECT_CC.
111 setOperationAction(ISD::SELECT, MVT::i32, Expand);
112 setOperationAction(ISD::SELECT, MVT::f32, Expand);
113 setOperationAction(ISD::SELECT, MVT::f64, Expand);
114 setOperationAction(ISD::SETCC, MVT::i32, Expand);
115 setOperationAction(ISD::SETCC, MVT::f32, Expand);
116 setOperationAction(ISD::SETCC, MVT::f64, Expand);
118 // Sparc doesn't have BRCOND either, it has BR_CC.
119 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
120 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
121 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
122 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
123 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
124 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
130 computeRegisterProperties();
133 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
134 /// either one or two GPRs, including FP values. TODO: we should pass FP values
135 /// in FP registers for fastcc functions.
136 std::vector<SDOperand>
137 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
138 MachineFunction &MF = DAG.getMachineFunction();
139 SSARegMap *RegMap = MF.getSSARegMap();
140 std::vector<SDOperand> ArgValues;
142 static const unsigned ArgRegs[] = {
143 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
146 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
147 unsigned ArgOffset = 68;
149 SDOperand Root = DAG.getRoot();
150 std::vector<SDOperand> OutChains;
152 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
153 MVT::ValueType ObjectVT = getValueType(I->getType());
156 default: assert(0 && "Unhandled argument type!");
162 if (I->use_empty()) { // Argument is dead.
163 if (CurArgReg < ArgRegEnd) ++CurArgReg;
164 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
165 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
166 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
167 MF.addLiveIn(*CurArgReg++, VReg);
168 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
169 if (ObjectVT != MVT::i32) {
170 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
172 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
173 DAG.getValueType(ObjectVT));
174 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
176 ArgValues.push_back(Arg);
178 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
179 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
181 if (ObjectVT == MVT::i32) {
182 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
185 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
187 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
188 DAG.getSrcValue(0), ObjectVT);
190 ArgValues.push_back(Load);
196 if (I->use_empty()) { // Argument is dead.
197 if (CurArgReg < ArgRegEnd) ++CurArgReg;
198 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
199 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
200 // FP value is passed in an integer register.
201 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
202 MF.addLiveIn(*CurArgReg++, VReg);
203 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
205 // We use the stack space that is already reserved for this reg.
206 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
207 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
209 SDOperand SV = DAG.getSrcValue(0);
210 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
212 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
219 if (I->use_empty()) { // Argument is dead.
220 if (CurArgReg < ArgRegEnd) ++CurArgReg;
221 if (CurArgReg < ArgRegEnd) ++CurArgReg;
222 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
223 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
224 ((CurArgReg-ArgRegs) & 1) == 0) {
225 // If this is a double argument and the whole thing lives on the stack,
226 // and the argument is aligned, load the double straight from the stack.
227 // We can't do a load in cases like void foo([6ints], int,double),
228 // because the double wouldn't be aligned!
229 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
230 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
231 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
232 DAG.getSrcValue(0)));
235 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
236 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
237 MF.addLiveIn(*CurArgReg++, VRegHi);
238 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
240 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
241 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
242 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
246 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
247 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
248 MF.addLiveIn(*CurArgReg++, VRegLo);
249 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
251 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
252 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
253 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
256 // Compose the two halves together into an i64 unit.
257 SDOperand WholeValue =
258 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
260 if (ObjectVT == MVT::i64) {
261 // If we are emitting an i64, this is what we want.
262 ArgValues.push_back(WholeValue);
264 assert(ObjectVT == MVT::f64);
265 // Otherwise, emit a store to the stack and reload into FPR.
266 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
267 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
268 SDOperand SV = DAG.getSrcValue(0);
269 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
270 WholeValue, FIPtr, SV);
271 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
279 // Store remaining ArgRegs to the stack if this is a varargs function.
280 if (F.getFunctionType()->isVarArg()) {
281 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
282 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
283 MF.addLiveIn(*CurArgReg, VReg);
284 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
286 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
287 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
289 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
290 Arg, FIPtr, DAG.getSrcValue(0)));
295 if (!OutChains.empty())
296 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
298 // Finally, inform the code generator which regs we return values in.
299 switch (getValueType(F.getReturnType())) {
300 default: assert(0 && "Unknown type!");
301 case MVT::isVoid: break;
306 MF.addLiveOut(V8::I0);
309 MF.addLiveOut(V8::I0);
310 MF.addLiveOut(V8::I1);
313 MF.addLiveOut(V8::F0);
316 MF.addLiveOut(V8::D0);
323 std::pair<SDOperand, SDOperand>
324 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
325 bool isVarArg, unsigned CC,
326 bool isTailCall, SDOperand Callee,
327 ArgListTy &Args, SelectionDAG &DAG) {
328 assert(0 && "Unimp");
332 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
334 if (Op.getValueType() == MVT::i64) {
335 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
336 DAG.getConstant(1, MVT::i32));
337 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
338 DAG.getConstant(0, MVT::i32));
339 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
341 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
345 SDOperand SparcV8TargetLowering::
346 LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
349 assert(0 && "Unimp");
353 std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
354 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
355 const Type *ArgTy, SelectionDAG &DAG) {
356 assert(0 && "Unimp");
360 std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
361 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
363 assert(0 && "Unimp");
367 SDOperand SparcV8TargetLowering::
368 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
369 switch (Op.getOpcode()) {
370 default: assert(0 && "Should not custom lower this!");
371 case ISD::GlobalAddress: {
372 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
373 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
374 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
375 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
376 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
378 case ISD::ConstantPool: {
379 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
380 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
381 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
382 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
383 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
385 case ISD::FP_TO_SINT: {
386 // Convert the fp value to integer in an FP register.
387 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(),
389 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
391 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
392 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
393 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
394 Op, FI, DAG.getSrcValue(0));
395 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
397 case ISD::SINT_TO_FP: {
398 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
400 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
401 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
402 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
403 Op.getOperand(0), FI, DAG.getSrcValue(0));
405 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0));
407 // Convert the int value to FP in an FP register.
408 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
411 SDOperand Chain = Op.getOperand(0);
412 SDOperand CC = Op.getOperand(1);
413 SDOperand LHS = Op.getOperand(2);
414 SDOperand RHS = Op.getOperand(3);
415 SDOperand Dest = Op.getOperand(4);
417 // Get the condition flag.
418 if (LHS.getValueType() == MVT::i32) {
419 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
420 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
422 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
423 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
426 case ISD::SELECT_CC: {
427 SDOperand LHS = Op.getOperand(0);
428 SDOperand RHS = Op.getOperand(1);
429 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
430 SDOperand TrueVal = Op.getOperand(2);
431 SDOperand FalseVal = Op.getOperand(3);
434 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
435 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
437 Opc = LHS.getValueType() == MVT::i32 ?
438 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
439 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
440 DAG.getConstant(CC, MVT::i32), CompareFlag);
446 SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
447 MachineBasicBlock *BB) {
449 // Figure out the conditional branch opcode to use for this select_cc.
450 switch (MI->getOpcode()) {
451 default: assert(0 && "Unknown SELECT_CC!");
452 case V8::SELECT_CC_Int_ICC:
453 case V8::SELECT_CC_FP_ICC:
454 case V8::SELECT_CC_DFP_ICC:
456 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
457 default: assert(0 && "Unknown integer condition code!");
458 case ISD::SETEQ: BROpcode = V8::BE; break;
459 case ISD::SETNE: BROpcode = V8::BNE; break;
460 case ISD::SETLT: BROpcode = V8::BL; break;
461 case ISD::SETGT: BROpcode = V8::BG; break;
462 case ISD::SETLE: BROpcode = V8::BLE; break;
463 case ISD::SETGE: BROpcode = V8::BGE; break;
464 case ISD::SETULT: BROpcode = V8::BCS; break;
465 case ISD::SETULE: BROpcode = V8::BLEU; break;
466 case ISD::SETUGT: BROpcode = V8::BGU; break;
467 case ISD::SETUGE: BROpcode = V8::BCC; break;
470 case V8::SELECT_CC_Int_FCC:
471 case V8::SELECT_CC_FP_FCC:
472 case V8::SELECT_CC_DFP_FCC:
474 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
475 default: assert(0 && "Unknown fp condition code!");
476 case ISD::SETEQ: BROpcode = V8::FBE; break;
477 case ISD::SETNE: BROpcode = V8::FBNE; break;
478 case ISD::SETLT: BROpcode = V8::FBL; break;
479 case ISD::SETGT: BROpcode = V8::FBG; break;
480 case ISD::SETLE: BROpcode = V8::FBLE; break;
481 case ISD::SETGE: BROpcode = V8::FBGE; break;
482 case ISD::SETULT: BROpcode = V8::FBUL; break;
483 case ISD::SETULE: BROpcode = V8::FBULE; break;
484 case ISD::SETUGT: BROpcode = V8::FBUG; break;
485 case ISD::SETUGE: BROpcode = V8::FBUGE; break;
486 case ISD::SETUO: BROpcode = V8::FBU; break;
487 case ISD::SETO: BROpcode = V8::FBO; break;
488 case ISD::SETONE: BROpcode = V8::FBLG; break;
489 case ISD::SETUEQ: BROpcode = V8::FBUE; break;
494 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
495 // control-flow pattern. The incoming instruction knows the destination vreg
496 // to set, the condition code register to branch on, the true/false values to
497 // select between, and a branch opcode to use.
498 const BasicBlock *LLVM_BB = BB->getBasicBlock();
499 ilist<MachineBasicBlock>::iterator It = BB;
506 // fallthrough --> copy0MBB
507 MachineBasicBlock *thisMBB = BB;
508 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
509 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
510 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
511 MachineFunction *F = BB->getParent();
512 F->getBasicBlockList().insert(It, copy0MBB);
513 F->getBasicBlockList().insert(It, sinkMBB);
514 // Update machine-CFG edges
515 BB->addSuccessor(copy0MBB);
516 BB->addSuccessor(sinkMBB);
520 // # fallthrough to sinkMBB
523 // Update machine-CFG edges
524 BB->addSuccessor(sinkMBB);
527 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
530 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
531 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
532 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
534 delete MI; // The pseudo instruction is gone now.
538 //===----------------------------------------------------------------------===//
539 // Instruction Selector Implementation
540 //===----------------------------------------------------------------------===//
542 //===--------------------------------------------------------------------===//
543 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
544 /// instructions for SelectionDAG operations.
547 class SparcV8DAGToDAGISel : public SelectionDAGISel {
548 SparcV8TargetLowering V8Lowering;
550 SparcV8DAGToDAGISel(TargetMachine &TM)
551 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
553 SDOperand Select(SDOperand Op);
555 // Complex Pattern Selectors.
556 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
557 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
559 /// InstructionSelectBasicBlock - This callback is invoked by
560 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
561 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
563 virtual const char *getPassName() const {
564 return "PowerPC DAG->DAG Pattern Instruction Selection";
567 // Include the pieces autogenerated from the target description.
568 #include "SparcV8GenDAGISel.inc"
570 } // end anonymous namespace
572 /// InstructionSelectBasicBlock - This callback is invoked by
573 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
574 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
577 // Select target instructions for the DAG.
578 DAG.setRoot(Select(DAG.getRoot()));
580 DAG.RemoveDeadNodes();
582 // Emit machine code to BB.
583 ScheduleAndEmitDAG(DAG);
586 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
588 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
589 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
590 Offset = CurDAG->getTargetConstant(0, MVT::i32);
594 if (Addr.getOpcode() == ISD::ADD) {
595 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
596 if (Predicate_simm13(CN)) {
597 if (FrameIndexSDNode *FIN =
598 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
599 // Constant offset from frame ref.
600 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
602 Base = Select(Addr.getOperand(0));
604 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
608 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
609 Base = Select(Addr.getOperand(1));
610 Offset = Addr.getOperand(0).getOperand(0);
613 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
614 Base = Select(Addr.getOperand(0));
615 Offset = Addr.getOperand(1).getOperand(0);
620 Offset = CurDAG->getTargetConstant(0, MVT::i32);
624 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
626 if (Addr.getOpcode() == ISD::FrameIndex) return false;
627 if (Addr.getOpcode() == ISD::ADD) {
628 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
629 Predicate_simm13(Addr.getOperand(1).Val))
630 return false; // Let the reg+imm pattern catch this!
631 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
632 Addr.getOperand(1).getOpcode() == V8ISD::Lo)
633 return false; // Let the reg+imm pattern catch this!
634 R1 = Select(Addr.getOperand(0));
635 R2 = Select(Addr.getOperand(1));
640 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
644 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
646 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
647 N->getOpcode() < V8ISD::FIRST_NUMBER)
648 return Op; // Already selected.
649 // If this has already been converted, use it.
650 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
651 if (CGMI != CodeGenMap.end()) return CGMI->second;
653 switch (N->getOpcode()) {
655 case ISD::BasicBlock: return CodeGenMap[Op] = Op;
656 case ISD::FrameIndex: {
657 int FI = cast<FrameIndexSDNode>(N)->getIndex();
659 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
660 CurDAG->getTargetFrameIndex(FI, MVT::i32),
661 CurDAG->getTargetConstant(0, MVT::i32));
662 return CodeGenMap[Op] =
663 CurDAG->getTargetNode(V8::ADDri, MVT::i32,
664 CurDAG->getTargetFrameIndex(FI, MVT::i32),
665 CurDAG->getTargetConstant(0, MVT::i32));
667 case V8ISD::CMPICC: {
668 // FIXME: Handle compare with immediate.
669 SDOperand LHS = Select(N->getOperand(0));
670 SDOperand RHS = Select(N->getOperand(1));
671 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
673 return CodeGenMap[Op] = Result.getValue(1);
675 case ISD::ADD_PARTS: {
676 SDOperand LHSL = Select(N->getOperand(0));
677 SDOperand LHSH = Select(N->getOperand(1));
678 SDOperand RHSL = Select(N->getOperand(2));
679 SDOperand RHSH = Select(N->getOperand(3));
680 // FIXME, handle immediate RHS.
681 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
683 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
685 CodeGenMap[SDOperand(N, 0)] = Low;
686 CodeGenMap[SDOperand(N, 1)] = Hi;
687 return Op.ResNo ? Hi : Low;
689 case ISD::SUB_PARTS: {
690 SDOperand LHSL = Select(N->getOperand(0));
691 SDOperand LHSH = Select(N->getOperand(1));
692 SDOperand RHSL = Select(N->getOperand(2));
693 SDOperand RHSH = Select(N->getOperand(3));
694 // FIXME, handle immediate RHS.
695 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
697 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
699 CodeGenMap[SDOperand(N, 0)] = Low;
700 CodeGenMap[SDOperand(N, 1)] = Hi;
701 return Op.ResNo ? Hi : Low;
705 // FIXME: should use a custom expander to expose the SRA to the dag.
706 SDOperand DivLHS = Select(N->getOperand(0));
707 SDOperand DivRHS = Select(N->getOperand(1));
709 // Set the Y register to the high-part.
711 if (N->getOpcode() == ISD::SDIV) {
712 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
713 CurDAG->getTargetConstant(31, MVT::i32));
715 TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
717 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
718 CurDAG->getRegister(V8::G0, MVT::i32));
720 // FIXME: Handle div by immediate.
721 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
722 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
726 // FIXME: Handle mul by immediate.
727 SDOperand MulLHS = Select(N->getOperand(0));
728 SDOperand MulRHS = Select(N->getOperand(1));
729 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
730 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
732 // The high part is in the Y register.
733 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
737 if (N->getNumOperands() == 2) {
738 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
739 SDOperand Val = Select(N->getOperand(1));
740 if (N->getOperand(1).getValueType() == MVT::i32) {
741 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
742 } else if (N->getOperand(1).getValueType() == MVT::f32) {
743 Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
745 assert(N->getOperand(1).getValueType() == MVT::f64);
746 Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
748 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
749 } else if (N->getNumOperands() > 1) {
750 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
751 assert(N->getOperand(1).getValueType() == MVT::i32 &&
752 N->getOperand(2).getValueType() == MVT::i32 &&
753 N->getNumOperands() == 3 && "Unknown two-register ret value!");
754 Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(1)));
755 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(2)));
756 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
758 break; // Generated code handles the void case.
762 return SelectCode(Op);
766 /// createPPCISelDag - This pass converts a legalized DAG into a
767 /// PowerPC-specific DAG, ready for instruction scheduling.
769 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
770 return new SparcV8DAGToDAGISel(TM);