1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
29 //===----------------------------------------------------------------------===//
30 // TargetLowering Implementation
31 //===----------------------------------------------------------------------===//
35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36 CMPICC, // Compare two GPR operands, set icc.
37 CMPFCC, // Compare two FP operands, set fcc.
38 BRICC, // Branch to dest on icc condition
39 BRFCC, // Branch to dest on fcc condition
41 Hi, Lo, // Hi/Lo operations, typically on a global address.
43 FTOI, // FP to Int within a FP register.
44 ITOF, // Int to FP within a FP register.
46 SELECT_ICC, // Select between two values using the current ICC flags.
47 SELECT_FCC, // Select between two values using the current FCC flags.
49 CALL, // A V8 call instruction.
50 RET_FLAG, // Return with a flag operand.
55 class SparcV8TargetLowering : public TargetLowering {
56 int VarArgsFrameOffset; // Frame offset to start of varargs area.
58 SparcV8TargetLowering(TargetMachine &TM);
59 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
61 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
62 /// be zero. Op is expected to be a target specific node. Used by DAG
64 virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
66 MVIZFnPtr MVIZ) const;
68 virtual std::vector<SDOperand>
69 LowerArguments(Function &F, SelectionDAG &DAG);
70 virtual std::pair<SDOperand, SDOperand>
71 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
73 bool isTailCall, SDOperand Callee, ArgListTy &Args,
75 virtual std::pair<SDOperand, SDOperand>
76 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
78 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
79 MachineBasicBlock *MBB);
81 virtual const char *getTargetNodeName(unsigned Opcode) const;
85 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
86 : TargetLowering(TM) {
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
90 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
91 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
93 // Custom legalize GlobalAddress nodes into LO/HI parts.
94 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
95 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
97 // Sparc doesn't have sext_inreg, replace them with shl/sra
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
102 // Sparc has no REM operation.
103 setOperationAction(ISD::UREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
106 // Custom expand fp<->sint
107 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
108 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
111 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
114 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
115 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
117 // Turn FP extload into load/fextend
118 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
120 // Sparc has no select or setcc: expand to SELECT_CC.
121 setOperationAction(ISD::SELECT, MVT::i32, Expand);
122 setOperationAction(ISD::SELECT, MVT::f32, Expand);
123 setOperationAction(ISD::SELECT, MVT::f64, Expand);
124 setOperationAction(ISD::SETCC, MVT::i32, Expand);
125 setOperationAction(ISD::SETCC, MVT::f32, Expand);
126 setOperationAction(ISD::SETCC, MVT::f64, Expand);
128 // Sparc doesn't have BRCOND either, it has BR_CC.
129 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
130 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
131 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
140 // V8 has no intrinsics for these particular operations.
141 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
142 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
143 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
145 setOperationAction(ISD::FSIN , MVT::f64, Expand);
146 setOperationAction(ISD::FCOS , MVT::f64, Expand);
147 setOperationAction(ISD::FSIN , MVT::f32, Expand);
148 setOperationAction(ISD::FCOS , MVT::f32, Expand);
149 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
150 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
151 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
152 setOperationAction(ISD::ROTL , MVT::i32, Expand);
153 setOperationAction(ISD::ROTR , MVT::i32, Expand);
154 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
156 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
157 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
158 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
160 // We don't have line number support yet.
161 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
162 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
163 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
165 // RET must be custom lowered, to meet ABI requirements
166 setOperationAction(ISD::RET , MVT::Other, Custom);
168 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
169 setOperationAction(ISD::VASTART , MVT::Other, Custom);
171 // Use the default implementation.
172 setOperationAction(ISD::VAARG , MVT::Other, Expand);
173 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
174 setOperationAction(ISD::VAEND , MVT::Other, Expand);
175 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
176 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
177 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
179 setStackPointerRegisterToSaveRestore(V8::O6);
181 computeRegisterProperties();
184 const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
187 case V8ISD::CMPICC: return "V8ISD::CMPICC";
188 case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
189 case V8ISD::BRICC: return "V8ISD::BRICC";
190 case V8ISD::BRFCC: return "V8ISD::BRFCC";
191 case V8ISD::Hi: return "V8ISD::Hi";
192 case V8ISD::Lo: return "V8ISD::Lo";
193 case V8ISD::FTOI: return "V8ISD::FTOI";
194 case V8ISD::ITOF: return "V8ISD::ITOF";
195 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
196 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
197 case V8ISD::CALL: return "V8ISD::CALL";
198 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
202 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
203 /// be zero. Op is expected to be a target specific node. Used by DAG
205 bool SparcV8TargetLowering::
206 isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
207 MVIZFnPtr MVIZ) const {
208 switch (Op.getOpcode()) {
209 default: return false;
210 case V8ISD::SELECT_ICC:
211 case V8ISD::SELECT_FCC:
212 assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
213 // These operations are masked zero if both the left and the right are zero.
214 return MVIZ(Op.getOperand(0), Mask, *this) &&
215 MVIZ(Op.getOperand(1), Mask, *this);
220 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
221 /// either one or two GPRs, including FP values. TODO: we should pass FP values
222 /// in FP registers for fastcc functions.
223 std::vector<SDOperand>
224 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
225 MachineFunction &MF = DAG.getMachineFunction();
226 SSARegMap *RegMap = MF.getSSARegMap();
227 std::vector<SDOperand> ArgValues;
229 static const unsigned ArgRegs[] = {
230 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
233 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
234 unsigned ArgOffset = 68;
236 SDOperand Root = DAG.getRoot();
237 std::vector<SDOperand> OutChains;
239 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
240 MVT::ValueType ObjectVT = getValueType(I->getType());
243 default: assert(0 && "Unhandled argument type!");
248 if (I->use_empty()) { // Argument is dead.
249 if (CurArgReg < ArgRegEnd) ++CurArgReg;
250 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
251 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
252 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
253 MF.addLiveIn(*CurArgReg++, VReg);
254 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
255 if (ObjectVT != MVT::i32) {
256 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
258 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
259 DAG.getValueType(ObjectVT));
260 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
262 ArgValues.push_back(Arg);
264 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
265 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
267 if (ObjectVT == MVT::i32) {
268 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
271 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
273 // Sparc is big endian, so add an offset based on the ObjectVT.
274 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
275 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
276 DAG.getConstant(Offset, MVT::i32));
277 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
278 DAG.getSrcValue(0), ObjectVT);
279 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
281 ArgValues.push_back(Load);
287 if (I->use_empty()) { // Argument is dead.
288 if (CurArgReg < ArgRegEnd) ++CurArgReg;
289 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
290 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
291 // FP value is passed in an integer register.
292 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
293 MF.addLiveIn(*CurArgReg++, VReg);
294 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
296 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
297 ArgValues.push_back(Arg);
299 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
300 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
301 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
302 ArgValues.push_back(Load);
309 if (I->use_empty()) { // Argument is dead.
310 if (CurArgReg < ArgRegEnd) ++CurArgReg;
311 if (CurArgReg < ArgRegEnd) ++CurArgReg;
312 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
313 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
314 ((CurArgReg-ArgRegs) & 1) == 0) {
315 // If this is a double argument and the whole thing lives on the stack,
316 // and the argument is aligned, load the double straight from the stack.
317 // We can't do a load in cases like void foo([6ints], int,double),
318 // because the double wouldn't be aligned!
319 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
320 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
321 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
322 DAG.getSrcValue(0)));
325 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
326 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
327 MF.addLiveIn(*CurArgReg++, VRegHi);
328 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
330 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
331 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
332 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
336 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
337 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
338 MF.addLiveIn(*CurArgReg++, VRegLo);
339 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
341 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
342 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
343 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
346 // Compose the two halves together into an i64 unit.
347 SDOperand WholeValue =
348 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
350 // If we want a double, do a bit convert.
351 if (ObjectVT == MVT::f64)
352 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
354 ArgValues.push_back(WholeValue);
361 // Store remaining ArgRegs to the stack if this is a varargs function.
362 if (F.getFunctionType()->isVarArg()) {
363 // Remember the vararg offset for the va_start implementation.
364 VarArgsFrameOffset = ArgOffset;
366 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
367 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
368 MF.addLiveIn(*CurArgReg, VReg);
369 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
371 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
372 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
374 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
375 Arg, FIPtr, DAG.getSrcValue(0)));
380 if (!OutChains.empty())
381 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
383 // Finally, inform the code generator which regs we return values in.
384 switch (getValueType(F.getReturnType())) {
385 default: assert(0 && "Unknown type!");
386 case MVT::isVoid: break;
391 MF.addLiveOut(V8::I0);
394 MF.addLiveOut(V8::I0);
395 MF.addLiveOut(V8::I1);
398 MF.addLiveOut(V8::F0);
401 MF.addLiveOut(V8::D0);
408 std::pair<SDOperand, SDOperand>
409 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
410 bool isVarArg, unsigned CC,
411 bool isTailCall, SDOperand Callee,
412 ArgListTy &Args, SelectionDAG &DAG) {
413 MachineFunction &MF = DAG.getMachineFunction();
414 // Count the size of the outgoing arguments.
415 unsigned ArgsSize = 0;
416 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
417 switch (getValueType(Args[i].second)) {
418 default: assert(0 && "Unknown value type!");
433 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
437 // Keep stack frames 8-byte aligned.
438 ArgsSize = (ArgsSize+7) & ~7;
440 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
441 DAG.getConstant(ArgsSize, getPointerTy()));
443 SDOperand StackPtr, NullSV;
444 std::vector<SDOperand> Stores;
445 std::vector<SDOperand> RegValuesToPass;
446 unsigned ArgOffset = 68;
447 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
448 SDOperand Val = Args[i].first;
449 MVT::ValueType ObjectVT = Val.getValueType();
450 SDOperand ValToStore(0, 0);
453 default: assert(0 && "Unhandled argument type!");
457 // Promote the integer to 32-bits. If the input type is signed, use a
458 // sign extend, otherwise use a zero extend.
459 if (Args[i].second->isSigned())
460 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
462 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
467 if (RegValuesToPass.size() >= 6) {
470 RegValuesToPass.push_back(Val);
475 if (RegValuesToPass.size() >= 6) {
478 // Convert this to a FP value in an int reg.
479 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
480 RegValuesToPass.push_back(Val);
485 // If we can store this directly into the outgoing slot, do so. We can
486 // do this when all ArgRegs are used and if the outgoing slot is aligned.
487 // FIXME: McGill/misr fails with this.
488 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
493 // Otherwise, convert this to a FP value in int regs.
494 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
498 if (RegValuesToPass.size() >= 6) {
499 ValToStore = Val; // Whole thing is passed in memory.
503 // Split the value into top and bottom part. Top part goes in a reg.
504 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
505 DAG.getConstant(1, MVT::i32));
506 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
507 DAG.getConstant(0, MVT::i32));
508 RegValuesToPass.push_back(Hi);
510 if (RegValuesToPass.size() >= 6) {
515 RegValuesToPass.push_back(Lo);
520 if (ValToStore.Val) {
522 StackPtr = DAG.getRegister(V8::O6, MVT::i32);
523 NullSV = DAG.getSrcValue(NULL);
525 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
526 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
527 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
528 ValToStore, PtrOff, NullSV));
530 ArgOffset += ObjSize;
533 // Emit all stores, make sure the occur before any copies into physregs.
535 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
537 static const unsigned ArgRegs[] = {
538 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
541 // Build a sequence of copy-to-reg nodes chained together with token chain
542 // and flag operands which copy the outgoing args into O[0-5].
544 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
545 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
546 InFlag = Chain.getValue(1);
549 // If the callee is a GlobalAddress node (quite common, every direct call is)
550 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
551 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
552 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
554 std::vector<MVT::ValueType> NodeTys;
555 NodeTys.push_back(MVT::Other); // Returns a chain
556 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
557 std::vector<SDOperand> Ops;
558 Ops.push_back(Chain);
559 Ops.push_back(Callee);
561 Ops.push_back(InFlag);
562 Chain = DAG.getNode(V8ISD::CALL, NodeTys, Ops);
563 InFlag = Chain.getValue(1);
565 MVT::ValueType RetTyVT = getValueType(RetTy);
567 if (RetTyVT != MVT::isVoid) {
569 default: assert(0 && "Unknown value type to return!");
573 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
574 Chain = RetVal.getValue(1);
576 // Add a note to keep track of whether it is sign or zero extended.
577 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
578 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
579 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
582 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
583 Chain = RetVal.getValue(1);
586 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
587 Chain = RetVal.getValue(1);
590 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
591 Chain = RetVal.getValue(1);
594 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
595 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
597 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
598 Chain = Hi.getValue(1);
603 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
604 DAG.getConstant(ArgsSize, getPointerTy()));
606 return std::make_pair(RetVal, Chain);
609 std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
610 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
612 assert(0 && "Unimp");
616 SDOperand SparcV8TargetLowering::
617 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
618 switch (Op.getOpcode()) {
619 default: assert(0 && "Should not custom lower this!");
620 case ISD::GlobalAddress: {
621 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
622 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
623 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
624 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
625 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
627 case ISD::ConstantPool: {
628 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
629 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
630 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
631 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
632 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
634 case ISD::FP_TO_SINT:
635 // Convert the fp value to integer in an FP register.
636 assert(Op.getValueType() == MVT::i32);
637 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
638 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
639 case ISD::SINT_TO_FP: {
640 assert(Op.getOperand(0).getValueType() == MVT::i32);
641 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
642 // Convert the int value to FP in an FP register.
643 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
646 SDOperand Chain = Op.getOperand(0);
647 SDOperand CC = Op.getOperand(1);
648 SDOperand LHS = Op.getOperand(2);
649 SDOperand RHS = Op.getOperand(3);
650 SDOperand Dest = Op.getOperand(4);
652 // Get the condition flag.
653 if (LHS.getValueType() == MVT::i32) {
654 std::vector<MVT::ValueType> VTs;
655 VTs.push_back(MVT::i32);
656 VTs.push_back(MVT::Flag);
657 std::vector<SDOperand> Ops;
660 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
661 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
663 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
664 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
667 case ISD::SELECT_CC: {
668 SDOperand LHS = Op.getOperand(0);
669 SDOperand RHS = Op.getOperand(1);
670 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
671 SDOperand TrueVal = Op.getOperand(2);
672 SDOperand FalseVal = Op.getOperand(3);
674 SDOperand CompareFlag;
676 if (LHS.getValueType() == MVT::i32) {
677 std::vector<MVT::ValueType> VTs;
678 VTs.push_back(LHS.getValueType()); // subcc returns a value
679 VTs.push_back(MVT::Flag);
680 std::vector<SDOperand> Ops;
683 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
684 Opc = V8ISD::SELECT_ICC;
686 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
687 Opc = V8ISD::SELECT_FCC;
689 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
690 DAG.getConstant(CC, MVT::i32), CompareFlag);
693 // vastart just stores the address of the VarArgsFrameIndex slot into the
694 // memory location argument.
695 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
696 DAG.getRegister(V8::I6, MVT::i32),
697 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
698 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
699 Op.getOperand(1), Op.getOperand(2));
704 switch(Op.getNumOperands()) {
706 assert(0 && "Do not know how to return this many arguments!");
709 return SDOperand(); // ret void is legal
712 switch(Op.getOperand(1).getValueType()) {
713 default: assert(0 && "Unknown type to return!");
714 case MVT::i32: ArgReg = V8::I0; break;
715 case MVT::f32: ArgReg = V8::F0; break;
716 case MVT::f64: ArgReg = V8::D0; break;
718 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
723 Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2),
725 Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1));
728 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
734 SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
735 MachineBasicBlock *BB) {
737 // Figure out the conditional branch opcode to use for this select_cc.
738 switch (MI->getOpcode()) {
739 default: assert(0 && "Unknown SELECT_CC!");
740 case V8::SELECT_CC_Int_ICC:
741 case V8::SELECT_CC_FP_ICC:
742 case V8::SELECT_CC_DFP_ICC:
744 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
745 default: assert(0 && "Unknown integer condition code!");
746 case ISD::SETEQ: BROpcode = V8::BE; break;
747 case ISD::SETNE: BROpcode = V8::BNE; break;
748 case ISD::SETLT: BROpcode = V8::BL; break;
749 case ISD::SETGT: BROpcode = V8::BG; break;
750 case ISD::SETLE: BROpcode = V8::BLE; break;
751 case ISD::SETGE: BROpcode = V8::BGE; break;
752 case ISD::SETULT: BROpcode = V8::BCS; break;
753 case ISD::SETULE: BROpcode = V8::BLEU; break;
754 case ISD::SETUGT: BROpcode = V8::BGU; break;
755 case ISD::SETUGE: BROpcode = V8::BCC; break;
758 case V8::SELECT_CC_Int_FCC:
759 case V8::SELECT_CC_FP_FCC:
760 case V8::SELECT_CC_DFP_FCC:
762 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
763 default: assert(0 && "Unknown fp condition code!");
764 case ISD::SETEQ: BROpcode = V8::FBE; break;
765 case ISD::SETNE: BROpcode = V8::FBNE; break;
766 case ISD::SETLT: BROpcode = V8::FBL; break;
767 case ISD::SETGT: BROpcode = V8::FBG; break;
768 case ISD::SETLE: BROpcode = V8::FBLE; break;
769 case ISD::SETGE: BROpcode = V8::FBGE; break;
770 case ISD::SETULT: BROpcode = V8::FBUL; break;
771 case ISD::SETULE: BROpcode = V8::FBULE; break;
772 case ISD::SETUGT: BROpcode = V8::FBUG; break;
773 case ISD::SETUGE: BROpcode = V8::FBUGE; break;
774 case ISD::SETUO: BROpcode = V8::FBU; break;
775 case ISD::SETO: BROpcode = V8::FBO; break;
776 case ISD::SETONE: BROpcode = V8::FBLG; break;
777 case ISD::SETUEQ: BROpcode = V8::FBUE; break;
782 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
783 // control-flow pattern. The incoming instruction knows the destination vreg
784 // to set, the condition code register to branch on, the true/false values to
785 // select between, and a branch opcode to use.
786 const BasicBlock *LLVM_BB = BB->getBasicBlock();
787 ilist<MachineBasicBlock>::iterator It = BB;
794 // fallthrough --> copy0MBB
795 MachineBasicBlock *thisMBB = BB;
796 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
797 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
798 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
799 MachineFunction *F = BB->getParent();
800 F->getBasicBlockList().insert(It, copy0MBB);
801 F->getBasicBlockList().insert(It, sinkMBB);
802 // Update machine-CFG edges
803 BB->addSuccessor(copy0MBB);
804 BB->addSuccessor(sinkMBB);
808 // # fallthrough to sinkMBB
811 // Update machine-CFG edges
812 BB->addSuccessor(sinkMBB);
815 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
818 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
819 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
820 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
822 delete MI; // The pseudo instruction is gone now.
826 //===----------------------------------------------------------------------===//
827 // Instruction Selector Implementation
828 //===----------------------------------------------------------------------===//
830 //===--------------------------------------------------------------------===//
831 /// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
832 /// instructions for SelectionDAG operations.
835 class SparcV8DAGToDAGISel : public SelectionDAGISel {
836 SparcV8TargetLowering V8Lowering;
838 SparcV8DAGToDAGISel(TargetMachine &TM)
839 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
841 SDOperand Select(SDOperand Op);
843 // Complex Pattern Selectors.
844 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
845 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
847 /// InstructionSelectBasicBlock - This callback is invoked by
848 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
849 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
851 virtual const char *getPassName() const {
852 return "SparcV8 DAG->DAG Pattern Instruction Selection";
855 // Include the pieces autogenerated from the target description.
856 #include "SparcV8GenDAGISel.inc"
858 } // end anonymous namespace
860 /// InstructionSelectBasicBlock - This callback is invoked by
861 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
862 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
865 // Select target instructions for the DAG.
866 DAG.setRoot(Select(DAG.getRoot()));
868 DAG.RemoveDeadNodes();
870 // Emit machine code to BB.
871 ScheduleAndEmitDAG(DAG);
874 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
876 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
877 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
878 Offset = CurDAG->getTargetConstant(0, MVT::i32);
882 if (Addr.getOpcode() == ISD::ADD) {
883 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
884 if (Predicate_simm13(CN)) {
885 if (FrameIndexSDNode *FIN =
886 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
887 // Constant offset from frame ref.
888 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
890 Base = Select(Addr.getOperand(0));
892 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
896 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
897 Base = Select(Addr.getOperand(1));
898 Offset = Addr.getOperand(0).getOperand(0);
901 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
902 Base = Select(Addr.getOperand(0));
903 Offset = Addr.getOperand(1).getOperand(0);
908 Offset = CurDAG->getTargetConstant(0, MVT::i32);
912 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
914 if (Addr.getOpcode() == ISD::FrameIndex) return false;
915 if (Addr.getOpcode() == ISD::ADD) {
916 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
917 Predicate_simm13(Addr.getOperand(1).Val))
918 return false; // Let the reg+imm pattern catch this!
919 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
920 Addr.getOperand(1).getOpcode() == V8ISD::Lo)
921 return false; // Let the reg+imm pattern catch this!
922 R1 = Select(Addr.getOperand(0));
923 R2 = Select(Addr.getOperand(1));
928 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
932 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
934 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
935 N->getOpcode() < V8ISD::FIRST_NUMBER)
936 return Op; // Already selected.
937 // If this has already been converted, use it.
938 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
939 if (CGMI != CodeGenMap.end()) return CGMI->second;
941 switch (N->getOpcode()) {
943 case ISD::FrameIndex: {
944 int FI = cast<FrameIndexSDNode>(N)->getIndex();
946 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
947 CurDAG->getTargetFrameIndex(FI, MVT::i32),
948 CurDAG->getTargetConstant(0, MVT::i32));
949 return CodeGenMap[Op] =
950 CurDAG->getTargetNode(V8::ADDri, MVT::i32,
951 CurDAG->getTargetFrameIndex(FI, MVT::i32),
952 CurDAG->getTargetConstant(0, MVT::i32));
954 case ISD::ADD_PARTS: {
955 SDOperand LHSL = Select(N->getOperand(0));
956 SDOperand LHSH = Select(N->getOperand(1));
957 SDOperand RHSL = Select(N->getOperand(2));
958 SDOperand RHSH = Select(N->getOperand(3));
959 // FIXME, handle immediate RHS.
960 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
962 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
964 CodeGenMap[SDOperand(N, 0)] = Low;
965 CodeGenMap[SDOperand(N, 1)] = Hi;
966 return Op.ResNo ? Hi : Low;
968 case ISD::SUB_PARTS: {
969 SDOperand LHSL = Select(N->getOperand(0));
970 SDOperand LHSH = Select(N->getOperand(1));
971 SDOperand RHSL = Select(N->getOperand(2));
972 SDOperand RHSH = Select(N->getOperand(3));
973 // FIXME, handle immediate RHS.
974 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
976 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
978 CodeGenMap[SDOperand(N, 0)] = Low;
979 CodeGenMap[SDOperand(N, 1)] = Hi;
980 return Op.ResNo ? Hi : Low;
984 // FIXME: should use a custom expander to expose the SRA to the dag.
985 SDOperand DivLHS = Select(N->getOperand(0));
986 SDOperand DivRHS = Select(N->getOperand(1));
988 // Set the Y register to the high-part.
990 if (N->getOpcode() == ISD::SDIV) {
991 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
992 CurDAG->getTargetConstant(31, MVT::i32));
994 TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
996 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
997 CurDAG->getRegister(V8::G0, MVT::i32));
999 // FIXME: Handle div by immediate.
1000 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
1001 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
1005 // FIXME: Handle mul by immediate.
1006 SDOperand MulLHS = Select(N->getOperand(0));
1007 SDOperand MulRHS = Select(N->getOperand(1));
1008 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
1009 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1011 // The high part is in the Y register.
1012 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
1015 // FIXME: This is a workaround for a bug in tblgen.
1016 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
1017 // Emits: (CALL:void (tglobaladdr:i32):$dst)
1018 // Pattern complexity = 2 cost = 1
1019 SDOperand N1 = N->getOperand(1);
1020 if (N1.getOpcode() != ISD::TargetGlobalAddress &&
1021 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
1022 SDOperand InFlag = SDOperand(0, 0);
1023 SDOperand Chain = N->getOperand(0);
1024 SDOperand Tmp0 = N1;
1025 Chain = Select(Chain);
1027 if (N->getNumOperands() == 3) {
1028 InFlag = Select(N->getOperand(2));
1029 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1032 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1035 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1036 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1037 return Result.getValue(Op.ResNo);
1043 return SelectCode(Op);
1047 /// createSparcV8ISelDag - This pass converts a legalized DAG into a
1048 /// SPARC-specific DAG, ready for instruction scheduling.
1050 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1051 return new SparcV8DAGToDAGISel(TM);