1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
32 //===----------------------------------------------------------------------===//
33 // TargetLowering Implementation
34 //===----------------------------------------------------------------------===//
38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
39 CMPICC, // Compare two GPR operands, set icc.
40 CMPFCC, // Compare two FP operands, set fcc.
41 BRICC, // Branch to dest on icc condition
42 BRFCC, // Branch to dest on fcc condition
43 SELECT_ICC, // Select between two values using the current ICC flags.
44 SELECT_FCC, // Select between two values using the current FCC flags.
46 Hi, Lo, // Hi/Lo operations, typically on a global address.
48 FTOI, // FP to Int within a FP register.
49 ITOF, // Int to FP within a FP register.
51 CALL, // A call instruction.
52 RET_FLAG // Return with a flag operand.
56 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
58 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
60 default: assert(0 && "Unknown integer condition code!");
61 case ISD::SETEQ: return SPCC::ICC_E;
62 case ISD::SETNE: return SPCC::ICC_NE;
63 case ISD::SETLT: return SPCC::ICC_L;
64 case ISD::SETGT: return SPCC::ICC_G;
65 case ISD::SETLE: return SPCC::ICC_LE;
66 case ISD::SETGE: return SPCC::ICC_GE;
67 case ISD::SETULT: return SPCC::ICC_CS;
68 case ISD::SETULE: return SPCC::ICC_LEU;
69 case ISD::SETUGT: return SPCC::ICC_GU;
70 case ISD::SETUGE: return SPCC::ICC_CC;
74 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
76 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
78 default: assert(0 && "Unknown fp condition code!");
80 case ISD::SETOEQ: return SPCC::FCC_E;
82 case ISD::SETUNE: return SPCC::FCC_NE;
84 case ISD::SETOLT: return SPCC::FCC_L;
86 case ISD::SETOGT: return SPCC::FCC_G;
88 case ISD::SETOLE: return SPCC::FCC_LE;
90 case ISD::SETOGE: return SPCC::FCC_GE;
91 case ISD::SETULT: return SPCC::FCC_UL;
92 case ISD::SETULE: return SPCC::FCC_ULE;
93 case ISD::SETUGT: return SPCC::FCC_UG;
94 case ISD::SETUGE: return SPCC::FCC_UGE;
95 case ISD::SETUO: return SPCC::FCC_U;
96 case ISD::SETO: return SPCC::FCC_O;
97 case ISD::SETONE: return SPCC::FCC_LG;
98 case ISD::SETUEQ: return SPCC::FCC_UE;
103 class SparcTargetLowering : public TargetLowering {
104 int VarArgsFrameOffset; // Frame offset to start of varargs area.
106 SparcTargetLowering(TargetMachine &TM);
107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
109 int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
111 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
112 /// in Mask are known to be either zero or one and return them in the
113 /// KnownZero/KnownOne bitsets.
114 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
118 const SelectionDAG &DAG,
119 unsigned Depth = 0) const;
121 virtual std::vector<SDOperand>
122 LowerArguments(Function &F, SelectionDAG &DAG);
123 virtual std::pair<SDOperand, SDOperand>
124 LowerCallTo(SDOperand Chain, const Type *RetTy,
125 bool RetSExt, bool RetZExt, bool isVarArg,
126 unsigned CC, bool isTailCall, SDOperand Callee,
127 ArgListTy &Args, SelectionDAG &DAG);
128 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
129 MachineBasicBlock *MBB);
131 virtual const char *getTargetNodeName(unsigned Opcode) const;
135 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
136 : TargetLowering(TM) {
138 // Set up the register classes.
139 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
140 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
141 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
143 // Turn FP extload into load/fextend
144 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
145 // Sparc doesn't have i1 sign extending load
146 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
147 // Turn FP truncstore into trunc + store.
148 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
150 // Custom legalize GlobalAddress nodes into LO/HI parts.
151 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
152 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
153 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
155 // Sparc doesn't have sext_inreg, replace them with shl/sra
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
160 // Sparc has no REM or DIVREM operations.
161 setOperationAction(ISD::UREM, MVT::i32, Expand);
162 setOperationAction(ISD::SREM, MVT::i32, Expand);
163 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
164 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
166 // Custom expand fp<->sint
167 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
168 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
171 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
172 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
174 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
175 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
177 // Sparc has no select or setcc: expand to SELECT_CC.
178 setOperationAction(ISD::SELECT, MVT::i32, Expand);
179 setOperationAction(ISD::SELECT, MVT::f32, Expand);
180 setOperationAction(ISD::SELECT, MVT::f64, Expand);
181 setOperationAction(ISD::SETCC, MVT::i32, Expand);
182 setOperationAction(ISD::SETCC, MVT::f32, Expand);
183 setOperationAction(ISD::SETCC, MVT::f64, Expand);
185 // Sparc doesn't have BRCOND either, it has BR_CC.
186 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
187 setOperationAction(ISD::BRIND, MVT::Other, Expand);
188 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
189 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
190 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
191 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
193 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
194 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
195 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
197 // SPARC has no intrinsics for these particular operations.
198 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
199 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
200 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
201 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
203 setOperationAction(ISD::FSIN , MVT::f64, Expand);
204 setOperationAction(ISD::FCOS , MVT::f64, Expand);
205 setOperationAction(ISD::FREM , MVT::f64, Expand);
206 setOperationAction(ISD::FSIN , MVT::f32, Expand);
207 setOperationAction(ISD::FCOS , MVT::f32, Expand);
208 setOperationAction(ISD::FREM , MVT::f32, Expand);
209 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
211 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
212 setOperationAction(ISD::ROTL , MVT::i32, Expand);
213 setOperationAction(ISD::ROTR , MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
215 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
216 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
217 setOperationAction(ISD::FPOW , MVT::f64, Expand);
218 setOperationAction(ISD::FPOW , MVT::f32, Expand);
220 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
221 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
222 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
224 // FIXME: Sparc provides these multiplies, but we don't have them yet.
225 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
227 // We don't have line number support yet.
228 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
229 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
230 setOperationAction(ISD::LABEL, MVT::Other, Expand);
232 // RET must be custom lowered, to meet ABI requirements
233 setOperationAction(ISD::RET , MVT::Other, Custom);
235 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
236 setOperationAction(ISD::VASTART , MVT::Other, Custom);
237 // VAARG needs to be lowered to not do unaligned accesses for doubles.
238 setOperationAction(ISD::VAARG , MVT::Other, Custom);
240 // Use the default implementation.
241 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
242 setOperationAction(ISD::VAEND , MVT::Other, Expand);
243 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
244 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
245 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
247 // No debug info support yet.
248 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
249 setOperationAction(ISD::LABEL, MVT::Other, Expand);
250 setOperationAction(ISD::DECLARE, MVT::Other, Expand);
252 setStackPointerRegisterToSaveRestore(SP::O6);
254 if (TM.getSubtarget<SparcSubtarget>().isV9())
255 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
257 computeRegisterProperties();
260 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
263 case SPISD::CMPICC: return "SPISD::CMPICC";
264 case SPISD::CMPFCC: return "SPISD::CMPFCC";
265 case SPISD::BRICC: return "SPISD::BRICC";
266 case SPISD::BRFCC: return "SPISD::BRFCC";
267 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
268 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
269 case SPISD::Hi: return "SPISD::Hi";
270 case SPISD::Lo: return "SPISD::Lo";
271 case SPISD::FTOI: return "SPISD::FTOI";
272 case SPISD::ITOF: return "SPISD::ITOF";
273 case SPISD::CALL: return "SPISD::CALL";
274 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
278 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
279 /// be zero. Op is expected to be a target specific node. Used by DAG
281 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
285 const SelectionDAG &DAG,
286 unsigned Depth) const {
287 APInt KnownZero2, KnownOne2;
288 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
290 switch (Op.getOpcode()) {
292 case SPISD::SELECT_ICC:
293 case SPISD::SELECT_FCC:
294 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
296 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
298 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
299 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
301 // Only known if known in both the LHS and RHS.
302 KnownOne &= KnownOne2;
303 KnownZero &= KnownZero2;
308 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
309 /// either one or two GPRs, including FP values. TODO: we should pass FP values
310 /// in FP registers for fastcc functions.
311 std::vector<SDOperand>
312 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
313 MachineFunction &MF = DAG.getMachineFunction();
314 MachineRegisterInfo &RegInfo = MF.getRegInfo();
315 std::vector<SDOperand> ArgValues;
317 static const unsigned ArgRegs[] = {
318 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
321 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
322 unsigned ArgOffset = 68;
324 SDOperand Root = DAG.getRoot();
325 std::vector<SDOperand> OutChains;
327 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
328 MVT::ValueType ObjectVT = getValueType(I->getType());
331 default: assert(0 && "Unhandled argument type!");
336 if (I->use_empty()) { // Argument is dead.
337 if (CurArgReg < ArgRegEnd) ++CurArgReg;
338 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
339 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
340 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
341 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
342 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
343 if (ObjectVT != MVT::i32) {
344 unsigned AssertOp = ISD::AssertSext;
345 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
346 DAG.getValueType(ObjectVT));
347 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
349 ArgValues.push_back(Arg);
351 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
352 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
354 if (ObjectVT == MVT::i32) {
355 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
357 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
359 // Sparc is big endian, so add an offset based on the ObjectVT.
360 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
361 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
362 DAG.getConstant(Offset, MVT::i32));
363 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
365 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
367 ArgValues.push_back(Load);
373 if (I->use_empty()) { // Argument is dead.
374 if (CurArgReg < ArgRegEnd) ++CurArgReg;
375 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
376 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
377 // FP value is passed in an integer register.
378 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
379 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
380 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
382 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
383 ArgValues.push_back(Arg);
385 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
386 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
387 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
388 ArgValues.push_back(Load);
395 if (I->use_empty()) { // Argument is dead.
396 if (CurArgReg < ArgRegEnd) ++CurArgReg;
397 if (CurArgReg < ArgRegEnd) ++CurArgReg;
398 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
399 } else if (/* FIXME: Apparently this isn't safe?? */
400 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
401 ((CurArgReg-ArgRegs) & 1) == 0) {
402 // If this is a double argument and the whole thing lives on the stack,
403 // and the argument is aligned, load the double straight from the stack.
404 // We can't do a load in cases like void foo([6ints], int,double),
405 // because the double wouldn't be aligned!
406 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
407 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
408 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
411 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
412 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
413 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
414 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
416 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
417 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
418 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
422 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
423 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
424 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
425 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
427 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
428 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
429 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
432 // Compose the two halves together into an i64 unit.
433 SDOperand WholeValue =
434 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
436 // If we want a double, do a bit convert.
437 if (ObjectVT == MVT::f64)
438 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
440 ArgValues.push_back(WholeValue);
447 // Store remaining ArgRegs to the stack if this is a varargs function.
448 if (F.getFunctionType()->isVarArg()) {
449 // Remember the vararg offset for the va_start implementation.
450 VarArgsFrameOffset = ArgOffset;
452 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
453 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
454 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
455 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
457 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
458 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
460 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
465 if (!OutChains.empty())
466 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
467 &OutChains[0], OutChains.size()));
469 // Finally, inform the code generator which regs we return values in.
470 switch (getValueType(F.getReturnType())) {
471 default: assert(0 && "Unknown type!");
472 case MVT::isVoid: break;
477 MF.getRegInfo().addLiveOut(SP::I0);
480 MF.getRegInfo().addLiveOut(SP::I0);
481 MF.getRegInfo().addLiveOut(SP::I1);
484 MF.getRegInfo().addLiveOut(SP::F0);
487 MF.getRegInfo().addLiveOut(SP::D0);
494 std::pair<SDOperand, SDOperand>
495 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
496 bool RetSExt, bool RetZExt, bool isVarArg,
497 unsigned CC, bool isTailCall, SDOperand Callee,
498 ArgListTy &Args, SelectionDAG &DAG) {
499 // Count the size of the outgoing arguments.
500 unsigned ArgsSize = 0;
501 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
502 switch (getValueType(Args[i].Ty)) {
503 default: assert(0 && "Unknown value type!");
518 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
522 // Keep stack frames 8-byte aligned.
523 ArgsSize = (ArgsSize+7) & ~7;
525 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
528 std::vector<SDOperand> Stores;
529 std::vector<SDOperand> RegValuesToPass;
530 unsigned ArgOffset = 68;
531 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
532 SDOperand Val = Args[i].Node;
533 MVT::ValueType ObjectVT = Val.getValueType();
534 SDOperand ValToStore(0, 0);
537 default: assert(0 && "Unhandled argument type!");
541 // Promote the integer to 32-bits. If the input type is signed, use a
542 // sign extend, otherwise use a zero extend.
543 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
545 ExtendKind = ISD::SIGN_EXTEND;
546 else if (Args[i].isZExt)
547 ExtendKind = ISD::ZERO_EXTEND;
548 Val = DAG.getNode(ExtendKind, MVT::i32, Val);
554 if (RegValuesToPass.size() >= 6) {
557 RegValuesToPass.push_back(Val);
562 if (RegValuesToPass.size() >= 6) {
565 // Convert this to a FP value in an int reg.
566 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
567 RegValuesToPass.push_back(Val);
572 // If we can store this directly into the outgoing slot, do so. We can
573 // do this when all ArgRegs are used and if the outgoing slot is aligned.
574 // FIXME: McGill/misr fails with this.
575 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
580 // Otherwise, convert this to a FP value in int regs.
581 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
585 if (RegValuesToPass.size() >= 6) {
586 ValToStore = Val; // Whole thing is passed in memory.
590 // Split the value into top and bottom part. Top part goes in a reg.
591 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
592 DAG.getConstant(1, MVT::i32));
593 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
594 DAG.getConstant(0, MVT::i32));
595 RegValuesToPass.push_back(Hi);
597 if (RegValuesToPass.size() >= 6) {
602 RegValuesToPass.push_back(Lo);
607 if (ValToStore.Val) {
609 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
611 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
612 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
613 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
615 ArgOffset += ObjSize;
618 // Emit all stores, make sure the occur before any copies into physregs.
620 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
622 static const unsigned ArgRegs[] = {
623 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
626 // Build a sequence of copy-to-reg nodes chained together with token chain
627 // and flag operands which copy the outgoing args into O[0-5].
629 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
630 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
631 InFlag = Chain.getValue(1);
634 // If the callee is a GlobalAddress node (quite common, every direct call is)
635 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
636 // Likewise ExternalSymbol -> TargetExternalSymbol.
637 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
638 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
639 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
640 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
642 std::vector<MVT::ValueType> NodeTys;
643 NodeTys.push_back(MVT::Other); // Returns a chain
644 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
645 SDOperand Ops[] = { Chain, Callee, InFlag };
646 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
647 InFlag = Chain.getValue(1);
649 MVT::ValueType RetTyVT = getValueType(RetTy);
651 if (RetTyVT != MVT::isVoid) {
653 default: assert(0 && "Unknown value type to return!");
657 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
658 Chain = RetVal.getValue(1);
660 // Add a note to keep track of whether it is sign or zero extended.
661 ISD::NodeType AssertKind = ISD::DELETED_NODE;
663 AssertKind = ISD::AssertSext;
665 AssertKind = ISD::AssertZext;
667 if (AssertKind != ISD::DELETED_NODE)
668 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
669 DAG.getValueType(RetTyVT));
671 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
675 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
676 Chain = RetVal.getValue(1);
679 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
680 Chain = RetVal.getValue(1);
683 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
684 Chain = RetVal.getValue(1);
687 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
688 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
690 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
691 Chain = Hi.getValue(1);
696 Chain = DAG.getCALLSEQ_END(Chain,
697 DAG.getConstant(ArgsSize, getPointerTy()),
698 DAG.getConstant(0, getPointerTy()),
700 return std::make_pair(RetVal, Chain);
703 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
704 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
705 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
706 ISD::CondCode CC, unsigned &SPCC) {
707 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
709 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
710 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
711 (LHS.getOpcode() == SPISD::SELECT_FCC &&
712 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
713 isa<ConstantSDNode>(LHS.getOperand(0)) &&
714 isa<ConstantSDNode>(LHS.getOperand(1)) &&
715 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
716 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
717 SDOperand CMPCC = LHS.getOperand(3);
718 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
719 LHS = CMPCC.getOperand(0);
720 RHS = CMPCC.getOperand(1);
724 static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) {
725 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
726 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
727 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
728 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
729 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
732 static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) {
733 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
734 Constant *C = N->getConstVal();
735 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
736 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
737 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
738 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
741 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
742 // Convert the fp value to integer in an FP register.
743 assert(Op.getValueType() == MVT::i32);
744 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
745 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
748 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
749 assert(Op.getOperand(0).getValueType() == MVT::i32);
750 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
751 // Convert the int value to FP in an FP register.
752 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
755 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
756 SDOperand Chain = Op.getOperand(0);
757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
758 SDOperand LHS = Op.getOperand(2);
759 SDOperand RHS = Op.getOperand(3);
760 SDOperand Dest = Op.getOperand(4);
761 unsigned Opc, SPCC = ~0U;
763 // If this is a br_cc of a "setcc", and if the setcc got lowered into
764 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
765 LookThroughSetCC(LHS, RHS, CC, SPCC);
767 // Get the condition flag.
768 SDOperand CompareFlag;
769 if (LHS.getValueType() == MVT::i32) {
770 std::vector<MVT::ValueType> VTs;
771 VTs.push_back(MVT::i32);
772 VTs.push_back(MVT::Flag);
773 SDOperand Ops[2] = { LHS, RHS };
774 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
775 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
778 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
779 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
782 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
783 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
786 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
787 SDOperand LHS = Op.getOperand(0);
788 SDOperand RHS = Op.getOperand(1);
789 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
790 SDOperand TrueVal = Op.getOperand(2);
791 SDOperand FalseVal = Op.getOperand(3);
792 unsigned Opc, SPCC = ~0U;
794 // If this is a select_cc of a "setcc", and if the setcc got lowered into
795 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
796 LookThroughSetCC(LHS, RHS, CC, SPCC);
798 SDOperand CompareFlag;
799 if (LHS.getValueType() == MVT::i32) {
800 std::vector<MVT::ValueType> VTs;
801 VTs.push_back(LHS.getValueType()); // subcc returns a value
802 VTs.push_back(MVT::Flag);
803 SDOperand Ops[2] = { LHS, RHS };
804 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
805 Opc = SPISD::SELECT_ICC;
806 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
808 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
809 Opc = SPISD::SELECT_FCC;
810 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
812 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
813 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
816 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
817 SparcTargetLowering &TLI) {
818 // vastart just stores the address of the VarArgsFrameIndex slot into the
819 // memory location argument.
820 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
821 DAG.getRegister(SP::I6, MVT::i32),
822 DAG.getConstant(TLI.getVarArgsFrameOffset(),
824 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
825 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
828 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
829 SDNode *Node = Op.Val;
830 MVT::ValueType VT = Node->getValueType(0);
831 SDOperand InChain = Node->getOperand(0);
832 SDOperand VAListPtr = Node->getOperand(1);
833 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
834 SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
835 // Increment the pointer, VAList, to the next vaarg
836 SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
837 DAG.getConstant(MVT::getSizeInBits(VT)/8,
839 // Store the incremented VAList to the legalized pointer
840 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
842 // Load the actual argument out of the pointer VAList, unless this is an
845 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
847 // Otherwise, load it as i64, then do a bitconvert.
848 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
850 // Bit-Convert the value to f64.
852 DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
855 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other),
859 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
860 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
861 SDOperand Size = Op.getOperand(1); // Legalize the size.
863 unsigned SPReg = SP::O6;
864 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
865 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
866 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
868 // The resultant pointer is actually 16 words from the bottom of the stack,
869 // to provide a register spill area.
870 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
871 DAG.getConstant(96, MVT::i32));
872 std::vector<MVT::ValueType> Tys;
873 Tys.push_back(MVT::i32);
874 Tys.push_back(MVT::Other);
875 SDOperand Ops[2] = { NewVal, Chain };
876 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
879 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
882 switch(Op.getNumOperands()) {
884 assert(0 && "Do not know how to return this many arguments!");
887 return SDOperand(); // ret void is legal
890 switch(Op.getOperand(1).getValueType()) {
891 default: assert(0 && "Unknown type to return!");
892 case MVT::i32: ArgReg = SP::I0; break;
893 case MVT::f32: ArgReg = SP::F0; break;
894 case MVT::f64: ArgReg = SP::D0; break;
896 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
901 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
903 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
906 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
910 SDOperand SparcTargetLowering::
911 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
912 switch (Op.getOpcode()) {
913 default: assert(0 && "Should not custom lower this!");
914 // Frame & Return address. Currently unimplemented
915 case ISD::RETURNADDR: return SDOperand();
916 case ISD::FRAMEADDR: return SDOperand();
917 case ISD::GlobalTLSAddress:
918 assert(0 && "TLS not implemented for Sparc.");
919 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
920 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG);
921 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
922 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
923 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
924 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
925 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
926 case ISD::VAARG: return LowerVAARG(Op, DAG);
927 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
928 case ISD::RET: return LowerRET(Op, DAG);
933 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
934 MachineBasicBlock *BB) {
935 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
938 // Figure out the conditional branch opcode to use for this select_cc.
939 switch (MI->getOpcode()) {
940 default: assert(0 && "Unknown SELECT_CC!");
941 case SP::SELECT_CC_Int_ICC:
942 case SP::SELECT_CC_FP_ICC:
943 case SP::SELECT_CC_DFP_ICC:
944 BROpcode = SP::BCOND;
946 case SP::SELECT_CC_Int_FCC:
947 case SP::SELECT_CC_FP_FCC:
948 case SP::SELECT_CC_DFP_FCC:
949 BROpcode = SP::FBCOND;
953 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
955 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
956 // control-flow pattern. The incoming instruction knows the destination vreg
957 // to set, the condition code register to branch on, the true/false values to
958 // select between, and a branch opcode to use.
959 const BasicBlock *LLVM_BB = BB->getBasicBlock();
960 ilist<MachineBasicBlock>::iterator It = BB;
967 // fallthrough --> copy0MBB
968 MachineBasicBlock *thisMBB = BB;
969 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
970 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
971 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
972 MachineFunction *F = BB->getParent();
973 F->getBasicBlockList().insert(It, copy0MBB);
974 F->getBasicBlockList().insert(It, sinkMBB);
975 // Update machine-CFG edges by first adding all successors of the current
976 // block to the new block which will contain the Phi node for the select.
977 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
978 e = BB->succ_end(); i != e; ++i)
979 sinkMBB->addSuccessor(*i);
980 // Next, remove all successors of the current block, and add the true
981 // and fallthrough blocks as its successors.
982 while(!BB->succ_empty())
983 BB->removeSuccessor(BB->succ_begin());
984 BB->addSuccessor(copy0MBB);
985 BB->addSuccessor(sinkMBB);
989 // # fallthrough to sinkMBB
992 // Update machine-CFG edges
993 BB->addSuccessor(sinkMBB);
996 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
999 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
1000 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1001 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1003 delete MI; // The pseudo instruction is gone now.
1007 //===----------------------------------------------------------------------===//
1008 // Instruction Selector Implementation
1009 //===----------------------------------------------------------------------===//
1011 //===--------------------------------------------------------------------===//
1012 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
1013 /// instructions for SelectionDAG operations.
1016 class SparcDAGToDAGISel : public SelectionDAGISel {
1017 SparcTargetLowering Lowering;
1019 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
1020 /// make the right decision when generating code for different targets.
1021 const SparcSubtarget &Subtarget;
1023 SparcDAGToDAGISel(TargetMachine &TM)
1024 : SelectionDAGISel(Lowering), Lowering(TM),
1025 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
1028 SDNode *Select(SDOperand Op);
1030 // Complex Pattern Selectors.
1031 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
1032 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
1035 /// InstructionSelectBasicBlock - This callback is invoked by
1036 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1037 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
1039 virtual const char *getPassName() const {
1040 return "SPARC DAG->DAG Pattern Instruction Selection";
1043 // Include the pieces autogenerated from the target description.
1044 #include "SparcGenDAGISel.inc"
1046 } // end anonymous namespace
1048 /// InstructionSelectBasicBlock - This callback is invoked by
1049 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1050 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1053 // Select target instructions for the DAG.
1054 DAG.setRoot(SelectRoot(DAG.getRoot()));
1055 DAG.RemoveDeadNodes();
1057 // Emit machine code to BB.
1058 ScheduleAndEmitDAG(DAG);
1061 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1062 SDOperand &Base, SDOperand &Offset) {
1063 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1064 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1065 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1068 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1069 Addr.getOpcode() == ISD::TargetGlobalAddress)
1070 return false; // direct calls.
1072 if (Addr.getOpcode() == ISD::ADD) {
1073 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1074 if (Predicate_simm13(CN)) {
1075 if (FrameIndexSDNode *FIN =
1076 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1077 // Constant offset from frame ref.
1078 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1080 Base = Addr.getOperand(0);
1082 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1086 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1087 Base = Addr.getOperand(1);
1088 Offset = Addr.getOperand(0).getOperand(0);
1091 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1092 Base = Addr.getOperand(0);
1093 Offset = Addr.getOperand(1).getOperand(0);
1098 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1102 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1103 SDOperand &R1, SDOperand &R2) {
1104 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1105 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1106 Addr.getOpcode() == ISD::TargetGlobalAddress)
1107 return false; // direct calls.
1109 if (Addr.getOpcode() == ISD::ADD) {
1110 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1111 Predicate_simm13(Addr.getOperand(1).Val))
1112 return false; // Let the reg+imm pattern catch this!
1113 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1114 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1115 return false; // Let the reg+imm pattern catch this!
1116 R1 = Addr.getOperand(0);
1117 R2 = Addr.getOperand(1);
1122 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1126 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1128 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1129 N->getOpcode() < SPISD::FIRST_NUMBER)
1130 return NULL; // Already selected.
1132 switch (N->getOpcode()) {
1136 // FIXME: should use a custom expander to expose the SRA to the dag.
1137 SDOperand DivLHS = N->getOperand(0);
1138 SDOperand DivRHS = N->getOperand(1);
1139 AddToISelQueue(DivLHS);
1140 AddToISelQueue(DivRHS);
1142 // Set the Y register to the high-part.
1144 if (N->getOpcode() == ISD::SDIV) {
1145 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1146 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1148 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1150 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1151 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1153 // FIXME: Handle div by immediate.
1154 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1155 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1160 // FIXME: Handle mul by immediate.
1161 SDOperand MulLHS = N->getOperand(0);
1162 SDOperand MulRHS = N->getOperand(1);
1163 AddToISelQueue(MulLHS);
1164 AddToISelQueue(MulRHS);
1165 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1166 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1168 // The high part is in the Y register.
1169 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1174 return SelectCode(Op);
1178 /// createSparcISelDag - This pass converts a legalized DAG into a
1179 /// SPARC-specific DAG, ready for instruction scheduling.
1181 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1182 return new SparcDAGToDAGISel(TM);