1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Support/Debug.h"
23 //===----------------------------------------------------------------------===//
24 // TargetLowering Implementation
25 //===----------------------------------------------------------------------===//
28 class SparcV8TargetLowering : public TargetLowering {
30 SparcV8TargetLowering(TargetMachine &TM);
32 virtual std::vector<SDOperand>
33 LowerArguments(Function &F, SelectionDAG &DAG);
34 virtual std::pair<SDOperand, SDOperand>
35 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
37 bool isTailCall, SDOperand Callee, ArgListTy &Args,
40 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
42 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
43 Value *VAListV, SelectionDAG &DAG);
44 virtual std::pair<SDOperand,SDOperand>
45 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
46 const Type *ArgTy, SelectionDAG &DAG);
47 virtual std::pair<SDOperand, SDOperand>
48 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
53 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
54 : TargetLowering(TM) {
56 // Set up the register classes.
57 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
58 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
59 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
61 computeRegisterProperties();
64 std::vector<SDOperand>
65 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
70 std::pair<SDOperand, SDOperand>
71 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
72 bool isVarArg, unsigned CC,
73 bool isTailCall, SDOperand Callee,
74 ArgListTy &Args, SelectionDAG &DAG) {
79 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
85 SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
86 Value *VAListV, SelectionDAG &DAG) {
91 std::pair<SDOperand,SDOperand>
92 SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
93 const Type *ArgTy, SelectionDAG &DAG) {
98 std::pair<SDOperand, SDOperand>
99 SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
101 assert(0 && "Unimp");
105 //===----------------------------------------------------------------------===//
106 // Instruction Selector Implementation
107 //===----------------------------------------------------------------------===//
109 //===--------------------------------------------------------------------===//
110 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
111 /// instructions for SelectionDAG operations.
114 class SparcV8DAGToDAGISel : public SelectionDAGISel {
115 SparcV8TargetLowering V8Lowering;
117 SparcV8DAGToDAGISel(TargetMachine &TM)
118 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
120 SDOperand Select(SDOperand Op);
122 /// InstructionSelectBasicBlock - This callback is invoked by
123 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
124 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
126 virtual const char *getPassName() const {
127 return "PowerPC DAG->DAG Pattern Instruction Selection";
130 // Include the pieces autogenerated from the target description.
131 #include "SparcV8GenDAGISel.inc"
133 } // end anonymous namespace
135 /// InstructionSelectBasicBlock - This callback is invoked by
136 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
137 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
140 // Select target instructions for the DAG.
141 DAG.setRoot(Select(DAG.getRoot()));
143 DAG.RemoveDeadNodes();
145 // Emit machine code to BB.
146 ScheduleAndEmitDAG(DAG);
150 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
152 if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
153 N->getOpcode() < V8ISD::FIRST_NUMBER*/)
154 return Op; // Already selected.
155 // If this has already been converted, use it.
156 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
157 if (CGMI != CodeGenMap.end()) return CGMI->second;
159 switch (N->getOpcode()) {
163 return SelectCode(Op);
167 /// createPPCISelDag - This pass converts a legalized DAG into a
168 /// PowerPC-specific DAG, ready for instruction scheduling.
170 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
171 return new SparcV8DAGToDAGISel(TM);