1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/SelectionDAGISel.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Support/Debug.h"
26 //===----------------------------------------------------------------------===//
27 // TargetLowering Implementation
28 //===----------------------------------------------------------------------===//
31 class SparcV8TargetLowering : public TargetLowering {
33 SparcV8TargetLowering(TargetMachine &TM);
35 virtual std::vector<SDOperand>
36 LowerArguments(Function &F, SelectionDAG &DAG);
37 virtual std::pair<SDOperand, SDOperand>
38 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
40 bool isTailCall, SDOperand Callee, ArgListTy &Args,
43 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
45 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
46 Value *VAListV, SelectionDAG &DAG);
47 virtual std::pair<SDOperand,SDOperand>
48 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
49 const Type *ArgTy, SelectionDAG &DAG);
50 virtual std::pair<SDOperand, SDOperand>
51 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
56 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
57 : TargetLowering(TM) {
59 // Set up the register classes.
60 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
61 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
62 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
64 // Sparc doesn't have sext_inreg, replace them with shl/sra
65 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
66 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
67 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
69 // Sparc has no REM operation.
70 setOperationAction(ISD::UREM, MVT::i32, Expand);
71 setOperationAction(ISD::SREM, MVT::i32, Expand);
73 computeRegisterProperties();
76 std::vector<SDOperand>
77 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
78 MachineFunction &MF = DAG.getMachineFunction();
79 SSARegMap *RegMap = MF.getSSARegMap();
80 std::vector<SDOperand> ArgValues;
82 static const unsigned GPR[] = {
83 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
86 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
87 MVT::ValueType ObjectVT = getValueType(I->getType());
88 assert(ArgNo < 6 && "Only args in regs for now");
91 default: assert(0 && "Unhandled argument type!");
92 // TODO: MVT::i64 & FP
97 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
98 MF.addLiveIn(GPR[ArgNo++], VReg);
99 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
100 DAG.setRoot(Arg.getValue(1));
101 if (ObjectVT != MVT::i32) {
102 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
104 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
105 DAG.getValueType(ObjectVT));
106 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
108 ArgValues.push_back(Arg);
112 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
113 MF.addLiveIn(GPR[ArgNo++], VRegLo);
114 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
115 MF.addLiveIn(GPR[ArgNo++], VRegHi);
116 SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
117 SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
118 DAG.setRoot(ArgHi.getValue(1));
119 ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
125 assert(!F.isVarArg() && "Unimp");
127 // Finally, inform the code generator which regs we return values in.
128 switch (getValueType(F.getReturnType())) {
129 default: assert(0 && "Unknown type!");
130 case MVT::isVoid: break;
135 MF.addLiveOut(V8::I0);
138 MF.addLiveOut(V8::I0);
139 MF.addLiveOut(V8::I1);
142 MF.addLiveOut(V8::F0);
145 MF.addLiveOut(V8::D0);
152 std::pair<SDOperand, SDOperand>
153 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
154 bool isVarArg, unsigned CC,
155 bool isTailCall, SDOperand Callee,
156 ArgListTy &Args, SelectionDAG &DAG) {
157 assert(0 && "Unimp");
161 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
163 if (Op.getValueType() == MVT::i64) {
164 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
165 DAG.getConstant(1, MVT::i32));
166 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
167 DAG.getConstant(0, MVT::i32));
168 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
170 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
174 SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
175 Value *VAListV, SelectionDAG &DAG) {
176 assert(0 && "Unimp");
180 std::pair<SDOperand,SDOperand>
181 SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
182 const Type *ArgTy, SelectionDAG &DAG) {
183 assert(0 && "Unimp");
187 std::pair<SDOperand, SDOperand>
188 SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
190 assert(0 && "Unimp");
194 //===----------------------------------------------------------------------===//
195 // Instruction Selector Implementation
196 //===----------------------------------------------------------------------===//
198 //===--------------------------------------------------------------------===//
199 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
200 /// instructions for SelectionDAG operations.
203 class SparcV8DAGToDAGISel : public SelectionDAGISel {
204 SparcV8TargetLowering V8Lowering;
206 SparcV8DAGToDAGISel(TargetMachine &TM)
207 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
209 SDOperand Select(SDOperand Op);
211 // Complex Pattern Selectors.
212 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
213 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
215 /// InstructionSelectBasicBlock - This callback is invoked by
216 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
217 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
219 virtual const char *getPassName() const {
220 return "PowerPC DAG->DAG Pattern Instruction Selection";
223 // Include the pieces autogenerated from the target description.
224 #include "SparcV8GenDAGISel.inc"
226 } // end anonymous namespace
228 /// InstructionSelectBasicBlock - This callback is invoked by
229 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
230 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
233 // Select target instructions for the DAG.
234 DAG.setRoot(Select(DAG.getRoot()));
236 DAG.RemoveDeadNodes();
238 // Emit machine code to BB.
239 ScheduleAndEmitDAG(DAG);
242 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
244 if (Addr.getOpcode() == ISD::ADD) {
245 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
246 Predicate_simm13(Addr.getOperand(1).Val))
247 return false; // Let the reg+imm pattern catch this!
248 R1 = Addr.getOperand(0);
249 R2 = Addr.getOperand(1);
254 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
258 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
260 if (Addr.getOpcode() == ISD::ADD) {
261 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
262 if (Predicate_simm13(CN)) {
263 Base = Addr.getOperand(0);
264 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
269 Offset = CurDAG->getTargetConstant(0, MVT::i32);
274 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
276 if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
277 N->getOpcode() < V8ISD::FIRST_NUMBER*/)
278 return Op; // Already selected.
279 // If this has already been converted, use it.
280 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
281 if (CGMI != CodeGenMap.end()) return CGMI->second;
283 switch (N->getOpcode()) {
287 // FIXME: should use a custom expander to expose the SRA to the dag.
288 SDOperand DivLHS = Select(N->getOperand(0));
289 SDOperand DivRHS = Select(N->getOperand(1));
291 // Set the Y register to the high-part.
293 if (N->getOpcode() == ISD::SDIV) {
294 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
295 CurDAG->getTargetConstant(31, MVT::i32));
297 TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
299 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
300 CurDAG->getRegister(V8::G0, MVT::i32));
302 // FIXME: Handle div by immediate.
303 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
304 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
308 // FIXME: Handle mul by immediate.
309 SDOperand MulLHS = Select(N->getOperand(0));
310 SDOperand MulRHS = Select(N->getOperand(1));
311 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
312 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
314 // The high part is in the Y register.
315 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
319 if (N->getNumOperands() == 2) {
320 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
321 SDOperand Val = Select(N->getOperand(1));
322 if (N->getOperand(1).getValueType() == MVT::i32) {
323 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
324 } else if (N->getOperand(1).getValueType() == MVT::f32) {
325 Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
327 assert(N->getOperand(1).getValueType() == MVT::f64);
328 Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
330 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
331 } else if (N->getNumOperands() > 1) {
332 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
333 assert(N->getOperand(1).getValueType() == MVT::i32 &&
334 N->getOperand(2).getValueType() == MVT::i32 &&
335 N->getNumOperands() == 3 && "Unknown two-register ret value!");
336 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(1)));
337 Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(2)));
338 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
340 break; // Generated code handles the void case.
344 return SelectCode(Op);
348 /// createPPCISelDag - This pass converts a legalized DAG into a
349 /// PowerPC-specific DAG, ready for instruction scheduling.
351 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
352 return new SparcV8DAGToDAGISel(TM);