1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcISelLowering.h"
15 #include "SparcTargetMachine.h"
16 #include "llvm/Intrinsics.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
24 //===----------------------------------------------------------------------===//
25 // Instruction Selector Implementation
26 //===----------------------------------------------------------------------===//
28 //===--------------------------------------------------------------------===//
29 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
30 /// instructions for SelectionDAG operations.
33 class SparcDAGToDAGISel : public SelectionDAGISel {
34 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
35 /// make the right decision when generating code for different targets.
36 const SparcSubtarget &Subtarget;
37 SparcTargetMachine& TM;
38 MachineBasicBlock *CurBB;
40 explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
41 : SelectionDAGISel(tm),
42 Subtarget(tm.getSubtarget<SparcSubtarget>()),
46 SDNode *Select(SDValue Op);
48 // Complex Pattern Selectors.
49 bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
50 bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
53 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
54 /// inline asm expressions.
55 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
57 std::vector<SDValue> &OutOps);
59 /// InstructionSelect - This callback is invoked by
60 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
61 virtual void InstructionSelect();
63 virtual const char *getPassName() const {
64 return "SPARC DAG->DAG Pattern Instruction Selection";
67 // Include the pieces autogenerated from the target description.
68 #include "SparcGenDAGISel.inc"
71 SDNode* getGlobalBaseReg();
73 } // end anonymous namespace
75 /// InstructionSelect - This callback is invoked by
76 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
77 void SparcDAGToDAGISel::InstructionSelect() {
79 // Select target instructions for the DAG.
81 CurDAG->RemoveDeadNodes();
84 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
85 MachineFunction *MF = CurBB->getParent();
86 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
87 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
90 bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
91 SDValue &Base, SDValue &Offset) {
92 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
93 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
94 Offset = CurDAG->getTargetConstant(0, MVT::i32);
97 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
98 Addr.getOpcode() == ISD::TargetGlobalAddress)
99 return false; // direct calls.
101 if (Addr.getOpcode() == ISD::ADD) {
102 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
103 if (Predicate_simm13(CN)) {
104 if (FrameIndexSDNode *FIN =
105 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
106 // Constant offset from frame ref.
107 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
109 Base = Addr.getOperand(0);
111 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
115 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
116 Base = Addr.getOperand(1);
117 Offset = Addr.getOperand(0).getOperand(0);
120 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
121 Base = Addr.getOperand(0);
122 Offset = Addr.getOperand(1).getOperand(0);
127 Offset = CurDAG->getTargetConstant(0, MVT::i32);
131 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
132 SDValue &R1, SDValue &R2) {
133 if (Addr.getOpcode() == ISD::FrameIndex) return false;
134 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
135 Addr.getOpcode() == ISD::TargetGlobalAddress)
136 return false; // direct calls.
138 if (Addr.getOpcode() == ISD::ADD) {
139 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
140 Predicate_simm13(Addr.getOperand(1).getNode()))
141 return false; // Let the reg+imm pattern catch this!
142 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
143 Addr.getOperand(1).getOpcode() == SPISD::Lo)
144 return false; // Let the reg+imm pattern catch this!
145 R1 = Addr.getOperand(0);
146 R2 = Addr.getOperand(1);
151 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
155 SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
156 SDNode *N = Op.getNode();
157 DebugLoc dl = N->getDebugLoc();
158 if (N->isMachineOpcode())
159 return NULL; // Already selected.
161 switch (N->getOpcode()) {
163 case SPISD::GLOBAL_BASE_REG:
164 return getGlobalBaseReg();
168 // FIXME: should use a custom expander to expose the SRA to the dag.
169 SDValue DivLHS = N->getOperand(0);
170 SDValue DivRHS = N->getOperand(1);
172 // Set the Y register to the high-part.
174 if (N->getOpcode() == ISD::SDIV) {
175 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
176 CurDAG->getTargetConstant(31, MVT::i32)), 0);
178 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
180 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Flag, TopPart,
181 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
183 // FIXME: Handle div by immediate.
184 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
185 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
190 // FIXME: Handle mul by immediate.
191 SDValue MulLHS = N->getOperand(0);
192 SDValue MulRHS = N->getOperand(1);
193 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
194 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
196 // The high part is in the Y register.
197 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
202 return SelectCode(Op);
206 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
207 /// inline asm expressions.
209 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
211 std::vector<SDValue> &OutOps) {
213 switch (ConstraintCode) {
214 default: return true;
216 if (!SelectADDRrr(Op, Op, Op0, Op1))
217 SelectADDRri(Op, Op, Op0, Op1);
221 OutOps.push_back(Op0);
222 OutOps.push_back(Op1);
226 /// createSparcISelDag - This pass converts a legalized DAG into a
227 /// SPARC-specific DAG, ready for instruction scheduling.
229 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
230 return new SparcDAGToDAGISel(TM);