1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
30 //===----------------------------------------------------------------------===//
31 // TargetLowering Implementation
32 //===----------------------------------------------------------------------===//
36 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
37 CMPICC, // Compare two GPR operands, set icc.
38 CMPFCC, // Compare two FP operands, set fcc.
39 BRICC, // Branch to dest on icc condition
40 BRFCC, // Branch to dest on fcc condition
41 SELECT_ICC, // Select between two values using the current ICC flags.
42 SELECT_FCC, // Select between two values using the current FCC flags.
44 Hi, Lo, // Hi/Lo operations, typically on a global address.
46 FTOI, // FP to Int within a FP register.
47 ITOF, // Int to FP within a FP register.
49 CALL, // A call instruction.
50 RET_FLAG, // Return with a flag operand.
54 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
56 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
58 default: assert(0 && "Unknown integer condition code!");
59 case ISD::SETEQ: return SPCC::ICC_E;
60 case ISD::SETNE: return SPCC::ICC_NE;
61 case ISD::SETLT: return SPCC::ICC_L;
62 case ISD::SETGT: return SPCC::ICC_G;
63 case ISD::SETLE: return SPCC::ICC_LE;
64 case ISD::SETGE: return SPCC::ICC_GE;
65 case ISD::SETULT: return SPCC::ICC_CS;
66 case ISD::SETULE: return SPCC::ICC_LEU;
67 case ISD::SETUGT: return SPCC::ICC_GU;
68 case ISD::SETUGE: return SPCC::ICC_CC;
72 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
74 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
76 default: assert(0 && "Unknown fp condition code!");
77 case ISD::SETEQ: return SPCC::FCC_E;
78 case ISD::SETNE: return SPCC::FCC_NE;
79 case ISD::SETLT: return SPCC::FCC_L;
80 case ISD::SETGT: return SPCC::FCC_G;
81 case ISD::SETLE: return SPCC::FCC_LE;
82 case ISD::SETGE: return SPCC::FCC_GE;
83 case ISD::SETULT: return SPCC::FCC_UL;
84 case ISD::SETULE: return SPCC::FCC_ULE;
85 case ISD::SETUGT: return SPCC::FCC_UG;
86 case ISD::SETUGE: return SPCC::FCC_UGE;
87 case ISD::SETUO: return SPCC::FCC_U;
88 case ISD::SETO: return SPCC::FCC_O;
89 case ISD::SETONE: return SPCC::FCC_LG;
90 case ISD::SETUEQ: return SPCC::FCC_UE;
95 class SparcTargetLowering : public TargetLowering {
96 int VarArgsFrameOffset; // Frame offset to start of varargs area.
98 SparcTargetLowering(TargetMachine &TM);
99 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
101 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
102 /// in Mask are known to be either zero or one and return them in the
103 /// KnownZero/KnownOne bitsets.
104 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
108 unsigned Depth = 0) const;
110 virtual std::vector<SDOperand>
111 LowerArguments(Function &F, SelectionDAG &DAG);
112 virtual std::pair<SDOperand, SDOperand>
113 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
115 bool isTailCall, SDOperand Callee, ArgListTy &Args,
117 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
118 MachineBasicBlock *MBB);
120 virtual const char *getTargetNodeName(unsigned Opcode) const;
124 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
125 : TargetLowering(TM) {
127 // Set up the register classes.
128 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
129 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
130 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
132 // Custom legalize GlobalAddress nodes into LO/HI parts.
133 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
134 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
136 // Sparc doesn't have sext_inreg, replace them with shl/sra
137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
141 // Sparc has no REM operation.
142 setOperationAction(ISD::UREM, MVT::i32, Expand);
143 setOperationAction(ISD::SREM, MVT::i32, Expand);
145 // Custom expand fp<->sint
146 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
147 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
150 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
153 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
156 // Turn FP extload into load/fextend
157 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
159 // Sparc has no select or setcc: expand to SELECT_CC.
160 setOperationAction(ISD::SELECT, MVT::i32, Expand);
161 setOperationAction(ISD::SELECT, MVT::f32, Expand);
162 setOperationAction(ISD::SELECT, MVT::f64, Expand);
163 setOperationAction(ISD::SETCC, MVT::i32, Expand);
164 setOperationAction(ISD::SETCC, MVT::f32, Expand);
165 setOperationAction(ISD::SETCC, MVT::f64, Expand);
167 // Sparc doesn't have BRCOND either, it has BR_CC.
168 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
169 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
170 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
171 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
173 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
174 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
175 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
177 // SPARC has no intrinsics for these particular operations.
178 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
179 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
180 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
182 setOperationAction(ISD::FSIN , MVT::f64, Expand);
183 setOperationAction(ISD::FCOS , MVT::f64, Expand);
184 setOperationAction(ISD::FSIN , MVT::f32, Expand);
185 setOperationAction(ISD::FCOS , MVT::f32, Expand);
186 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
187 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
188 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
189 setOperationAction(ISD::ROTL , MVT::i32, Expand);
190 setOperationAction(ISD::ROTR , MVT::i32, Expand);
191 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
195 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
196 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
197 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
199 // We don't have line number support yet.
200 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
201 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
202 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
204 // RET must be custom lowered, to meet ABI requirements
205 setOperationAction(ISD::RET , MVT::Other, Custom);
207 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
208 setOperationAction(ISD::VASTART , MVT::Other, Custom);
209 // VAARG needs to be lowered to not do unaligned accesses for doubles.
210 setOperationAction(ISD::VAARG , MVT::Other, Custom);
212 // Use the default implementation.
213 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
214 setOperationAction(ISD::VAEND , MVT::Other, Expand);
215 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
216 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
217 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
219 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
220 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
222 setStackPointerRegisterToSaveRestore(SP::O6);
224 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
225 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
228 computeRegisterProperties();
231 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
234 case SPISD::CMPICC: return "SPISD::CMPICC";
235 case SPISD::CMPFCC: return "SPISD::CMPFCC";
236 case SPISD::BRICC: return "SPISD::BRICC";
237 case SPISD::BRFCC: return "SPISD::BRFCC";
238 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
239 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
240 case SPISD::Hi: return "SPISD::Hi";
241 case SPISD::Lo: return "SPISD::Lo";
242 case SPISD::FTOI: return "SPISD::FTOI";
243 case SPISD::ITOF: return "SPISD::ITOF";
244 case SPISD::CALL: return "SPISD::CALL";
245 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
249 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
250 /// be zero. Op is expected to be a target specific node. Used by DAG
252 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
256 unsigned Depth) const {
257 uint64_t KnownZero2, KnownOne2;
258 KnownZero = KnownOne = 0; // Don't know anything.
260 switch (Op.getOpcode()) {
262 case SPISD::SELECT_ICC:
263 case SPISD::SELECT_FCC:
264 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
265 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
266 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
267 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
269 // Only known if known in both the LHS and RHS.
270 KnownOne &= KnownOne2;
271 KnownZero &= KnownZero2;
276 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
277 /// either one or two GPRs, including FP values. TODO: we should pass FP values
278 /// in FP registers for fastcc functions.
279 std::vector<SDOperand>
280 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
281 MachineFunction &MF = DAG.getMachineFunction();
282 SSARegMap *RegMap = MF.getSSARegMap();
283 std::vector<SDOperand> ArgValues;
285 static const unsigned ArgRegs[] = {
286 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
289 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
290 unsigned ArgOffset = 68;
292 SDOperand Root = DAG.getRoot();
293 std::vector<SDOperand> OutChains;
295 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
296 MVT::ValueType ObjectVT = getValueType(I->getType());
299 default: assert(0 && "Unhandled argument type!");
304 if (I->use_empty()) { // Argument is dead.
305 if (CurArgReg < ArgRegEnd) ++CurArgReg;
306 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
307 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
308 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
309 MF.addLiveIn(*CurArgReg++, VReg);
310 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
311 if (ObjectVT != MVT::i32) {
312 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
314 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
315 DAG.getValueType(ObjectVT));
316 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
318 ArgValues.push_back(Arg);
320 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
321 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
323 if (ObjectVT == MVT::i32) {
324 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
327 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
329 // Sparc is big endian, so add an offset based on the ObjectVT.
330 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
331 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
332 DAG.getConstant(Offset, MVT::i32));
333 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
334 DAG.getSrcValue(0), ObjectVT);
335 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
337 ArgValues.push_back(Load);
343 if (I->use_empty()) { // Argument is dead.
344 if (CurArgReg < ArgRegEnd) ++CurArgReg;
345 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
346 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
347 // FP value is passed in an integer register.
348 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
349 MF.addLiveIn(*CurArgReg++, VReg);
350 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
352 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
353 ArgValues.push_back(Arg);
355 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
356 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
357 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
358 ArgValues.push_back(Load);
365 if (I->use_empty()) { // Argument is dead.
366 if (CurArgReg < ArgRegEnd) ++CurArgReg;
367 if (CurArgReg < ArgRegEnd) ++CurArgReg;
368 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
369 } else if (/* FIXME: Apparently this isn't safe?? */
370 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
371 ((CurArgReg-ArgRegs) & 1) == 0) {
372 // If this is a double argument and the whole thing lives on the stack,
373 // and the argument is aligned, load the double straight from the stack.
374 // We can't do a load in cases like void foo([6ints], int,double),
375 // because the double wouldn't be aligned!
376 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
377 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
378 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
379 DAG.getSrcValue(0)));
382 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
383 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
384 MF.addLiveIn(*CurArgReg++, VRegHi);
385 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
387 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
388 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
389 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
393 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
394 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
395 MF.addLiveIn(*CurArgReg++, VRegLo);
396 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
398 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
399 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
400 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
403 // Compose the two halves together into an i64 unit.
404 SDOperand WholeValue =
405 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
407 // If we want a double, do a bit convert.
408 if (ObjectVT == MVT::f64)
409 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
411 ArgValues.push_back(WholeValue);
418 // Store remaining ArgRegs to the stack if this is a varargs function.
419 if (F.getFunctionType()->isVarArg()) {
420 // Remember the vararg offset for the va_start implementation.
421 VarArgsFrameOffset = ArgOffset;
423 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
424 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
425 MF.addLiveIn(*CurArgReg, VReg);
426 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
428 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
429 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
431 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
432 Arg, FIPtr, DAG.getSrcValue(0)));
437 if (!OutChains.empty())
438 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
440 // Finally, inform the code generator which regs we return values in.
441 switch (getValueType(F.getReturnType())) {
442 default: assert(0 && "Unknown type!");
443 case MVT::isVoid: break;
448 MF.addLiveOut(SP::I0);
451 MF.addLiveOut(SP::I0);
452 MF.addLiveOut(SP::I1);
455 MF.addLiveOut(SP::F0);
458 MF.addLiveOut(SP::D0);
465 std::pair<SDOperand, SDOperand>
466 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
467 bool isVarArg, unsigned CC,
468 bool isTailCall, SDOperand Callee,
469 ArgListTy &Args, SelectionDAG &DAG) {
470 MachineFunction &MF = DAG.getMachineFunction();
471 // Count the size of the outgoing arguments.
472 unsigned ArgsSize = 0;
473 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
474 switch (getValueType(Args[i].second)) {
475 default: assert(0 && "Unknown value type!");
490 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
494 // Keep stack frames 8-byte aligned.
495 ArgsSize = (ArgsSize+7) & ~7;
497 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
499 SDOperand StackPtr, NullSV;
500 std::vector<SDOperand> Stores;
501 std::vector<SDOperand> RegValuesToPass;
502 unsigned ArgOffset = 68;
503 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
504 SDOperand Val = Args[i].first;
505 MVT::ValueType ObjectVT = Val.getValueType();
506 SDOperand ValToStore(0, 0);
509 default: assert(0 && "Unhandled argument type!");
513 // Promote the integer to 32-bits. If the input type is signed, use a
514 // sign extend, otherwise use a zero extend.
515 if (Args[i].second->isSigned())
516 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
518 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
523 if (RegValuesToPass.size() >= 6) {
526 RegValuesToPass.push_back(Val);
531 if (RegValuesToPass.size() >= 6) {
534 // Convert this to a FP value in an int reg.
535 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
536 RegValuesToPass.push_back(Val);
541 // If we can store this directly into the outgoing slot, do so. We can
542 // do this when all ArgRegs are used and if the outgoing slot is aligned.
543 // FIXME: McGill/misr fails with this.
544 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
549 // Otherwise, convert this to a FP value in int regs.
550 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
554 if (RegValuesToPass.size() >= 6) {
555 ValToStore = Val; // Whole thing is passed in memory.
559 // Split the value into top and bottom part. Top part goes in a reg.
560 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
561 DAG.getConstant(1, MVT::i32));
562 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
563 DAG.getConstant(0, MVT::i32));
564 RegValuesToPass.push_back(Hi);
566 if (RegValuesToPass.size() >= 6) {
571 RegValuesToPass.push_back(Lo);
576 if (ValToStore.Val) {
578 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
579 NullSV = DAG.getSrcValue(NULL);
581 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
582 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
583 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
584 ValToStore, PtrOff, NullSV));
586 ArgOffset += ObjSize;
589 // Emit all stores, make sure the occur before any copies into physregs.
591 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
593 static const unsigned ArgRegs[] = {
594 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
597 // Build a sequence of copy-to-reg nodes chained together with token chain
598 // and flag operands which copy the outgoing args into O[0-5].
600 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
601 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
602 InFlag = Chain.getValue(1);
605 // If the callee is a GlobalAddress node (quite common, every direct call is)
606 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
607 // Likewise ExternalSymbol -> TargetExternalSymbol.
608 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
609 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
610 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
611 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
613 std::vector<MVT::ValueType> NodeTys;
614 NodeTys.push_back(MVT::Other); // Returns a chain
615 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
616 std::vector<SDOperand> Ops;
617 Ops.push_back(Chain);
618 Ops.push_back(Callee);
620 Ops.push_back(InFlag);
621 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
622 InFlag = Chain.getValue(1);
624 MVT::ValueType RetTyVT = getValueType(RetTy);
626 if (RetTyVT != MVT::isVoid) {
628 default: assert(0 && "Unknown value type to return!");
632 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
633 Chain = RetVal.getValue(1);
635 // Add a note to keep track of whether it is sign or zero extended.
636 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
637 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
638 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
641 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
642 Chain = RetVal.getValue(1);
645 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
646 Chain = RetVal.getValue(1);
649 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
650 Chain = RetVal.getValue(1);
653 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
654 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
656 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
657 Chain = Hi.getValue(1);
662 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
663 DAG.getConstant(ArgsSize, getPointerTy()));
665 return std::make_pair(RetVal, Chain);
668 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
669 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
670 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
671 ISD::CondCode CC, unsigned &SPCC) {
672 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
674 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
675 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
676 (LHS.getOpcode() == SPISD::SELECT_FCC &&
677 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
678 isa<ConstantSDNode>(LHS.getOperand(0)) &&
679 isa<ConstantSDNode>(LHS.getOperand(1)) &&
680 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
681 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
682 SDOperand CMPCC = LHS.getOperand(3);
683 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
684 LHS = CMPCC.getOperand(0);
685 RHS = CMPCC.getOperand(1);
690 SDOperand SparcTargetLowering::
691 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
692 switch (Op.getOpcode()) {
693 default: assert(0 && "Should not custom lower this!");
694 case ISD::GlobalAddress: {
695 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
696 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
697 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
698 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
699 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
701 case ISD::ConstantPool: {
702 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
703 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
704 cast<ConstantPoolSDNode>(Op)->getAlignment());
705 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
706 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
707 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
709 case ISD::FP_TO_SINT:
710 // Convert the fp value to integer in an FP register.
711 assert(Op.getValueType() == MVT::i32);
712 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
713 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
714 case ISD::SINT_TO_FP: {
715 assert(Op.getOperand(0).getValueType() == MVT::i32);
716 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
717 // Convert the int value to FP in an FP register.
718 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
721 SDOperand Chain = Op.getOperand(0);
722 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
723 SDOperand LHS = Op.getOperand(2);
724 SDOperand RHS = Op.getOperand(3);
725 SDOperand Dest = Op.getOperand(4);
726 unsigned Opc, SPCC = ~0U;
728 // If this is a br_cc of a "setcc", and if the setcc got lowered into
729 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
730 LookThroughSetCC(LHS, RHS, CC, SPCC);
732 // Get the condition flag.
733 SDOperand CompareFlag;
734 if (LHS.getValueType() == MVT::i32) {
735 std::vector<MVT::ValueType> VTs;
736 VTs.push_back(MVT::i32);
737 VTs.push_back(MVT::Flag);
738 std::vector<SDOperand> Ops;
741 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
742 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
745 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
746 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
749 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
750 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
752 case ISD::SELECT_CC: {
753 SDOperand LHS = Op.getOperand(0);
754 SDOperand RHS = Op.getOperand(1);
755 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
756 SDOperand TrueVal = Op.getOperand(2);
757 SDOperand FalseVal = Op.getOperand(3);
758 unsigned Opc, SPCC = ~0U;
760 // If this is a select_cc of a "setcc", and if the setcc got lowered into
761 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
762 LookThroughSetCC(LHS, RHS, CC, SPCC);
764 SDOperand CompareFlag;
765 if (LHS.getValueType() == MVT::i32) {
766 std::vector<MVT::ValueType> VTs;
767 VTs.push_back(LHS.getValueType()); // subcc returns a value
768 VTs.push_back(MVT::Flag);
769 std::vector<SDOperand> Ops;
772 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
773 Opc = SPISD::SELECT_ICC;
774 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
776 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
777 Opc = SPISD::SELECT_FCC;
778 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
780 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
781 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
784 // vastart just stores the address of the VarArgsFrameIndex slot into the
785 // memory location argument.
786 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
787 DAG.getRegister(SP::I6, MVT::i32),
788 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
789 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
790 Op.getOperand(1), Op.getOperand(2));
793 SDNode *Node = Op.Val;
794 MVT::ValueType VT = Node->getValueType(0);
795 SDOperand InChain = Node->getOperand(0);
796 SDOperand VAListPtr = Node->getOperand(1);
797 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
798 Node->getOperand(2));
799 // Increment the pointer, VAList, to the next vaarg
800 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
801 DAG.getConstant(MVT::getSizeInBits(VT)/8,
803 // Store the incremented VAList to the legalized pointer
804 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
805 VAListPtr, Node->getOperand(2));
806 // Load the actual argument out of the pointer VAList, unless this is an
808 if (VT != MVT::f64) {
809 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
811 // Otherwise, load it as i64, then do a bitconvert.
812 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
813 std::vector<MVT::ValueType> Tys;
814 Tys.push_back(MVT::f64);
815 Tys.push_back(MVT::Other);
816 std::vector<SDOperand> Ops;
817 // Bit-Convert the value to f64.
818 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
819 Ops.push_back(V.getValue(1));
820 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
823 case ISD::DYNAMIC_STACKALLOC: {
824 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
825 SDOperand Size = Op.getOperand(1); // Legalize the size.
827 unsigned SPReg = SP::O6;
828 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
829 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
830 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
832 // The resultant pointer is actually 16 words from the bottom of the stack,
833 // to provide a register spill area.
834 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
835 DAG.getConstant(96, MVT::i32));
836 std::vector<MVT::ValueType> Tys;
837 Tys.push_back(MVT::i32);
838 Tys.push_back(MVT::Other);
839 std::vector<SDOperand> Ops;
840 Ops.push_back(NewVal);
841 Ops.push_back(Chain);
842 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
847 switch(Op.getNumOperands()) {
849 assert(0 && "Do not know how to return this many arguments!");
852 return SDOperand(); // ret void is legal
855 switch(Op.getOperand(1).getValueType()) {
856 default: assert(0 && "Unknown type to return!");
857 case MVT::i32: ArgReg = SP::I0; break;
858 case MVT::f32: ArgReg = SP::F0; break;
859 case MVT::f64: ArgReg = SP::D0; break;
861 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
866 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
868 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
871 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
877 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
878 MachineBasicBlock *BB) {
881 // Figure out the conditional branch opcode to use for this select_cc.
882 switch (MI->getOpcode()) {
883 default: assert(0 && "Unknown SELECT_CC!");
884 case SP::SELECT_CC_Int_ICC:
885 case SP::SELECT_CC_FP_ICC:
886 case SP::SELECT_CC_DFP_ICC:
887 BROpcode = SP::BCOND;
889 case SP::SELECT_CC_Int_FCC:
890 case SP::SELECT_CC_FP_FCC:
891 case SP::SELECT_CC_DFP_FCC:
892 BROpcode = SP::FBCOND;
896 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
898 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
899 // control-flow pattern. The incoming instruction knows the destination vreg
900 // to set, the condition code register to branch on, the true/false values to
901 // select between, and a branch opcode to use.
902 const BasicBlock *LLVM_BB = BB->getBasicBlock();
903 ilist<MachineBasicBlock>::iterator It = BB;
910 // fallthrough --> copy0MBB
911 MachineBasicBlock *thisMBB = BB;
912 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
913 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
914 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
915 MachineFunction *F = BB->getParent();
916 F->getBasicBlockList().insert(It, copy0MBB);
917 F->getBasicBlockList().insert(It, sinkMBB);
918 // Update machine-CFG edges
919 BB->addSuccessor(copy0MBB);
920 BB->addSuccessor(sinkMBB);
924 // # fallthrough to sinkMBB
927 // Update machine-CFG edges
928 BB->addSuccessor(sinkMBB);
931 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
934 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
935 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
936 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
938 delete MI; // The pseudo instruction is gone now.
942 //===----------------------------------------------------------------------===//
943 // Instruction Selector Implementation
944 //===----------------------------------------------------------------------===//
946 //===--------------------------------------------------------------------===//
947 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
948 /// instructions for SelectionDAG operations.
951 class SparcDAGToDAGISel : public SelectionDAGISel {
952 SparcTargetLowering Lowering;
954 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
955 /// make the right decision when generating code for different targets.
956 const SparcSubtarget &Subtarget;
958 SparcDAGToDAGISel(TargetMachine &TM)
959 : SelectionDAGISel(Lowering), Lowering(TM),
960 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
963 void Select(SDOperand &Result, SDOperand Op);
965 // Complex Pattern Selectors.
966 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
967 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
969 /// InstructionSelectBasicBlock - This callback is invoked by
970 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
971 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
973 virtual const char *getPassName() const {
974 return "SPARC DAG->DAG Pattern Instruction Selection";
977 // Include the pieces autogenerated from the target description.
978 #include "SparcGenDAGISel.inc"
980 } // end anonymous namespace
982 /// InstructionSelectBasicBlock - This callback is invoked by
983 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
984 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
987 // Select target instructions for the DAG.
988 DAG.setRoot(SelectRoot(DAG.getRoot()));
990 DAG.RemoveDeadNodes();
992 // Emit machine code to BB.
993 ScheduleAndEmitDAG(DAG);
996 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
998 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
999 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1000 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1003 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1004 Addr.getOpcode() == ISD::TargetGlobalAddress)
1005 return false; // direct calls.
1007 if (Addr.getOpcode() == ISD::ADD) {
1008 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1009 if (Predicate_simm13(CN)) {
1010 if (FrameIndexSDNode *FIN =
1011 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1012 // Constant offset from frame ref.
1013 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1015 Base = Addr.getOperand(0);
1017 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1021 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1022 Base = Addr.getOperand(1);
1023 Offset = Addr.getOperand(0).getOperand(0);
1026 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1027 Base = Addr.getOperand(0);
1028 Offset = Addr.getOperand(1).getOperand(0);
1033 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1037 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1039 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1040 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1041 Addr.getOpcode() == ISD::TargetGlobalAddress)
1042 return false; // direct calls.
1044 if (Addr.getOpcode() == ISD::ADD) {
1045 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1046 Predicate_simm13(Addr.getOperand(1).Val))
1047 return false; // Let the reg+imm pattern catch this!
1048 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1049 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1050 return false; // Let the reg+imm pattern catch this!
1051 R1 = Addr.getOperand(0);
1052 R2 = Addr.getOperand(1);
1057 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1061 void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
1063 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1064 N->getOpcode() < SPISD::FIRST_NUMBER) {
1066 return; // Already selected.
1069 // If this has already been converted, use it.
1070 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
1071 if (CGMI != CodeGenMap.end()) {
1072 Result = CGMI->second;
1076 switch (N->getOpcode()) {
1080 // FIXME: should use a custom expander to expose the SRA to the dag.
1081 SDOperand DivLHS, DivRHS;
1082 Select(DivLHS, N->getOperand(0));
1083 Select(DivRHS, N->getOperand(1));
1085 // Set the Y register to the high-part.
1087 if (N->getOpcode() == ISD::SDIV) {
1088 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1089 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1091 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1093 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1094 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1096 // FIXME: Handle div by immediate.
1097 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1098 Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
1103 // FIXME: Handle mul by immediate.
1104 SDOperand MulLHS, MulRHS;
1105 Select(MulLHS, N->getOperand(0));
1106 Select(MulRHS, N->getOperand(1));
1107 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1108 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1110 // The high part is in the Y register.
1111 Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1116 SelectCode(Result, Op);
1120 /// createSparcISelDag - This pass converts a legalized DAG into a
1121 /// SPARC-specific DAG, ready for instruction scheduling.
1123 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1124 return new SparcDAGToDAGISel(TM);