1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/SelectionDAGISel.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Support/Debug.h"
26 //===----------------------------------------------------------------------===//
27 // TargetLowering Implementation
28 //===----------------------------------------------------------------------===//
31 class SparcV8TargetLowering : public TargetLowering {
33 SparcV8TargetLowering(TargetMachine &TM);
35 virtual std::vector<SDOperand>
36 LowerArguments(Function &F, SelectionDAG &DAG);
37 virtual std::pair<SDOperand, SDOperand>
38 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
40 bool isTailCall, SDOperand Callee, ArgListTy &Args,
43 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
45 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
46 Value *VAListV, SelectionDAG &DAG);
47 virtual std::pair<SDOperand,SDOperand>
48 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
49 const Type *ArgTy, SelectionDAG &DAG);
50 virtual std::pair<SDOperand, SDOperand>
51 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
56 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
57 : TargetLowering(TM) {
59 // Set up the register classes.
60 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
61 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
62 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
64 // Sparc doesn't have sext_inreg, replace them with shl/sra
65 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
66 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
67 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
69 computeRegisterProperties();
72 std::vector<SDOperand>
73 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
74 MachineFunction &MF = DAG.getMachineFunction();
75 SSARegMap *RegMap = MF.getSSARegMap();
76 std::vector<SDOperand> ArgValues;
78 static const unsigned GPR[] = {
79 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
82 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
83 MVT::ValueType ObjectVT = getValueType(I->getType());
84 assert(ArgNo < 6 && "Only args in regs for now");
87 default: assert(0 && "Unhandled argument type!");
88 // TODO: MVT::i64 & FP
93 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
94 MF.addLiveIn(GPR[ArgNo++], VReg);
95 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
96 DAG.setRoot(Arg.getValue(1));
97 if (ObjectVT != MVT::i32) {
98 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
100 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
101 DAG.getValueType(ObjectVT));
102 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
104 ArgValues.push_back(Arg);
108 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
109 MF.addLiveIn(GPR[ArgNo++], VRegLo);
110 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
111 MF.addLiveIn(GPR[ArgNo++], VRegHi);
112 SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
113 SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
114 DAG.setRoot(ArgHi.getValue(1));
115 ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
121 assert(!F.isVarArg() && "Unimp");
123 // Finally, inform the code generator which regs we return values in.
124 switch (getValueType(F.getReturnType())) {
125 default: assert(0 && "Unknown type!");
126 case MVT::isVoid: break;
131 MF.addLiveOut(V8::I0);
134 MF.addLiveOut(V8::I0);
135 MF.addLiveOut(V8::I1);
138 MF.addLiveOut(V8::F0);
141 MF.addLiveOut(V8::D0);
148 std::pair<SDOperand, SDOperand>
149 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
150 bool isVarArg, unsigned CC,
151 bool isTailCall, SDOperand Callee,
152 ArgListTy &Args, SelectionDAG &DAG) {
153 assert(0 && "Unimp");
157 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
159 if (Op.getValueType() == MVT::i64) {
160 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
161 DAG.getConstant(1, MVT::i32));
162 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
163 DAG.getConstant(0, MVT::i32));
164 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
166 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
170 SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
171 Value *VAListV, SelectionDAG &DAG) {
172 assert(0 && "Unimp");
176 std::pair<SDOperand,SDOperand>
177 SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
178 const Type *ArgTy, SelectionDAG &DAG) {
179 assert(0 && "Unimp");
183 std::pair<SDOperand, SDOperand>
184 SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
186 assert(0 && "Unimp");
190 //===----------------------------------------------------------------------===//
191 // Instruction Selector Implementation
192 //===----------------------------------------------------------------------===//
194 //===--------------------------------------------------------------------===//
195 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
196 /// instructions for SelectionDAG operations.
199 class SparcV8DAGToDAGISel : public SelectionDAGISel {
200 SparcV8TargetLowering V8Lowering;
202 SparcV8DAGToDAGISel(TargetMachine &TM)
203 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
205 SDOperand Select(SDOperand Op);
207 // Complex Pattern Selectors.
208 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
209 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
211 /// InstructionSelectBasicBlock - This callback is invoked by
212 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
213 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
215 virtual const char *getPassName() const {
216 return "PowerPC DAG->DAG Pattern Instruction Selection";
219 // Include the pieces autogenerated from the target description.
220 #include "SparcV8GenDAGISel.inc"
222 } // end anonymous namespace
224 /// InstructionSelectBasicBlock - This callback is invoked by
225 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
226 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
229 // Select target instructions for the DAG.
230 DAG.setRoot(Select(DAG.getRoot()));
232 DAG.RemoveDeadNodes();
234 // Emit machine code to BB.
235 ScheduleAndEmitDAG(DAG);
238 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
240 if (Addr.getOpcode() == ISD::ADD) {
241 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
242 Predicate_simm13(Addr.getOperand(1).Val))
243 return false; // Let the reg+imm pattern catch this!
244 R1 = Addr.getOperand(0);
245 R2 = Addr.getOperand(1);
250 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
254 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
256 if (Addr.getOpcode() == ISD::ADD) {
257 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
258 if (Predicate_simm13(CN)) {
259 Base = Addr.getOperand(0);
260 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
265 Offset = CurDAG->getTargetConstant(0, MVT::i32);
270 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
272 if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
273 N->getOpcode() < V8ISD::FIRST_NUMBER*/)
274 return Op; // Already selected.
275 // If this has already been converted, use it.
276 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
277 if (CGMI != CodeGenMap.end()) return CGMI->second;
279 switch (N->getOpcode()) {
282 if (N->getNumOperands() == 2) {
283 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
284 SDOperand Val = Select(N->getOperand(1));
285 if (N->getOperand(1).getValueType() == MVT::i32) {
286 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
287 } else if (N->getOperand(1).getValueType() == MVT::f32) {
288 Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
290 assert(N->getOperand(1).getValueType() == MVT::f64);
291 Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
293 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
294 } else if (N->getNumOperands() > 1) {
295 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
296 assert(N->getOperand(1).getValueType() == MVT::i32 &&
297 N->getOperand(2).getValueType() == MVT::i32 &&
298 N->getNumOperands() == 3 && "Unknown two-register ret value!");
299 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(1)));
300 Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(2)));
301 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
303 break; // Generated code handles the void case.
307 return SelectCode(Op);
311 /// createPPCISelDag - This pass converts a legalized DAG into a
312 /// PowerPC-specific DAG, ready for instruction scheduling.
314 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
315 return new SparcV8DAGToDAGISel(TM);