1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/SelectionDAGISel.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Support/Debug.h"
26 //===----------------------------------------------------------------------===//
27 // TargetLowering Implementation
28 //===----------------------------------------------------------------------===//
31 class SparcV8TargetLowering : public TargetLowering {
33 SparcV8TargetLowering(TargetMachine &TM);
35 virtual std::vector<SDOperand>
36 LowerArguments(Function &F, SelectionDAG &DAG);
37 virtual std::pair<SDOperand, SDOperand>
38 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
40 bool isTailCall, SDOperand Callee, ArgListTy &Args,
43 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
45 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
46 Value *VAListV, SelectionDAG &DAG);
47 virtual std::pair<SDOperand,SDOperand>
48 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
49 const Type *ArgTy, SelectionDAG &DAG);
50 virtual std::pair<SDOperand, SDOperand>
51 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
56 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
57 : TargetLowering(TM) {
59 // Set up the register classes.
60 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
61 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
62 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
64 computeRegisterProperties();
67 std::vector<SDOperand>
68 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
69 MachineFunction &MF = DAG.getMachineFunction();
70 SSARegMap *RegMap = MF.getSSARegMap();
71 std::vector<SDOperand> ArgValues;
73 static const unsigned GPR[] = {
74 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
77 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
78 MVT::ValueType ObjectVT = getValueType(I->getType());
79 assert(ArgNo < 6 && "Only args in regs for now");
82 default: assert(0 && "Unhandled argument type!");
83 // TODO: MVT::i64 & FP
88 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
89 MF.addLiveIn(GPR[ArgNo++], VReg);
90 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
91 DAG.setRoot(Arg.getValue(1));
92 if (ObjectVT != MVT::i32) {
93 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
95 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
96 DAG.getValueType(ObjectVT));
97 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
99 ArgValues.push_back(Arg);
104 assert(!F.isVarArg() && "Unimp");
106 // Finally, inform the code generator which regs we return values in.
107 switch (getValueType(F.getReturnType())) {
108 default: assert(0 && "Unknown type!");
109 case MVT::isVoid: break;
114 MF.addLiveOut(V8::I0);
117 MF.addLiveOut(V8::I0);
118 MF.addLiveOut(V8::I1);
121 MF.addLiveOut(V8::F0);
124 MF.addLiveOut(V8::D0);
131 std::pair<SDOperand, SDOperand>
132 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
133 bool isVarArg, unsigned CC,
134 bool isTailCall, SDOperand Callee,
135 ArgListTy &Args, SelectionDAG &DAG) {
136 assert(0 && "Unimp");
140 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
142 if (Op.getValueType() == MVT::i64) {
143 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
144 DAG.getConstant(1, MVT::i32));
145 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
146 DAG.getConstant(0, MVT::i32));
147 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
149 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
153 SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
154 Value *VAListV, SelectionDAG &DAG) {
155 assert(0 && "Unimp");
159 std::pair<SDOperand,SDOperand>
160 SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
161 const Type *ArgTy, SelectionDAG &DAG) {
162 assert(0 && "Unimp");
166 std::pair<SDOperand, SDOperand>
167 SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
169 assert(0 && "Unimp");
173 //===----------------------------------------------------------------------===//
174 // Instruction Selector Implementation
175 //===----------------------------------------------------------------------===//
177 //===--------------------------------------------------------------------===//
178 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
179 /// instructions for SelectionDAG operations.
182 class SparcV8DAGToDAGISel : public SelectionDAGISel {
183 SparcV8TargetLowering V8Lowering;
185 SparcV8DAGToDAGISel(TargetMachine &TM)
186 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
188 SDOperand Select(SDOperand Op);
190 // Complex Pattern Selectors.
191 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
192 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
194 /// InstructionSelectBasicBlock - This callback is invoked by
195 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
196 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
198 virtual const char *getPassName() const {
199 return "PowerPC DAG->DAG Pattern Instruction Selection";
202 // Include the pieces autogenerated from the target description.
203 #include "SparcV8GenDAGISel.inc"
205 } // end anonymous namespace
207 /// InstructionSelectBasicBlock - This callback is invoked by
208 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
209 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
212 // Select target instructions for the DAG.
213 DAG.setRoot(Select(DAG.getRoot()));
215 DAG.RemoveDeadNodes();
217 // Emit machine code to BB.
218 ScheduleAndEmitDAG(DAG);
221 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand N, SDOperand &R1,
223 // FIXME: This should obviously be smarter.
225 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
229 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand N, SDOperand &Base,
231 // FIXME: This should obviously be smarter.
233 Offset = CurDAG->getTargetConstant(0, MVT::i32);
238 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
240 if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
241 N->getOpcode() < V8ISD::FIRST_NUMBER*/)
242 return Op; // Already selected.
243 // If this has already been converted, use it.
244 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
245 if (CGMI != CodeGenMap.end()) return CGMI->second;
247 switch (N->getOpcode()) {
250 if (N->getNumOperands() == 2) {
251 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
252 SDOperand Val = Select(N->getOperand(1));
253 if (N->getOperand(1).getValueType() == MVT::i32) {
254 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
255 } else if (N->getOperand(1).getValueType() == MVT::f32) {
256 Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
258 assert(N->getOperand(1).getValueType() == MVT::f64);
259 Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
261 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
262 } else if (N->getNumOperands() > 1) {
263 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
264 assert(N->getOperand(1).getValueType() == MVT::i32 &&
265 N->getOperand(2).getValueType() == MVT::i32 &&
266 N->getNumOperands() == 3 && "Unknown two-register ret value!");
267 Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(1)));
268 Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(2)));
269 return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
271 break; // Generated code handles the void case.
275 return SelectCode(Op);
279 /// createPPCISelDag - This pass converts a legalized DAG into a
280 /// PowerPC-specific DAG, ready for instruction scheduling.
282 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
283 return new SparcV8DAGToDAGISel(TM);