1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
32 //===----------------------------------------------------------------------===//
33 // TargetLowering Implementation
34 //===----------------------------------------------------------------------===//
38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
39 CMPICC, // Compare two GPR operands, set icc.
40 CMPFCC, // Compare two FP operands, set fcc.
41 BRICC, // Branch to dest on icc condition
42 BRFCC, // Branch to dest on fcc condition
43 SELECT_ICC, // Select between two values using the current ICC flags.
44 SELECT_FCC, // Select between two values using the current FCC flags.
46 Hi, Lo, // Hi/Lo operations, typically on a global address.
48 FTOI, // FP to Int within a FP register.
49 ITOF, // Int to FP within a FP register.
51 CALL, // A call instruction.
52 RET_FLAG // Return with a flag operand.
56 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
58 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
60 default: assert(0 && "Unknown integer condition code!");
61 case ISD::SETEQ: return SPCC::ICC_E;
62 case ISD::SETNE: return SPCC::ICC_NE;
63 case ISD::SETLT: return SPCC::ICC_L;
64 case ISD::SETGT: return SPCC::ICC_G;
65 case ISD::SETLE: return SPCC::ICC_LE;
66 case ISD::SETGE: return SPCC::ICC_GE;
67 case ISD::SETULT: return SPCC::ICC_CS;
68 case ISD::SETULE: return SPCC::ICC_LEU;
69 case ISD::SETUGT: return SPCC::ICC_GU;
70 case ISD::SETUGE: return SPCC::ICC_CC;
74 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
76 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
78 default: assert(0 && "Unknown fp condition code!");
80 case ISD::SETOEQ: return SPCC::FCC_E;
82 case ISD::SETUNE: return SPCC::FCC_NE;
84 case ISD::SETOLT: return SPCC::FCC_L;
86 case ISD::SETOGT: return SPCC::FCC_G;
88 case ISD::SETOLE: return SPCC::FCC_LE;
90 case ISD::SETOGE: return SPCC::FCC_GE;
91 case ISD::SETULT: return SPCC::FCC_UL;
92 case ISD::SETULE: return SPCC::FCC_ULE;
93 case ISD::SETUGT: return SPCC::FCC_UG;
94 case ISD::SETUGE: return SPCC::FCC_UGE;
95 case ISD::SETUO: return SPCC::FCC_U;
96 case ISD::SETO: return SPCC::FCC_O;
97 case ISD::SETONE: return SPCC::FCC_LG;
98 case ISD::SETUEQ: return SPCC::FCC_UE;
103 class SparcTargetLowering : public TargetLowering {
104 int VarArgsFrameOffset; // Frame offset to start of varargs area.
106 SparcTargetLowering(TargetMachine &TM);
107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
110 /// in Mask are known to be either zero or one and return them in the
111 /// KnownZero/KnownOne bitsets.
112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
116 const SelectionDAG &DAG,
117 unsigned Depth = 0) const;
119 virtual std::vector<SDOperand>
120 LowerArguments(Function &F, SelectionDAG &DAG);
121 virtual std::pair<SDOperand, SDOperand>
122 LowerCallTo(SDOperand Chain, const Type *RetTy,
123 bool RetSExt, bool RetZExt, bool isVarArg,
124 unsigned CC, bool isTailCall, SDOperand Callee,
125 ArgListTy &Args, SelectionDAG &DAG);
126 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
127 MachineBasicBlock *MBB);
129 virtual const char *getTargetNodeName(unsigned Opcode) const;
133 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
134 : TargetLowering(TM) {
136 // Set up the register classes.
137 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
138 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
139 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
141 // Turn FP extload into load/fextend
142 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
144 // Sparc doesn't have i1 sign extending load
145 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
147 // Custom legalize GlobalAddress nodes into LO/HI parts.
148 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
150 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
152 // Sparc doesn't have sext_inreg, replace them with shl/sra
153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
157 // Sparc has no REM or DIVREM operations.
158 setOperationAction(ISD::UREM, MVT::i32, Expand);
159 setOperationAction(ISD::SREM, MVT::i32, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
161 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
163 // Custom expand fp<->sint
164 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
165 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
168 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
169 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
171 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
172 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
174 // Sparc has no select or setcc: expand to SELECT_CC.
175 setOperationAction(ISD::SELECT, MVT::i32, Expand);
176 setOperationAction(ISD::SELECT, MVT::f32, Expand);
177 setOperationAction(ISD::SELECT, MVT::f64, Expand);
178 setOperationAction(ISD::SETCC, MVT::i32, Expand);
179 setOperationAction(ISD::SETCC, MVT::f32, Expand);
180 setOperationAction(ISD::SETCC, MVT::f64, Expand);
182 // Sparc doesn't have BRCOND either, it has BR_CC.
183 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
184 setOperationAction(ISD::BRIND, MVT::Other, Expand);
185 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
186 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
187 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
188 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
190 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
191 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
192 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
194 // SPARC has no intrinsics for these particular operations.
195 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
196 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
197 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
198 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
200 setOperationAction(ISD::FSIN , MVT::f64, Expand);
201 setOperationAction(ISD::FCOS , MVT::f64, Expand);
202 setOperationAction(ISD::FREM , MVT::f64, Expand);
203 setOperationAction(ISD::FSIN , MVT::f32, Expand);
204 setOperationAction(ISD::FCOS , MVT::f32, Expand);
205 setOperationAction(ISD::FREM , MVT::f32, Expand);
206 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
207 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
208 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
209 setOperationAction(ISD::ROTL , MVT::i32, Expand);
210 setOperationAction(ISD::ROTR , MVT::i32, Expand);
211 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
212 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
213 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
214 setOperationAction(ISD::FPOW , MVT::f64, Expand);
215 setOperationAction(ISD::FPOW , MVT::f32, Expand);
217 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
218 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
219 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
221 // We don't have line number support yet.
222 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
223 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
224 setOperationAction(ISD::LABEL, MVT::Other, Expand);
226 // RET must be custom lowered, to meet ABI requirements
227 setOperationAction(ISD::RET , MVT::Other, Custom);
229 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
230 setOperationAction(ISD::VASTART , MVT::Other, Custom);
231 // VAARG needs to be lowered to not do unaligned accesses for doubles.
232 setOperationAction(ISD::VAARG , MVT::Other, Custom);
234 // Use the default implementation.
235 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
236 setOperationAction(ISD::VAEND , MVT::Other, Expand);
237 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
238 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
239 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
241 setStackPointerRegisterToSaveRestore(SP::O6);
243 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
244 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
247 computeRegisterProperties();
250 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
253 case SPISD::CMPICC: return "SPISD::CMPICC";
254 case SPISD::CMPFCC: return "SPISD::CMPFCC";
255 case SPISD::BRICC: return "SPISD::BRICC";
256 case SPISD::BRFCC: return "SPISD::BRFCC";
257 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
258 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
259 case SPISD::Hi: return "SPISD::Hi";
260 case SPISD::Lo: return "SPISD::Lo";
261 case SPISD::FTOI: return "SPISD::FTOI";
262 case SPISD::ITOF: return "SPISD::ITOF";
263 case SPISD::CALL: return "SPISD::CALL";
264 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
268 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
269 /// be zero. Op is expected to be a target specific node. Used by DAG
271 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
275 const SelectionDAG &DAG,
276 unsigned Depth) const {
277 APInt KnownZero2, KnownOne2;
278 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
280 switch (Op.getOpcode()) {
282 case SPISD::SELECT_ICC:
283 case SPISD::SELECT_FCC:
284 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
286 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
288 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
289 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
291 // Only known if known in both the LHS and RHS.
292 KnownOne &= KnownOne2;
293 KnownZero &= KnownZero2;
298 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
299 /// either one or two GPRs, including FP values. TODO: we should pass FP values
300 /// in FP registers for fastcc functions.
301 std::vector<SDOperand>
302 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
303 MachineFunction &MF = DAG.getMachineFunction();
304 MachineRegisterInfo &RegInfo = MF.getRegInfo();
305 std::vector<SDOperand> ArgValues;
307 static const unsigned ArgRegs[] = {
308 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
311 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
312 unsigned ArgOffset = 68;
314 SDOperand Root = DAG.getRoot();
315 std::vector<SDOperand> OutChains;
317 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
318 MVT::ValueType ObjectVT = getValueType(I->getType());
321 default: assert(0 && "Unhandled argument type!");
326 if (I->use_empty()) { // Argument is dead.
327 if (CurArgReg < ArgRegEnd) ++CurArgReg;
328 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
329 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
330 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
331 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
332 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
333 if (ObjectVT != MVT::i32) {
334 unsigned AssertOp = ISD::AssertSext;
335 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
336 DAG.getValueType(ObjectVT));
337 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
339 ArgValues.push_back(Arg);
341 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
342 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
344 if (ObjectVT == MVT::i32) {
345 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
347 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
349 // Sparc is big endian, so add an offset based on the ObjectVT.
350 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
351 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
352 DAG.getConstant(Offset, MVT::i32));
353 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
355 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
357 ArgValues.push_back(Load);
363 if (I->use_empty()) { // Argument is dead.
364 if (CurArgReg < ArgRegEnd) ++CurArgReg;
365 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
366 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
367 // FP value is passed in an integer register.
368 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
369 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
370 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
372 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
373 ArgValues.push_back(Arg);
375 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
376 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
377 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
378 ArgValues.push_back(Load);
385 if (I->use_empty()) { // Argument is dead.
386 if (CurArgReg < ArgRegEnd) ++CurArgReg;
387 if (CurArgReg < ArgRegEnd) ++CurArgReg;
388 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
389 } else if (/* FIXME: Apparently this isn't safe?? */
390 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
391 ((CurArgReg-ArgRegs) & 1) == 0) {
392 // If this is a double argument and the whole thing lives on the stack,
393 // and the argument is aligned, load the double straight from the stack.
394 // We can't do a load in cases like void foo([6ints], int,double),
395 // because the double wouldn't be aligned!
396 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
397 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
398 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
401 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
402 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
403 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
404 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
406 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
407 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
408 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
412 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
413 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
414 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
415 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
417 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
418 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
419 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
422 // Compose the two halves together into an i64 unit.
423 SDOperand WholeValue =
424 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
426 // If we want a double, do a bit convert.
427 if (ObjectVT == MVT::f64)
428 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
430 ArgValues.push_back(WholeValue);
437 // Store remaining ArgRegs to the stack if this is a varargs function.
438 if (F.getFunctionType()->isVarArg()) {
439 // Remember the vararg offset for the va_start implementation.
440 VarArgsFrameOffset = ArgOffset;
442 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
443 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
444 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
445 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
447 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
448 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
450 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
455 if (!OutChains.empty())
456 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
457 &OutChains[0], OutChains.size()));
459 // Finally, inform the code generator which regs we return values in.
460 switch (getValueType(F.getReturnType())) {
461 default: assert(0 && "Unknown type!");
462 case MVT::isVoid: break;
467 MF.getRegInfo().addLiveOut(SP::I0);
470 MF.getRegInfo().addLiveOut(SP::I0);
471 MF.getRegInfo().addLiveOut(SP::I1);
474 MF.getRegInfo().addLiveOut(SP::F0);
477 MF.getRegInfo().addLiveOut(SP::D0);
484 std::pair<SDOperand, SDOperand>
485 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
486 bool RetSExt, bool RetZExt, bool isVarArg,
487 unsigned CC, bool isTailCall, SDOperand Callee,
488 ArgListTy &Args, SelectionDAG &DAG) {
489 // Count the size of the outgoing arguments.
490 unsigned ArgsSize = 0;
491 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
492 switch (getValueType(Args[i].Ty)) {
493 default: assert(0 && "Unknown value type!");
508 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
512 // Keep stack frames 8-byte aligned.
513 ArgsSize = (ArgsSize+7) & ~7;
515 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
518 std::vector<SDOperand> Stores;
519 std::vector<SDOperand> RegValuesToPass;
520 unsigned ArgOffset = 68;
521 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
522 SDOperand Val = Args[i].Node;
523 MVT::ValueType ObjectVT = Val.getValueType();
524 SDOperand ValToStore(0, 0);
527 default: assert(0 && "Unhandled argument type!");
531 // Promote the integer to 32-bits. If the input type is signed, use a
532 // sign extend, otherwise use a zero extend.
533 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
535 ExtendKind = ISD::SIGN_EXTEND;
536 else if (Args[i].isZExt)
537 ExtendKind = ISD::ZERO_EXTEND;
538 Val = DAG.getNode(ExtendKind, MVT::i32, Val);
544 if (RegValuesToPass.size() >= 6) {
547 RegValuesToPass.push_back(Val);
552 if (RegValuesToPass.size() >= 6) {
555 // Convert this to a FP value in an int reg.
556 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
557 RegValuesToPass.push_back(Val);
562 // If we can store this directly into the outgoing slot, do so. We can
563 // do this when all ArgRegs are used and if the outgoing slot is aligned.
564 // FIXME: McGill/misr fails with this.
565 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
570 // Otherwise, convert this to a FP value in int regs.
571 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
575 if (RegValuesToPass.size() >= 6) {
576 ValToStore = Val; // Whole thing is passed in memory.
580 // Split the value into top and bottom part. Top part goes in a reg.
581 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
582 DAG.getConstant(1, MVT::i32));
583 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
584 DAG.getConstant(0, MVT::i32));
585 RegValuesToPass.push_back(Hi);
587 if (RegValuesToPass.size() >= 6) {
592 RegValuesToPass.push_back(Lo);
597 if (ValToStore.Val) {
599 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
601 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
602 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
603 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
605 ArgOffset += ObjSize;
608 // Emit all stores, make sure the occur before any copies into physregs.
610 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
612 static const unsigned ArgRegs[] = {
613 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
616 // Build a sequence of copy-to-reg nodes chained together with token chain
617 // and flag operands which copy the outgoing args into O[0-5].
619 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
620 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
621 InFlag = Chain.getValue(1);
624 // If the callee is a GlobalAddress node (quite common, every direct call is)
625 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
626 // Likewise ExternalSymbol -> TargetExternalSymbol.
627 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
628 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
629 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
630 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
632 std::vector<MVT::ValueType> NodeTys;
633 NodeTys.push_back(MVT::Other); // Returns a chain
634 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
635 SDOperand Ops[] = { Chain, Callee, InFlag };
636 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
637 InFlag = Chain.getValue(1);
639 MVT::ValueType RetTyVT = getValueType(RetTy);
641 if (RetTyVT != MVT::isVoid) {
643 default: assert(0 && "Unknown value type to return!");
647 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
648 Chain = RetVal.getValue(1);
650 // Add a note to keep track of whether it is sign or zero extended.
651 ISD::NodeType AssertKind = ISD::DELETED_NODE;
653 AssertKind = ISD::AssertSext;
655 AssertKind = ISD::AssertZext;
657 if (AssertKind != ISD::DELETED_NODE)
658 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
659 DAG.getValueType(RetTyVT));
661 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
665 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
666 Chain = RetVal.getValue(1);
669 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
670 Chain = RetVal.getValue(1);
673 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
674 Chain = RetVal.getValue(1);
677 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
678 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
680 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
681 Chain = Hi.getValue(1);
686 Chain = DAG.getCALLSEQ_END(Chain,
687 DAG.getConstant(ArgsSize, getPointerTy()),
688 DAG.getConstant(0, getPointerTy()),
690 return std::make_pair(RetVal, Chain);
693 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
694 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
695 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
696 ISD::CondCode CC, unsigned &SPCC) {
697 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
699 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
700 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
701 (LHS.getOpcode() == SPISD::SELECT_FCC &&
702 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
703 isa<ConstantSDNode>(LHS.getOperand(0)) &&
704 isa<ConstantSDNode>(LHS.getOperand(1)) &&
705 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
706 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
707 SDOperand CMPCC = LHS.getOperand(3);
708 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
709 LHS = CMPCC.getOperand(0);
710 RHS = CMPCC.getOperand(1);
715 SDOperand SparcTargetLowering::
716 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
717 switch (Op.getOpcode()) {
718 default: assert(0 && "Should not custom lower this!");
719 case ISD::GlobalTLSAddress:
720 assert(0 && "TLS not implemented for Sparc.");
721 case ISD::GlobalAddress: {
722 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
723 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
724 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
725 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
726 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
728 case ISD::ConstantPool: {
729 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
730 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
731 cast<ConstantPoolSDNode>(Op)->getAlignment());
732 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
733 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
734 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
736 case ISD::FP_TO_SINT:
737 // Convert the fp value to integer in an FP register.
738 assert(Op.getValueType() == MVT::i32);
739 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
740 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
741 case ISD::SINT_TO_FP: {
742 assert(Op.getOperand(0).getValueType() == MVT::i32);
743 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
744 // Convert the int value to FP in an FP register.
745 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
748 SDOperand Chain = Op.getOperand(0);
749 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
750 SDOperand LHS = Op.getOperand(2);
751 SDOperand RHS = Op.getOperand(3);
752 SDOperand Dest = Op.getOperand(4);
753 unsigned Opc, SPCC = ~0U;
755 // If this is a br_cc of a "setcc", and if the setcc got lowered into
756 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
757 LookThroughSetCC(LHS, RHS, CC, SPCC);
759 // Get the condition flag.
760 SDOperand CompareFlag;
761 if (LHS.getValueType() == MVT::i32) {
762 std::vector<MVT::ValueType> VTs;
763 VTs.push_back(MVT::i32);
764 VTs.push_back(MVT::Flag);
765 SDOperand Ops[2] = { LHS, RHS };
766 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
767 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
770 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
771 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
774 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
775 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
777 case ISD::SELECT_CC: {
778 SDOperand LHS = Op.getOperand(0);
779 SDOperand RHS = Op.getOperand(1);
780 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
781 SDOperand TrueVal = Op.getOperand(2);
782 SDOperand FalseVal = Op.getOperand(3);
783 unsigned Opc, SPCC = ~0U;
785 // If this is a select_cc of a "setcc", and if the setcc got lowered into
786 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
787 LookThroughSetCC(LHS, RHS, CC, SPCC);
789 SDOperand CompareFlag;
790 if (LHS.getValueType() == MVT::i32) {
791 std::vector<MVT::ValueType> VTs;
792 VTs.push_back(LHS.getValueType()); // subcc returns a value
793 VTs.push_back(MVT::Flag);
794 SDOperand Ops[2] = { LHS, RHS };
795 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
796 Opc = SPISD::SELECT_ICC;
797 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
799 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
800 Opc = SPISD::SELECT_FCC;
801 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
803 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
804 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
807 // vastart just stores the address of the VarArgsFrameIndex slot into the
808 // memory location argument.
809 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
810 DAG.getRegister(SP::I6, MVT::i32),
811 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
812 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
813 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
816 SDNode *Node = Op.Val;
817 MVT::ValueType VT = Node->getValueType(0);
818 SDOperand InChain = Node->getOperand(0);
819 SDOperand VAListPtr = Node->getOperand(1);
820 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
821 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0);
822 // Increment the pointer, VAList, to the next vaarg
823 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
824 DAG.getConstant(MVT::getSizeInBits(VT)/8,
826 // Store the incremented VAList to the legalized pointer
827 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
829 // Load the actual argument out of the pointer VAList, unless this is an
831 if (VT != MVT::f64) {
832 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
834 // Otherwise, load it as i64, then do a bitconvert.
835 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
836 std::vector<MVT::ValueType> Tys;
837 Tys.push_back(MVT::f64);
838 Tys.push_back(MVT::Other);
839 // Bit-Convert the value to f64.
840 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
842 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
845 case ISD::DYNAMIC_STACKALLOC: {
846 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
847 SDOperand Size = Op.getOperand(1); // Legalize the size.
849 unsigned SPReg = SP::O6;
850 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
851 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
852 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
854 // The resultant pointer is actually 16 words from the bottom of the stack,
855 // to provide a register spill area.
856 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
857 DAG.getConstant(96, MVT::i32));
858 std::vector<MVT::ValueType> Tys;
859 Tys.push_back(MVT::i32);
860 Tys.push_back(MVT::Other);
861 SDOperand Ops[2] = { NewVal, Chain };
862 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
867 switch(Op.getNumOperands()) {
869 assert(0 && "Do not know how to return this many arguments!");
872 return SDOperand(); // ret void is legal
875 switch(Op.getOperand(1).getValueType()) {
876 default: assert(0 && "Unknown type to return!");
877 case MVT::i32: ArgReg = SP::I0; break;
878 case MVT::f32: ArgReg = SP::F0; break;
879 case MVT::f64: ArgReg = SP::D0; break;
881 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
886 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
888 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
891 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
893 // Frame & Return address. Currently unimplemented
894 case ISD::RETURNADDR: break;
895 case ISD::FRAMEADDR: break;
901 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
902 MachineBasicBlock *BB) {
903 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
906 // Figure out the conditional branch opcode to use for this select_cc.
907 switch (MI->getOpcode()) {
908 default: assert(0 && "Unknown SELECT_CC!");
909 case SP::SELECT_CC_Int_ICC:
910 case SP::SELECT_CC_FP_ICC:
911 case SP::SELECT_CC_DFP_ICC:
912 BROpcode = SP::BCOND;
914 case SP::SELECT_CC_Int_FCC:
915 case SP::SELECT_CC_FP_FCC:
916 case SP::SELECT_CC_DFP_FCC:
917 BROpcode = SP::FBCOND;
921 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
923 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
924 // control-flow pattern. The incoming instruction knows the destination vreg
925 // to set, the condition code register to branch on, the true/false values to
926 // select between, and a branch opcode to use.
927 const BasicBlock *LLVM_BB = BB->getBasicBlock();
928 ilist<MachineBasicBlock>::iterator It = BB;
935 // fallthrough --> copy0MBB
936 MachineBasicBlock *thisMBB = BB;
937 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
938 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
939 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
940 MachineFunction *F = BB->getParent();
941 F->getBasicBlockList().insert(It, copy0MBB);
942 F->getBasicBlockList().insert(It, sinkMBB);
943 // Update machine-CFG edges by first adding all successors of the current
944 // block to the new block which will contain the Phi node for the select.
945 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
946 e = BB->succ_end(); i != e; ++i)
947 sinkMBB->addSuccessor(*i);
948 // Next, remove all successors of the current block, and add the true
949 // and fallthrough blocks as its successors.
950 while(!BB->succ_empty())
951 BB->removeSuccessor(BB->succ_begin());
952 BB->addSuccessor(copy0MBB);
953 BB->addSuccessor(sinkMBB);
957 // # fallthrough to sinkMBB
960 // Update machine-CFG edges
961 BB->addSuccessor(sinkMBB);
964 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
967 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
968 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
969 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
971 delete MI; // The pseudo instruction is gone now.
975 //===----------------------------------------------------------------------===//
976 // Instruction Selector Implementation
977 //===----------------------------------------------------------------------===//
979 //===--------------------------------------------------------------------===//
980 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
981 /// instructions for SelectionDAG operations.
984 class SparcDAGToDAGISel : public SelectionDAGISel {
985 SparcTargetLowering Lowering;
987 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
988 /// make the right decision when generating code for different targets.
989 const SparcSubtarget &Subtarget;
991 SparcDAGToDAGISel(TargetMachine &TM)
992 : SelectionDAGISel(Lowering), Lowering(TM),
993 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
996 SDNode *Select(SDOperand Op);
998 // Complex Pattern Selectors.
999 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
1000 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
1003 /// InstructionSelectBasicBlock - This callback is invoked by
1004 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1005 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
1007 virtual const char *getPassName() const {
1008 return "SPARC DAG->DAG Pattern Instruction Selection";
1011 // Include the pieces autogenerated from the target description.
1012 #include "SparcGenDAGISel.inc"
1014 } // end anonymous namespace
1016 /// InstructionSelectBasicBlock - This callback is invoked by
1017 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1018 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1021 // Select target instructions for the DAG.
1022 DAG.setRoot(SelectRoot(DAG.getRoot()));
1023 DAG.RemoveDeadNodes();
1025 // Emit machine code to BB.
1026 ScheduleAndEmitDAG(DAG);
1029 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1030 SDOperand &Base, SDOperand &Offset) {
1031 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1032 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1033 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1036 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1037 Addr.getOpcode() == ISD::TargetGlobalAddress)
1038 return false; // direct calls.
1040 if (Addr.getOpcode() == ISD::ADD) {
1041 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1042 if (Predicate_simm13(CN)) {
1043 if (FrameIndexSDNode *FIN =
1044 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1045 // Constant offset from frame ref.
1046 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1048 Base = Addr.getOperand(0);
1050 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1054 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1055 Base = Addr.getOperand(1);
1056 Offset = Addr.getOperand(0).getOperand(0);
1059 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1060 Base = Addr.getOperand(0);
1061 Offset = Addr.getOperand(1).getOperand(0);
1066 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1070 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1071 SDOperand &R1, SDOperand &R2) {
1072 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1073 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1074 Addr.getOpcode() == ISD::TargetGlobalAddress)
1075 return false; // direct calls.
1077 if (Addr.getOpcode() == ISD::ADD) {
1078 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1079 Predicate_simm13(Addr.getOperand(1).Val))
1080 return false; // Let the reg+imm pattern catch this!
1081 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1082 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1083 return false; // Let the reg+imm pattern catch this!
1084 R1 = Addr.getOperand(0);
1085 R2 = Addr.getOperand(1);
1090 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1094 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1096 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1097 N->getOpcode() < SPISD::FIRST_NUMBER)
1098 return NULL; // Already selected.
1100 switch (N->getOpcode()) {
1104 // FIXME: should use a custom expander to expose the SRA to the dag.
1105 SDOperand DivLHS = N->getOperand(0);
1106 SDOperand DivRHS = N->getOperand(1);
1107 AddToISelQueue(DivLHS);
1108 AddToISelQueue(DivRHS);
1110 // Set the Y register to the high-part.
1112 if (N->getOpcode() == ISD::SDIV) {
1113 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1114 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1116 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1118 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1119 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1121 // FIXME: Handle div by immediate.
1122 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1123 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1128 // FIXME: Handle mul by immediate.
1129 SDOperand MulLHS = N->getOperand(0);
1130 SDOperand MulRHS = N->getOperand(1);
1131 AddToISelQueue(MulLHS);
1132 AddToISelQueue(MulRHS);
1133 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1134 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1136 // The high part is in the Y register.
1137 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1142 return SelectCode(Op);
1146 /// createSparcISelDag - This pass converts a legalized DAG into a
1147 /// SPARC-specific DAG, ready for instruction scheduling.
1149 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1150 return new SparcDAGToDAGISel(TM);