1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcTargetMachine.h"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/IR/Intrinsics.h"
17 #include "llvm/Support/Compiler.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
23 //===----------------------------------------------------------------------===//
24 // Instruction Selector Implementation
25 //===----------------------------------------------------------------------===//
27 //===--------------------------------------------------------------------===//
28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29 /// instructions for SelectionDAG operations.
32 class SparcDAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const SparcSubtarget *Subtarget;
37 explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
39 bool runOnMachineFunction(MachineFunction &MF) override {
40 Subtarget = &MF.getSubtarget<SparcSubtarget>();
41 return SelectionDAGISel::runOnMachineFunction(MF);
44 SDNode *Select(SDNode *N) override;
46 // Complex Pattern Selectors.
47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
50 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
51 /// inline asm expressions.
52 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
53 unsigned ConstraintID,
54 std::vector<SDValue> &OutOps) override;
56 const char *getPassName() const override {
57 return "SPARC DAG->DAG Pattern Instruction Selection";
60 // Include the pieces autogenerated from the target description.
61 #include "SparcGenDAGISel.inc"
64 SDNode* getGlobalBaseReg();
66 } // end anonymous namespace
68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
69 unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
70 return CurDAG->getRegister(GlobalBaseReg,
71 TLI->getPointerTy(CurDAG->getDataLayout()))
75 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
76 SDValue &Base, SDValue &Offset) {
77 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
78 Base = CurDAG->getTargetFrameIndex(
79 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
80 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
83 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
84 Addr.getOpcode() == ISD::TargetGlobalAddress ||
85 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
86 return false; // direct calls.
88 if (Addr.getOpcode() == ISD::ADD) {
89 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
90 if (isInt<13>(CN->getSExtValue())) {
91 if (FrameIndexSDNode *FIN =
92 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
93 // Constant offset from frame ref.
94 Base = CurDAG->getTargetFrameIndex(
95 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
97 Base = Addr.getOperand(0);
99 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
105 Base = Addr.getOperand(1);
106 Offset = Addr.getOperand(0).getOperand(0);
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
110 Base = Addr.getOperand(0);
111 Offset = Addr.getOperand(1).getOperand(0);
116 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
120 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
121 if (Addr.getOpcode() == ISD::FrameIndex) return false;
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
123 Addr.getOpcode() == ISD::TargetGlobalAddress ||
124 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
125 return false; // direct calls.
127 if (Addr.getOpcode() == ISD::ADD) {
128 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
129 if (isInt<13>(CN->getSExtValue()))
130 return false; // Let the reg+imm pattern catch this!
131 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
132 Addr.getOperand(1).getOpcode() == SPISD::Lo)
133 return false; // Let the reg+imm pattern catch this!
134 R1 = Addr.getOperand(0);
135 R2 = Addr.getOperand(1);
140 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
144 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
146 if (N->isMachineOpcode()) {
148 return nullptr; // Already selected.
151 switch (N->getOpcode()) {
153 case SPISD::GLOBAL_BASE_REG:
154 return getGlobalBaseReg();
158 // sdivx / udivx handle 64-bit divides.
159 if (N->getValueType(0) == MVT::i64)
161 // FIXME: should use a custom expander to expose the SRA to the dag.
162 SDValue DivLHS = N->getOperand(0);
163 SDValue DivRHS = N->getOperand(1);
165 // Set the Y register to the high-part.
167 if (N->getOpcode() == ISD::SDIV) {
168 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
169 CurDAG->getTargetConstant(31, dl, MVT::i32)),
172 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
174 TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,
178 // FIXME: Handle div by immediate.
179 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
180 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
185 // FIXME: Handle mul by immediate.
186 SDValue MulLHS = N->getOperand(0);
187 SDValue MulRHS = N->getOperand(1);
188 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
190 CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MulLHS, MulRHS);
191 SDValue ResultHigh = SDValue(Mul, 1);
192 ReplaceUses(SDValue(N, 0), ResultHigh);
197 return SelectCode(N);
201 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
202 /// inline asm expressions.
204 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
205 unsigned ConstraintID,
206 std::vector<SDValue> &OutOps) {
208 switch (ConstraintID) {
209 default: return true;
210 case InlineAsm::Constraint_i:
211 case InlineAsm::Constraint_m: // memory
212 if (!SelectADDRrr(Op, Op0, Op1))
213 SelectADDRri(Op, Op0, Op1);
217 OutOps.push_back(Op0);
218 OutOps.push_back(Op1);
222 /// createSparcISelDag - This pass converts a legalized DAG into a
223 /// SPARC-specific DAG, ready for instruction scheduling.
225 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
226 return new SparcDAGToDAGISel(TM);