1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
31 //===----------------------------------------------------------------------===//
32 // TargetLowering Implementation
33 //===----------------------------------------------------------------------===//
37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
38 CMPICC, // Compare two GPR operands, set icc.
39 CMPFCC, // Compare two FP operands, set fcc.
40 BRICC, // Branch to dest on icc condition
41 BRFCC, // Branch to dest on fcc condition
42 SELECT_ICC, // Select between two values using the current ICC flags.
43 SELECT_FCC, // Select between two values using the current FCC flags.
45 Hi, Lo, // Hi/Lo operations, typically on a global address.
47 FTOI, // FP to Int within a FP register.
48 ITOF, // Int to FP within a FP register.
50 CALL, // A call instruction.
51 RET_FLAG // Return with a flag operand.
55 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
57 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
59 default: assert(0 && "Unknown integer condition code!");
60 case ISD::SETEQ: return SPCC::ICC_E;
61 case ISD::SETNE: return SPCC::ICC_NE;
62 case ISD::SETLT: return SPCC::ICC_L;
63 case ISD::SETGT: return SPCC::ICC_G;
64 case ISD::SETLE: return SPCC::ICC_LE;
65 case ISD::SETGE: return SPCC::ICC_GE;
66 case ISD::SETULT: return SPCC::ICC_CS;
67 case ISD::SETULE: return SPCC::ICC_LEU;
68 case ISD::SETUGT: return SPCC::ICC_GU;
69 case ISD::SETUGE: return SPCC::ICC_CC;
73 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
75 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
77 default: assert(0 && "Unknown fp condition code!");
79 case ISD::SETOEQ: return SPCC::FCC_E;
81 case ISD::SETUNE: return SPCC::FCC_NE;
83 case ISD::SETOLT: return SPCC::FCC_L;
85 case ISD::SETOGT: return SPCC::FCC_G;
87 case ISD::SETOLE: return SPCC::FCC_LE;
89 case ISD::SETOGE: return SPCC::FCC_GE;
90 case ISD::SETULT: return SPCC::FCC_UL;
91 case ISD::SETULE: return SPCC::FCC_ULE;
92 case ISD::SETUGT: return SPCC::FCC_UG;
93 case ISD::SETUGE: return SPCC::FCC_UGE;
94 case ISD::SETUO: return SPCC::FCC_U;
95 case ISD::SETO: return SPCC::FCC_O;
96 case ISD::SETONE: return SPCC::FCC_LG;
97 case ISD::SETUEQ: return SPCC::FCC_UE;
102 class SparcTargetLowering : public TargetLowering {
103 int VarArgsFrameOffset; // Frame offset to start of varargs area.
105 SparcTargetLowering(TargetMachine &TM);
106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
109 /// in Mask are known to be either zero or one and return them in the
110 /// KnownZero/KnownOne bitsets.
111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
115 unsigned Depth = 0) const;
117 virtual std::vector<SDOperand>
118 LowerArguments(Function &F, SelectionDAG &DAG);
119 virtual std::pair<SDOperand, SDOperand>
120 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
122 bool isTailCall, SDOperand Callee, ArgListTy &Args,
124 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
125 MachineBasicBlock *MBB);
127 virtual const char *getTargetNodeName(unsigned Opcode) const;
131 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
132 : TargetLowering(TM) {
134 // Set up the register classes.
135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
139 // Turn FP extload into load/fextend
140 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
142 // Custom legalize GlobalAddress nodes into LO/HI parts.
143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
144 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
146 // Sparc doesn't have sext_inreg, replace them with shl/sra
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
151 // Sparc has no REM operation.
152 setOperationAction(ISD::UREM, MVT::i32, Expand);
153 setOperationAction(ISD::SREM, MVT::i32, Expand);
155 // Custom expand fp<->sint
156 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
157 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
160 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
161 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
163 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
164 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
166 // Sparc has no select or setcc: expand to SELECT_CC.
167 setOperationAction(ISD::SELECT, MVT::i32, Expand);
168 setOperationAction(ISD::SELECT, MVT::f32, Expand);
169 setOperationAction(ISD::SELECT, MVT::f64, Expand);
170 setOperationAction(ISD::SETCC, MVT::i32, Expand);
171 setOperationAction(ISD::SETCC, MVT::f32, Expand);
172 setOperationAction(ISD::SETCC, MVT::f64, Expand);
174 // Sparc doesn't have BRCOND either, it has BR_CC.
175 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
176 setOperationAction(ISD::BRIND, MVT::Other, Expand);
177 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
178 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
180 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
182 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
183 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
184 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
186 // SPARC has no intrinsics for these particular operations.
187 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
188 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
189 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
191 setOperationAction(ISD::FSIN , MVT::f64, Expand);
192 setOperationAction(ISD::FCOS , MVT::f64, Expand);
193 setOperationAction(ISD::FSIN , MVT::f32, Expand);
194 setOperationAction(ISD::FCOS , MVT::f32, Expand);
195 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
196 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
197 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
198 setOperationAction(ISD::ROTL , MVT::i32, Expand);
199 setOperationAction(ISD::ROTR , MVT::i32, Expand);
200 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
201 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
202 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
204 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
205 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
206 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
208 // We don't have line number support yet.
209 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
210 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
211 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
213 // RET must be custom lowered, to meet ABI requirements
214 setOperationAction(ISD::RET , MVT::Other, Custom);
216 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
217 setOperationAction(ISD::VASTART , MVT::Other, Custom);
218 // VAARG needs to be lowered to not do unaligned accesses for doubles.
219 setOperationAction(ISD::VAARG , MVT::Other, Custom);
221 // Use the default implementation.
222 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
223 setOperationAction(ISD::VAEND , MVT::Other, Expand);
224 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
225 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
228 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
229 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
231 setStackPointerRegisterToSaveRestore(SP::O6);
233 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
234 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
237 computeRegisterProperties();
240 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
243 case SPISD::CMPICC: return "SPISD::CMPICC";
244 case SPISD::CMPFCC: return "SPISD::CMPFCC";
245 case SPISD::BRICC: return "SPISD::BRICC";
246 case SPISD::BRFCC: return "SPISD::BRFCC";
247 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
248 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
249 case SPISD::Hi: return "SPISD::Hi";
250 case SPISD::Lo: return "SPISD::Lo";
251 case SPISD::FTOI: return "SPISD::FTOI";
252 case SPISD::ITOF: return "SPISD::ITOF";
253 case SPISD::CALL: return "SPISD::CALL";
254 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
258 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
259 /// be zero. Op is expected to be a target specific node. Used by DAG
261 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
265 unsigned Depth) const {
266 uint64_t KnownZero2, KnownOne2;
267 KnownZero = KnownOne = 0; // Don't know anything.
269 switch (Op.getOpcode()) {
271 case SPISD::SELECT_ICC:
272 case SPISD::SELECT_FCC:
273 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
274 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
275 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
276 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
278 // Only known if known in both the LHS and RHS.
279 KnownOne &= KnownOne2;
280 KnownZero &= KnownZero2;
285 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
286 /// either one or two GPRs, including FP values. TODO: we should pass FP values
287 /// in FP registers for fastcc functions.
288 std::vector<SDOperand>
289 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
290 MachineFunction &MF = DAG.getMachineFunction();
291 SSARegMap *RegMap = MF.getSSARegMap();
292 std::vector<SDOperand> ArgValues;
294 static const unsigned ArgRegs[] = {
295 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
298 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
299 unsigned ArgOffset = 68;
301 SDOperand Root = DAG.getRoot();
302 std::vector<SDOperand> OutChains;
304 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
305 MVT::ValueType ObjectVT = getValueType(I->getType());
308 default: assert(0 && "Unhandled argument type!");
313 if (I->use_empty()) { // Argument is dead.
314 if (CurArgReg < ArgRegEnd) ++CurArgReg;
315 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
316 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
317 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
318 MF.addLiveIn(*CurArgReg++, VReg);
319 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
320 if (ObjectVT != MVT::i32) {
321 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
323 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
324 DAG.getValueType(ObjectVT));
325 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
327 ArgValues.push_back(Arg);
329 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
330 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
332 if (ObjectVT == MVT::i32) {
333 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
335 ISD::LoadExtType LoadOp =
336 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
338 // Sparc is big endian, so add an offset based on the ObjectVT.
339 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
340 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
341 DAG.getConstant(Offset, MVT::i32));
342 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
344 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
346 ArgValues.push_back(Load);
352 if (I->use_empty()) { // Argument is dead.
353 if (CurArgReg < ArgRegEnd) ++CurArgReg;
354 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
355 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
356 // FP value is passed in an integer register.
357 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
358 MF.addLiveIn(*CurArgReg++, VReg);
359 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
361 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
362 ArgValues.push_back(Arg);
364 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
365 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
366 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
367 ArgValues.push_back(Load);
374 if (I->use_empty()) { // Argument is dead.
375 if (CurArgReg < ArgRegEnd) ++CurArgReg;
376 if (CurArgReg < ArgRegEnd) ++CurArgReg;
377 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
378 } else if (/* FIXME: Apparently this isn't safe?? */
379 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
380 ((CurArgReg-ArgRegs) & 1) == 0) {
381 // If this is a double argument and the whole thing lives on the stack,
382 // and the argument is aligned, load the double straight from the stack.
383 // We can't do a load in cases like void foo([6ints], int,double),
384 // because the double wouldn't be aligned!
385 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
386 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
387 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
390 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
391 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
392 MF.addLiveIn(*CurArgReg++, VRegHi);
393 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
395 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
396 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
397 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
401 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
402 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
403 MF.addLiveIn(*CurArgReg++, VRegLo);
404 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
406 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
407 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
408 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
411 // Compose the two halves together into an i64 unit.
412 SDOperand WholeValue =
413 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
415 // If we want a double, do a bit convert.
416 if (ObjectVT == MVT::f64)
417 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
419 ArgValues.push_back(WholeValue);
426 // Store remaining ArgRegs to the stack if this is a varargs function.
427 if (F.getFunctionType()->isVarArg()) {
428 // Remember the vararg offset for the va_start implementation.
429 VarArgsFrameOffset = ArgOffset;
431 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
432 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
433 MF.addLiveIn(*CurArgReg, VReg);
434 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
436 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
437 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
439 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
444 if (!OutChains.empty())
445 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
446 &OutChains[0], OutChains.size()));
448 // Finally, inform the code generator which regs we return values in.
449 switch (getValueType(F.getReturnType())) {
450 default: assert(0 && "Unknown type!");
451 case MVT::isVoid: break;
456 MF.addLiveOut(SP::I0);
459 MF.addLiveOut(SP::I0);
460 MF.addLiveOut(SP::I1);
463 MF.addLiveOut(SP::F0);
466 MF.addLiveOut(SP::D0);
473 std::pair<SDOperand, SDOperand>
474 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
475 bool isVarArg, unsigned CC,
476 bool isTailCall, SDOperand Callee,
477 ArgListTy &Args, SelectionDAG &DAG) {
478 // Count the size of the outgoing arguments.
479 unsigned ArgsSize = 0;
480 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
481 switch (getValueType(Args[i].second)) {
482 default: assert(0 && "Unknown value type!");
497 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
501 // Keep stack frames 8-byte aligned.
502 ArgsSize = (ArgsSize+7) & ~7;
504 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
507 std::vector<SDOperand> Stores;
508 std::vector<SDOperand> RegValuesToPass;
509 unsigned ArgOffset = 68;
510 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
511 SDOperand Val = Args[i].first;
512 MVT::ValueType ObjectVT = Val.getValueType();
513 SDOperand ValToStore(0, 0);
516 default: assert(0 && "Unhandled argument type!");
520 // Promote the integer to 32-bits. If the input type is signed, use a
521 // sign extend, otherwise use a zero extend.
522 if (Args[i].second->isSigned())
523 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
525 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
530 if (RegValuesToPass.size() >= 6) {
533 RegValuesToPass.push_back(Val);
538 if (RegValuesToPass.size() >= 6) {
541 // Convert this to a FP value in an int reg.
542 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
543 RegValuesToPass.push_back(Val);
548 // If we can store this directly into the outgoing slot, do so. We can
549 // do this when all ArgRegs are used and if the outgoing slot is aligned.
550 // FIXME: McGill/misr fails with this.
551 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
556 // Otherwise, convert this to a FP value in int regs.
557 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
561 if (RegValuesToPass.size() >= 6) {
562 ValToStore = Val; // Whole thing is passed in memory.
566 // Split the value into top and bottom part. Top part goes in a reg.
567 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
568 DAG.getConstant(1, MVT::i32));
569 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
570 DAG.getConstant(0, MVT::i32));
571 RegValuesToPass.push_back(Hi);
573 if (RegValuesToPass.size() >= 6) {
578 RegValuesToPass.push_back(Lo);
583 if (ValToStore.Val) {
585 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
587 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
588 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
589 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
591 ArgOffset += ObjSize;
594 // Emit all stores, make sure the occur before any copies into physregs.
596 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
598 static const unsigned ArgRegs[] = {
599 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
602 // Build a sequence of copy-to-reg nodes chained together with token chain
603 // and flag operands which copy the outgoing args into O[0-5].
605 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
606 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
607 InFlag = Chain.getValue(1);
610 // If the callee is a GlobalAddress node (quite common, every direct call is)
611 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
612 // Likewise ExternalSymbol -> TargetExternalSymbol.
613 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
614 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
615 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
616 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
618 std::vector<MVT::ValueType> NodeTys;
619 NodeTys.push_back(MVT::Other); // Returns a chain
620 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
621 SDOperand Ops[] = { Chain, Callee, InFlag };
622 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
623 InFlag = Chain.getValue(1);
625 MVT::ValueType RetTyVT = getValueType(RetTy);
627 if (RetTyVT != MVT::isVoid) {
629 default: assert(0 && "Unknown value type to return!");
633 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
634 Chain = RetVal.getValue(1);
636 // Add a note to keep track of whether it is sign or zero extended.
637 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
638 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
639 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
642 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
643 Chain = RetVal.getValue(1);
646 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
647 Chain = RetVal.getValue(1);
650 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
651 Chain = RetVal.getValue(1);
654 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
655 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
657 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
658 Chain = Hi.getValue(1);
663 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
664 DAG.getConstant(ArgsSize, getPointerTy()));
666 return std::make_pair(RetVal, Chain);
669 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
670 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
671 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
672 ISD::CondCode CC, unsigned &SPCC) {
673 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
675 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
676 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
677 (LHS.getOpcode() == SPISD::SELECT_FCC &&
678 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
679 isa<ConstantSDNode>(LHS.getOperand(0)) &&
680 isa<ConstantSDNode>(LHS.getOperand(1)) &&
681 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
682 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
683 SDOperand CMPCC = LHS.getOperand(3);
684 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
685 LHS = CMPCC.getOperand(0);
686 RHS = CMPCC.getOperand(1);
691 SDOperand SparcTargetLowering::
692 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
693 switch (Op.getOpcode()) {
694 default: assert(0 && "Should not custom lower this!");
695 case ISD::GlobalAddress: {
696 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
697 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
698 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
699 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
700 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
702 case ISD::ConstantPool: {
703 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
704 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
705 cast<ConstantPoolSDNode>(Op)->getAlignment());
706 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
707 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
708 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
710 case ISD::FP_TO_SINT:
711 // Convert the fp value to integer in an FP register.
712 assert(Op.getValueType() == MVT::i32);
713 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
714 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
715 case ISD::SINT_TO_FP: {
716 assert(Op.getOperand(0).getValueType() == MVT::i32);
717 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
718 // Convert the int value to FP in an FP register.
719 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
722 SDOperand Chain = Op.getOperand(0);
723 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
724 SDOperand LHS = Op.getOperand(2);
725 SDOperand RHS = Op.getOperand(3);
726 SDOperand Dest = Op.getOperand(4);
727 unsigned Opc, SPCC = ~0U;
729 // If this is a br_cc of a "setcc", and if the setcc got lowered into
730 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
731 LookThroughSetCC(LHS, RHS, CC, SPCC);
733 // Get the condition flag.
734 SDOperand CompareFlag;
735 if (LHS.getValueType() == MVT::i32) {
736 std::vector<MVT::ValueType> VTs;
737 VTs.push_back(MVT::i32);
738 VTs.push_back(MVT::Flag);
739 SDOperand Ops[2] = { LHS, RHS };
740 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
741 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
744 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
745 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
748 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
749 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
751 case ISD::SELECT_CC: {
752 SDOperand LHS = Op.getOperand(0);
753 SDOperand RHS = Op.getOperand(1);
754 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
755 SDOperand TrueVal = Op.getOperand(2);
756 SDOperand FalseVal = Op.getOperand(3);
757 unsigned Opc, SPCC = ~0U;
759 // If this is a select_cc of a "setcc", and if the setcc got lowered into
760 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
761 LookThroughSetCC(LHS, RHS, CC, SPCC);
763 SDOperand CompareFlag;
764 if (LHS.getValueType() == MVT::i32) {
765 std::vector<MVT::ValueType> VTs;
766 VTs.push_back(LHS.getValueType()); // subcc returns a value
767 VTs.push_back(MVT::Flag);
768 SDOperand Ops[2] = { LHS, RHS };
769 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
770 Opc = SPISD::SELECT_ICC;
771 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
773 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
774 Opc = SPISD::SELECT_FCC;
775 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
777 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
778 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
781 // vastart just stores the address of the VarArgsFrameIndex slot into the
782 // memory location argument.
783 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
784 DAG.getRegister(SP::I6, MVT::i32),
785 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
786 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
787 return DAG.getStore(Op.getOperand(0), Offset,
788 Op.getOperand(1), SV->getValue(), SV->getOffset());
791 SDNode *Node = Op.Val;
792 MVT::ValueType VT = Node->getValueType(0);
793 SDOperand InChain = Node->getOperand(0);
794 SDOperand VAListPtr = Node->getOperand(1);
795 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
796 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
797 SV->getValue(), SV->getOffset());
798 // Increment the pointer, VAList, to the next vaarg
799 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
800 DAG.getConstant(MVT::getSizeInBits(VT)/8,
802 // Store the incremented VAList to the legalized pointer
803 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
804 VAListPtr, SV->getValue(), SV->getOffset());
805 // Load the actual argument out of the pointer VAList, unless this is an
807 if (VT != MVT::f64) {
808 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
810 // Otherwise, load it as i64, then do a bitconvert.
811 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
812 std::vector<MVT::ValueType> Tys;
813 Tys.push_back(MVT::f64);
814 Tys.push_back(MVT::Other);
815 // Bit-Convert the value to f64.
816 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
818 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
821 case ISD::DYNAMIC_STACKALLOC: {
822 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
823 SDOperand Size = Op.getOperand(1); // Legalize the size.
825 unsigned SPReg = SP::O6;
826 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
827 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
828 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
830 // The resultant pointer is actually 16 words from the bottom of the stack,
831 // to provide a register spill area.
832 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
833 DAG.getConstant(96, MVT::i32));
834 std::vector<MVT::ValueType> Tys;
835 Tys.push_back(MVT::i32);
836 Tys.push_back(MVT::Other);
837 SDOperand Ops[2] = { NewVal, Chain };
838 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
843 switch(Op.getNumOperands()) {
845 assert(0 && "Do not know how to return this many arguments!");
848 return SDOperand(); // ret void is legal
851 switch(Op.getOperand(1).getValueType()) {
852 default: assert(0 && "Unknown type to return!");
853 case MVT::i32: ArgReg = SP::I0; break;
854 case MVT::f32: ArgReg = SP::F0; break;
855 case MVT::f64: ArgReg = SP::D0; break;
857 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
862 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
864 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
867 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
873 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
874 MachineBasicBlock *BB) {
875 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
878 // Figure out the conditional branch opcode to use for this select_cc.
879 switch (MI->getOpcode()) {
880 default: assert(0 && "Unknown SELECT_CC!");
881 case SP::SELECT_CC_Int_ICC:
882 case SP::SELECT_CC_FP_ICC:
883 case SP::SELECT_CC_DFP_ICC:
884 BROpcode = SP::BCOND;
886 case SP::SELECT_CC_Int_FCC:
887 case SP::SELECT_CC_FP_FCC:
888 case SP::SELECT_CC_DFP_FCC:
889 BROpcode = SP::FBCOND;
893 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
895 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
896 // control-flow pattern. The incoming instruction knows the destination vreg
897 // to set, the condition code register to branch on, the true/false values to
898 // select between, and a branch opcode to use.
899 const BasicBlock *LLVM_BB = BB->getBasicBlock();
900 ilist<MachineBasicBlock>::iterator It = BB;
907 // fallthrough --> copy0MBB
908 MachineBasicBlock *thisMBB = BB;
909 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
910 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
911 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
912 MachineFunction *F = BB->getParent();
913 F->getBasicBlockList().insert(It, copy0MBB);
914 F->getBasicBlockList().insert(It, sinkMBB);
915 // Update machine-CFG edges by first adding all successors of the current
916 // block to the new block which will contain the Phi node for the select.
917 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
918 e = BB->succ_end(); i != e; ++i)
919 sinkMBB->addSuccessor(*i);
920 // Next, remove all successors of the current block, and add the true
921 // and fallthrough blocks as its successors.
922 while(!BB->succ_empty())
923 BB->removeSuccessor(BB->succ_begin());
924 BB->addSuccessor(copy0MBB);
925 BB->addSuccessor(sinkMBB);
929 // # fallthrough to sinkMBB
932 // Update machine-CFG edges
933 BB->addSuccessor(sinkMBB);
936 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
939 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
940 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
941 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
943 delete MI; // The pseudo instruction is gone now.
947 //===----------------------------------------------------------------------===//
948 // Instruction Selector Implementation
949 //===----------------------------------------------------------------------===//
951 //===--------------------------------------------------------------------===//
952 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
953 /// instructions for SelectionDAG operations.
956 class SparcDAGToDAGISel : public SelectionDAGISel {
957 SparcTargetLowering Lowering;
959 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
960 /// make the right decision when generating code for different targets.
961 const SparcSubtarget &Subtarget;
963 SparcDAGToDAGISel(TargetMachine &TM)
964 : SelectionDAGISel(Lowering), Lowering(TM),
965 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
968 SDNode *Select(SDOperand Op);
970 // Complex Pattern Selectors.
971 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
972 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
975 /// InstructionSelectBasicBlock - This callback is invoked by
976 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
977 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
979 virtual const char *getPassName() const {
980 return "SPARC DAG->DAG Pattern Instruction Selection";
983 // Include the pieces autogenerated from the target description.
984 #include "SparcGenDAGISel.inc"
986 } // end anonymous namespace
988 /// InstructionSelectBasicBlock - This callback is invoked by
989 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
990 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
993 // Select target instructions for the DAG.
994 DAG.setRoot(SelectRoot(DAG.getRoot()));
995 DAG.RemoveDeadNodes();
997 // Emit machine code to BB.
998 ScheduleAndEmitDAG(DAG);
1001 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1002 SDOperand &Base, SDOperand &Offset) {
1003 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1004 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1005 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1008 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1009 Addr.getOpcode() == ISD::TargetGlobalAddress)
1010 return false; // direct calls.
1012 if (Addr.getOpcode() == ISD::ADD) {
1013 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1014 if (Predicate_simm13(CN)) {
1015 if (FrameIndexSDNode *FIN =
1016 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1017 // Constant offset from frame ref.
1018 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1020 Base = Addr.getOperand(0);
1022 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1026 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1027 Base = Addr.getOperand(1);
1028 Offset = Addr.getOperand(0).getOperand(0);
1031 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1032 Base = Addr.getOperand(0);
1033 Offset = Addr.getOperand(1).getOperand(0);
1038 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1042 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1043 SDOperand &R1, SDOperand &R2) {
1044 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1045 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1046 Addr.getOpcode() == ISD::TargetGlobalAddress)
1047 return false; // direct calls.
1049 if (Addr.getOpcode() == ISD::ADD) {
1050 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1051 Predicate_simm13(Addr.getOperand(1).Val))
1052 return false; // Let the reg+imm pattern catch this!
1053 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1054 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1055 return false; // Let the reg+imm pattern catch this!
1056 R1 = Addr.getOperand(0);
1057 R2 = Addr.getOperand(1);
1062 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1066 SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1068 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1069 N->getOpcode() < SPISD::FIRST_NUMBER)
1070 return NULL; // Already selected.
1072 switch (N->getOpcode()) {
1076 // FIXME: should use a custom expander to expose the SRA to the dag.
1077 SDOperand DivLHS = N->getOperand(0);
1078 SDOperand DivRHS = N->getOperand(1);
1079 AddToISelQueue(DivLHS);
1080 AddToISelQueue(DivRHS);
1082 // Set the Y register to the high-part.
1084 if (N->getOpcode() == ISD::SDIV) {
1085 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1086 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1088 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1090 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1091 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1093 // FIXME: Handle div by immediate.
1094 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1095 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1100 // FIXME: Handle mul by immediate.
1101 SDOperand MulLHS = N->getOperand(0);
1102 SDOperand MulRHS = N->getOperand(1);
1103 AddToISelQueue(MulLHS);
1104 AddToISelQueue(MulRHS);
1105 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1106 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1108 // The high part is in the Y register.
1109 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1114 return SelectCode(Op);
1118 /// createSparcISelDag - This pass converts a legalized DAG into a
1119 /// SPARC-specific DAG, ready for instruction scheduling.
1121 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1122 return new SparcDAGToDAGISel(TM);