1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "MCTargetDesc/SparcMCExpr.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/ErrorHandling.h"
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags, CCState &State)
43 assert (ArgFlags.isSRet());
45 // Assign SRet argument.
46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags, CCState &State)
56 static const uint16_t RegList[] = {
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
63 // Assign whole thing in stack.
64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65 State.AllocateStack(8,4),
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList, 6))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75 State.AllocateStack(4,4),
80 // Allocate a full-sized argument for the 64-bit ABI.
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128
85 || LocVT.getSizeInBits() == 64) &&
86 "Can't handle non-64 bits locations");
88 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
91 unsigned Offset = State.AllocateStack(size, alignment);
94 if (LocVT == MVT::i64 && Offset < 6*8)
95 // Promote integers to %i0-%i5.
96 Reg = SP::I0 + Offset/8;
97 else if (LocVT == MVT::f64 && Offset < 16*8)
98 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
99 Reg = SP::D0 + Offset/8;
100 else if (LocVT == MVT::f32 && Offset < 16*8)
101 // Promote floats to %f1, %f3, ...
102 Reg = SP::F1 + Offset/4;
103 else if (LocVT == MVT::f128 && Offset < 16*8)
104 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
105 Reg = SP::Q0 + Offset/16;
107 // Promote to register when possible, otherwise use the stack slot.
109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113 // This argument goes on the stack in an 8-byte slot.
114 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
115 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
116 if (LocVT == MVT::f32)
119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
123 // Allocate a half-sized argument for the 64-bit ABI.
125 // This is used when passing { float, int } structs by value in registers.
126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
127 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
129 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
130 unsigned Offset = State.AllocateStack(4, 4);
132 if (LocVT == MVT::f32 && Offset < 16*8) {
133 // Promote floats to %f0-%f31.
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
139 if (LocVT == MVT::i32 && Offset < 6*8) {
140 // Promote integers to %i0-%i5, using half the register.
141 unsigned Reg = SP::I0 + Offset/8;
143 LocInfo = CCValAssign::AExt;
145 // Set the Custom bit if this i32 goes in the high bits of a register.
147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
158 #include "SparcGenCallingConv.inc"
160 // The calling conventions in SparcCallingConv.td are described in terms of the
161 // callee's register window. This function translates registers to the
162 // corresponding caller window %o register.
163 static unsigned toCallerWindow(unsigned Reg) {
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
171 SparcTargetLowering::LowerReturn(SDValue Chain,
172 CallingConv::ID CallConv, bool IsVarArg,
173 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<SDValue> &OutVals,
175 SDLoc DL, SelectionDAG &DAG) const {
176 if (Subtarget->is64Bit())
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
182 SparcTargetLowering::LowerReturn_32(SDValue Chain,
183 CallingConv::ID CallConv, bool IsVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
189 // CCValAssign - represent the assignment of the return value to locations.
190 SmallVector<CCValAssign, 16> RVLocs;
192 // CCState - Info about the registers and stack slot.
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
194 DAG.getTarget(), RVLocs, *DAG.getContext());
196 // Analyze return values.
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
200 SmallVector<SDValue, 4> RetOps(1, Chain);
201 // Make room for the return address offset.
202 RetOps.push_back(SDValue());
204 // Copy the result values into the output registers.
205 for (unsigned i = 0; i != RVLocs.size(); ++i) {
206 CCValAssign &VA = RVLocs[i];
207 assert(VA.isRegLoc() && "Can only return in registers!");
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
212 // Guarantee that all emitted copies are stuck together with flags.
213 Flag = Chain.getValue(1);
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
217 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
218 // If the function returns a struct, copy the SRetReturnReg to I0
219 if (MF.getFunction()->hasStructRetAttr()) {
220 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
221 unsigned Reg = SFI->getSRetReturnReg();
223 llvm_unreachable("sret virtual register not created in the entry block");
224 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
226 Flag = Chain.getValue(1);
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
228 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
231 RetOps[0] = Chain; // Update chain.
232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
234 // Add the flag if we have it.
236 RetOps.push_back(Flag);
238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
239 &RetOps[0], RetOps.size());
242 // Lower return values for the 64-bit ABI.
243 // Return values are passed the exactly the same way as function arguments.
245 SparcTargetLowering::LowerReturn_64(SDValue Chain,
246 CallingConv::ID CallConv, bool IsVarArg,
247 const SmallVectorImpl<ISD::OutputArg> &Outs,
248 const SmallVectorImpl<SDValue> &OutVals,
249 SDLoc DL, SelectionDAG &DAG) const {
250 // CCValAssign - represent the assignment of the return value to locations.
251 SmallVector<CCValAssign, 16> RVLocs;
253 // CCState - Info about the registers and stack slot.
254 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
255 DAG.getTarget(), RVLocs, *DAG.getContext());
257 // Analyze return values.
258 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
261 SmallVector<SDValue, 4> RetOps(1, Chain);
263 // The second operand on the return instruction is the return address offset.
264 // The return address is always %i7+8 with the 64-bit ABI.
265 RetOps.push_back(DAG.getConstant(8, MVT::i32));
267 // Copy the result values into the output registers.
268 for (unsigned i = 0; i != RVLocs.size(); ++i) {
269 CCValAssign &VA = RVLocs[i];
270 assert(VA.isRegLoc() && "Can only return in registers!");
271 SDValue OutVal = OutVals[i];
273 // Integer return values must be sign or zero extended by the callee.
274 switch (VA.getLocInfo()) {
275 case CCValAssign::Full: break;
276 case CCValAssign::SExt:
277 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
279 case CCValAssign::ZExt:
280 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
282 case CCValAssign::AExt:
283 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
286 llvm_unreachable("Unknown loc info!");
289 // The custom bit on an i32 return value indicates that it should be passed
290 // in the high bits of the register.
291 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
292 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
293 DAG.getConstant(32, MVT::i32));
295 // The next value may go in the low bits of the same register.
296 // Handle both at once.
297 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
298 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
299 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
300 // Skip the next value, it's already done.
305 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
307 // Guarantee that all emitted copies are stuck together with flags.
308 Flag = Chain.getValue(1);
309 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
312 RetOps[0] = Chain; // Update chain.
314 // Add the flag if we have it.
316 RetOps.push_back(Flag);
318 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
319 &RetOps[0], RetOps.size());
322 SDValue SparcTargetLowering::
323 LowerFormalArguments(SDValue Chain,
324 CallingConv::ID CallConv,
326 const SmallVectorImpl<ISD::InputArg> &Ins,
329 SmallVectorImpl<SDValue> &InVals) const {
330 if (Subtarget->is64Bit())
331 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
333 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
337 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
338 /// passed in either one or two GPRs, including FP values. TODO: we should
339 /// pass FP values in FP registers for fastcc functions.
340 SDValue SparcTargetLowering::
341 LowerFormalArguments_32(SDValue Chain,
342 CallingConv::ID CallConv,
344 const SmallVectorImpl<ISD::InputArg> &Ins,
347 SmallVectorImpl<SDValue> &InVals) const {
348 MachineFunction &MF = DAG.getMachineFunction();
349 MachineRegisterInfo &RegInfo = MF.getRegInfo();
350 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
352 // Assign locations to all of the incoming arguments.
353 SmallVector<CCValAssign, 16> ArgLocs;
354 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
355 getTargetMachine(), ArgLocs, *DAG.getContext());
356 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
358 const unsigned StackOffset = 92;
360 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
361 CCValAssign &VA = ArgLocs[i];
363 if (i == 0 && Ins[i].Flags.isSRet()) {
364 // Get SRet from [%fp+64].
365 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
366 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
367 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
368 MachinePointerInfo(),
369 false, false, false, 0);
370 InVals.push_back(Arg);
375 if (VA.needsCustom()) {
376 assert(VA.getLocVT() == MVT::f64);
377 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
378 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
379 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
382 CCValAssign &NextVA = ArgLocs[++i];
385 if (NextVA.isMemLoc()) {
386 int FrameIdx = MF.getFrameInfo()->
387 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
388 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
389 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
390 MachinePointerInfo(),
391 false, false, false, 0);
393 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
394 &SP::IntRegsRegClass);
395 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
398 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
399 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
400 InVals.push_back(WholeValue);
403 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
404 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
405 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
406 if (VA.getLocVT() == MVT::f32)
407 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
408 else if (VA.getLocVT() != MVT::i32) {
409 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
410 DAG.getValueType(VA.getLocVT()));
411 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
413 InVals.push_back(Arg);
417 assert(VA.isMemLoc());
419 unsigned Offset = VA.getLocMemOffset()+StackOffset;
421 if (VA.needsCustom()) {
422 assert(VA.getValVT() == MVT::f64);
423 // If it is double-word aligned, just load.
424 if (Offset % 8 == 0) {
425 int FI = MF.getFrameInfo()->CreateFixedObject(8,
428 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
429 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
430 MachinePointerInfo(),
431 false,false, false, 0);
432 InVals.push_back(Load);
436 int FI = MF.getFrameInfo()->CreateFixedObject(4,
439 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
440 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
441 MachinePointerInfo(),
442 false, false, false, 0);
443 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
446 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
448 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
449 MachinePointerInfo(),
450 false, false, false, 0);
453 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
454 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
455 InVals.push_back(WholeValue);
459 int FI = MF.getFrameInfo()->CreateFixedObject(4,
462 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
464 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
465 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
466 MachinePointerInfo(),
467 false, false, false, 0);
469 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
470 // Sparc is big endian, so add an offset based on the ObjectVT.
471 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
472 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
473 DAG.getConstant(Offset, MVT::i32));
474 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
475 MachinePointerInfo(),
476 VA.getValVT(), false, false,0);
477 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
479 InVals.push_back(Load);
482 if (MF.getFunction()->hasStructRetAttr()) {
483 // Copy the SRet Argument to SRetReturnReg.
484 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
485 unsigned Reg = SFI->getSRetReturnReg();
487 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
488 SFI->setSRetReturnReg(Reg);
490 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
491 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
494 // Store remaining ArgRegs to the stack if this is a varargs function.
496 static const uint16_t ArgRegs[] = {
497 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
499 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
500 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
501 unsigned ArgOffset = CCInfo.getNextStackOffset();
502 if (NumAllocated == 6)
503 ArgOffset += StackOffset;
506 ArgOffset = 68+4*NumAllocated;
509 // Remember the vararg offset for the va_start implementation.
510 FuncInfo->setVarArgsFrameOffset(ArgOffset);
512 std::vector<SDValue> OutChains;
514 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
515 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
516 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
517 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
519 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
521 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
523 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
524 MachinePointerInfo(),
529 if (!OutChains.empty()) {
530 OutChains.push_back(Chain);
531 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
532 &OutChains[0], OutChains.size());
539 // Lower formal arguments for the 64 bit ABI.
540 SDValue SparcTargetLowering::
541 LowerFormalArguments_64(SDValue Chain,
542 CallingConv::ID CallConv,
544 const SmallVectorImpl<ISD::InputArg> &Ins,
547 SmallVectorImpl<SDValue> &InVals) const {
548 MachineFunction &MF = DAG.getMachineFunction();
550 // Analyze arguments according to CC_Sparc64.
551 SmallVector<CCValAssign, 16> ArgLocs;
552 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
553 getTargetMachine(), ArgLocs, *DAG.getContext());
554 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
556 // The argument array begins at %fp+BIAS+128, after the register save area.
557 const unsigned ArgArea = 128;
559 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
560 CCValAssign &VA = ArgLocs[i];
562 // This argument is passed in a register.
563 // All integer register arguments are promoted by the caller to i64.
565 // Create a virtual register for the promoted live-in value.
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
567 getRegClassFor(VA.getLocVT()));
568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
570 // Get the high bits for i32 struct elements.
571 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
573 DAG.getConstant(32, MVT::i32));
575 // The caller promoted the argument, so insert an Assert?ext SDNode so we
576 // won't promote the value again in this function.
577 switch (VA.getLocInfo()) {
578 case CCValAssign::SExt:
579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
580 DAG.getValueType(VA.getValVT()));
582 case CCValAssign::ZExt:
583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
584 DAG.getValueType(VA.getValVT()));
590 // Truncate the register down to the argument type.
592 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
594 InVals.push_back(Arg);
598 // The registers are exhausted. This argument was passed on the stack.
599 assert(VA.isMemLoc());
600 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
601 // beginning of the arguments area at %fp+BIAS+128.
602 unsigned Offset = VA.getLocMemOffset() + ArgArea;
603 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
604 // Adjust offset for extended arguments, SPARC is big-endian.
605 // The caller will have written the full slot with extended bytes, but we
606 // prefer our own extending loads.
608 Offset += 8 - ValSize;
609 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
610 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
611 DAG.getFrameIndex(FI, getPointerTy()),
612 MachinePointerInfo::getFixedStack(FI),
613 false, false, false, 0));
619 // This function takes variable arguments, some of which may have been passed
620 // in registers %i0-%i5. Variable floating point arguments are never passed
621 // in floating point registers. They go on %i0-%i5 or on the stack like
622 // integer arguments.
624 // The va_start intrinsic needs to know the offset to the first variable
626 unsigned ArgOffset = CCInfo.getNextStackOffset();
627 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
628 // Skip the 128 bytes of register save area.
629 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
630 Subtarget->getStackPointerBias());
632 // Save the variable arguments that were passed in registers.
633 // The caller is required to reserve stack space for 6 arguments regardless
634 // of how many arguments were actually passed.
635 SmallVector<SDValue, 8> OutChains;
636 for (; ArgOffset < 6*8; ArgOffset += 8) {
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
639 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
640 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
641 DAG.getFrameIndex(FI, getPointerTy()),
642 MachinePointerInfo::getFixedStack(FI),
646 if (!OutChains.empty())
647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
648 &OutChains[0], OutChains.size());
654 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
655 SmallVectorImpl<SDValue> &InVals) const {
656 if (Subtarget->is64Bit())
657 return LowerCall_64(CLI, InVals);
658 return LowerCall_32(CLI, InVals);
661 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
662 ImmutableCallSite *CS) {
664 return CS->hasFnAttr(Attribute::ReturnsTwice);
666 const Function *CalleeFn = 0;
667 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
668 CalleeFn = dyn_cast<Function>(G->getGlobal());
669 } else if (ExternalSymbolSDNode *E =
670 dyn_cast<ExternalSymbolSDNode>(Callee)) {
671 const Function *Fn = DAG.getMachineFunction().getFunction();
672 const Module *M = Fn->getParent();
673 const char *CalleeName = E->getSymbol();
674 CalleeFn = M->getFunction(CalleeName);
679 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
682 // Lower a call for the 32-bit ABI.
684 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
685 SmallVectorImpl<SDValue> &InVals) const {
686 SelectionDAG &DAG = CLI.DAG;
688 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
689 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
690 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
691 SDValue Chain = CLI.Chain;
692 SDValue Callee = CLI.Callee;
693 bool &isTailCall = CLI.IsTailCall;
694 CallingConv::ID CallConv = CLI.CallConv;
695 bool isVarArg = CLI.IsVarArg;
697 // Sparc target does not yet support tail call optimization.
700 // Analyze operands of the call, assigning locations to each operand.
701 SmallVector<CCValAssign, 16> ArgLocs;
702 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
703 DAG.getTarget(), ArgLocs, *DAG.getContext());
704 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
706 // Get the size of the outgoing arguments stack space requirement.
707 unsigned ArgsSize = CCInfo.getNextStackOffset();
709 // Keep stack frames 8-byte aligned.
710 ArgsSize = (ArgsSize+7) & ~7;
712 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
714 // Create local copies for byval args.
715 SmallVector<SDValue, 8> ByValArgs;
716 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
717 ISD::ArgFlagsTy Flags = Outs[i].Flags;
718 if (!Flags.isByVal())
721 SDValue Arg = OutVals[i];
722 unsigned Size = Flags.getByValSize();
723 unsigned Align = Flags.getByValAlign();
725 int FI = MFI->CreateStackObject(Size, Align, false);
726 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
727 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
729 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
730 false, // isVolatile,
731 (Size <= 32), // AlwaysInline if size <= 32
732 MachinePointerInfo(), MachinePointerInfo());
733 ByValArgs.push_back(FIPtr);
736 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
739 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
740 SmallVector<SDValue, 8> MemOpChains;
742 const unsigned StackOffset = 92;
743 bool hasStructRetAttr = false;
744 // Walk the register/memloc assignments, inserting copies/loads.
745 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
748 CCValAssign &VA = ArgLocs[i];
749 SDValue Arg = OutVals[realArgIdx];
751 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
753 // Use local copy if it is a byval arg.
755 Arg = ByValArgs[byvalArgIdx++];
757 // Promote the value if needed.
758 switch (VA.getLocInfo()) {
759 default: llvm_unreachable("Unknown loc info!");
760 case CCValAssign::Full: break;
761 case CCValAssign::SExt:
762 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
764 case CCValAssign::ZExt:
765 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
767 case CCValAssign::AExt:
768 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
770 case CCValAssign::BCvt:
771 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
775 if (Flags.isSRet()) {
776 assert(VA.needsCustom());
777 // store SRet argument in %sp+64
778 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
779 SDValue PtrOff = DAG.getIntPtrConstant(64);
780 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
782 MachinePointerInfo(),
784 hasStructRetAttr = true;
788 if (VA.needsCustom()) {
789 assert(VA.getLocVT() == MVT::f64);
792 unsigned Offset = VA.getLocMemOffset() + StackOffset;
793 // if it is double-word aligned, just store.
794 if (Offset % 8 == 0) {
795 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
796 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
797 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
798 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
799 MachinePointerInfo(),
805 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
806 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
807 Arg, StackPtr, MachinePointerInfo(),
809 // Sparc is big-endian, so the high part comes first.
810 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
811 MachinePointerInfo(), false, false, false, 0);
812 // Increment the pointer to the other half.
813 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
814 DAG.getIntPtrConstant(4));
815 // Load the low part.
816 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
817 MachinePointerInfo(), false, false, false, 0);
820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
822 CCValAssign &NextVA = ArgLocs[++i];
823 if (NextVA.isRegLoc()) {
824 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
826 // Store the low part in stack.
827 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
828 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
829 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
830 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
831 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
832 MachinePointerInfo(),
836 unsigned Offset = VA.getLocMemOffset() + StackOffset;
837 // Store the high part.
838 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
839 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
840 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
841 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
842 MachinePointerInfo(),
844 // Store the low part.
845 PtrOff = DAG.getIntPtrConstant(Offset+4);
846 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
847 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
848 MachinePointerInfo(),
854 // Arguments that can be passed on register must be kept at
857 if (VA.getLocVT() != MVT::f32) {
858 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
861 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
862 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
866 assert(VA.isMemLoc());
868 // Create a store off the stack pointer for this argument.
869 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
870 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
871 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
872 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
873 MachinePointerInfo(),
878 // Emit all stores, make sure the occur before any copies into physregs.
879 if (!MemOpChains.empty())
880 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
881 &MemOpChains[0], MemOpChains.size());
883 // Build a sequence of copy-to-reg nodes chained together with token
884 // chain and flag operands which copy the outgoing args into registers.
885 // The InFlag in necessary since all emitted instructions must be
888 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
889 unsigned Reg = toCallerWindow(RegsToPass[i].first);
890 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
891 InFlag = Chain.getValue(1);
894 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
895 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
897 // If the callee is a GlobalAddress node (quite common, every direct call is)
898 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
899 // Likewise ExternalSymbol -> TargetExternalSymbol.
900 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
901 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
902 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
903 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
904 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
905 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
907 // Returns a chain & a flag for retval copy to use
908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
909 SmallVector<SDValue, 8> Ops;
910 Ops.push_back(Chain);
911 Ops.push_back(Callee);
912 if (hasStructRetAttr)
913 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
914 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
915 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
916 RegsToPass[i].second.getValueType()));
918 // Add a register mask operand representing the call-preserved registers.
919 const SparcRegisterInfo *TRI =
920 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
921 const uint32_t *Mask = ((hasReturnsTwice)
922 ? TRI->getRTCallPreservedMask(CallConv)
923 : TRI->getCallPreservedMask(CallConv));
924 assert(Mask && "Missing call preserved mask for calling convention");
925 Ops.push_back(DAG.getRegisterMask(Mask));
927 if (InFlag.getNode())
928 Ops.push_back(InFlag);
930 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
931 InFlag = Chain.getValue(1);
933 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
934 DAG.getIntPtrConstant(0, true), InFlag, dl);
935 InFlag = Chain.getValue(1);
937 // Assign locations to each value returned by this call.
938 SmallVector<CCValAssign, 16> RVLocs;
939 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
940 DAG.getTarget(), RVLocs, *DAG.getContext());
942 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
944 // Copy all of the result registers out of their specified physreg.
945 for (unsigned i = 0; i != RVLocs.size(); ++i) {
946 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
947 RVLocs[i].getValVT(), InFlag).getValue(1);
948 InFlag = Chain.getValue(2);
949 InVals.push_back(Chain.getValue(0));
955 // This functions returns true if CalleeName is a ABI function that returns
956 // a long double (fp128).
957 static bool isFP128ABICall(const char *CalleeName)
959 static const char *const ABICalls[] =
960 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
962 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
963 "_Q_lltoq", "_Q_ulltoq",
966 for (const char * const *I = ABICalls; *I != 0; ++I)
967 if (strcmp(CalleeName, *I) == 0)
973 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
975 const Function *CalleeFn = 0;
976 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
977 CalleeFn = dyn_cast<Function>(G->getGlobal());
978 } else if (ExternalSymbolSDNode *E =
979 dyn_cast<ExternalSymbolSDNode>(Callee)) {
980 const Function *Fn = DAG.getMachineFunction().getFunction();
981 const Module *M = Fn->getParent();
982 const char *CalleeName = E->getSymbol();
983 CalleeFn = M->getFunction(CalleeName);
984 if (!CalleeFn && isFP128ABICall(CalleeName))
985 return 16; // Return sizeof(fp128)
991 assert(CalleeFn->hasStructRetAttr() &&
992 "Callee does not have the StructRet attribute.");
994 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
995 Type *ElementTy = Ty->getElementType();
996 return getDataLayout()->getTypeAllocSize(ElementTy);
1000 // Fixup floating point arguments in the ... part of a varargs call.
1002 // The SPARC v9 ABI requires that floating point arguments are treated the same
1003 // as integers when calling a varargs function. This does not apply to the
1004 // fixed arguments that are part of the function's prototype.
1006 // This function post-processes a CCValAssign array created by
1007 // AnalyzeCallOperands().
1008 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1009 ArrayRef<ISD::OutputArg> Outs) {
1010 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1011 const CCValAssign &VA = ArgLocs[i];
1012 MVT ValTy = VA.getLocVT();
1013 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1014 // varargs functions.
1015 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1017 // The fixed arguments to a varargs function still go in FP registers.
1018 if (Outs[VA.getValNo()].IsFixed)
1021 // This floating point argument should be reassigned.
1024 // Determine the offset into the argument array.
1025 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1026 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1027 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1028 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1031 // This argument should go in %i0-%i5.
1032 unsigned IReg = SP::I0 + Offset/8;
1033 if (ValTy == MVT::f64)
1034 // Full register, just bitconvert into i64.
1035 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1036 IReg, MVT::i64, CCValAssign::BCvt);
1038 assert(ValTy == MVT::f128 && "Unexpected type!");
1039 // Full register, just bitconvert into i128 -- We will lower this into
1040 // two i64s in LowerCall_64.
1041 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1042 IReg, MVT::i128, CCValAssign::BCvt);
1045 // This needs to go to memory, we're out of integer registers.
1046 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1047 Offset, VA.getLocVT(), VA.getLocInfo());
1053 // Lower a call for the 64-bit ABI.
1055 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1056 SmallVectorImpl<SDValue> &InVals) const {
1057 SelectionDAG &DAG = CLI.DAG;
1059 SDValue Chain = CLI.Chain;
1061 // Sparc target does not yet support tail call optimization.
1062 CLI.IsTailCall = false;
1064 // Analyze operands of the call, assigning locations to each operand.
1065 SmallVector<CCValAssign, 16> ArgLocs;
1066 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1067 DAG.getTarget(), ArgLocs, *DAG.getContext());
1068 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1070 // Get the size of the outgoing arguments stack space requirement.
1071 // The stack offset computed by CC_Sparc64 includes all arguments.
1072 // Called functions expect 6 argument words to exist in the stack frame, used
1074 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1076 // Keep stack frames 16-byte aligned.
1077 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1079 // Varargs calls require special treatment.
1081 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1083 // Adjust the stack pointer to make room for the arguments.
1084 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1085 // with more than 6 arguments.
1086 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1089 // Collect the set of registers to pass to the function and their values.
1090 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1092 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1094 // Collect chains from all the memory opeations that copy arguments to the
1095 // stack. They must follow the stack pointer adjustment above and precede the
1096 // call instruction itself.
1097 SmallVector<SDValue, 8> MemOpChains;
1099 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1100 const CCValAssign &VA = ArgLocs[i];
1101 SDValue Arg = CLI.OutVals[i];
1103 // Promote the value if needed.
1104 switch (VA.getLocInfo()) {
1106 llvm_unreachable("Unknown location info!");
1107 case CCValAssign::Full:
1109 case CCValAssign::SExt:
1110 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1112 case CCValAssign::ZExt:
1113 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1115 case CCValAssign::AExt:
1116 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1118 case CCValAssign::BCvt:
1119 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1120 // SPARC does not support i128 natively. Lower it into two i64, see below.
1121 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1122 || VA.getLocVT() != MVT::i128)
1123 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1127 if (VA.isRegLoc()) {
1128 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1129 && VA.getLocVT() == MVT::i128) {
1130 // Store and reload into the interger register reg and reg+1.
1131 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1132 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1133 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1134 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
1135 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1137 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
1138 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1141 // Store to %sp+BIAS+128+Offset
1142 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1143 MachinePointerInfo(),
1145 // Load into Reg and Reg+1
1146 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1147 MachinePointerInfo(),
1148 false, false, false, 0);
1149 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1150 MachinePointerInfo(),
1151 false, false, false, 0);
1152 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1154 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1159 // The custom bit on an i32 return value indicates that it should be
1160 // passed in the high bits of the register.
1161 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1162 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1163 DAG.getConstant(32, MVT::i32));
1165 // The next value may go in the low bits of the same register.
1166 // Handle both at once.
1167 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1168 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1169 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1171 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1172 // Skip the next value, it's already done.
1176 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1180 assert(VA.isMemLoc());
1182 // Create a store off the stack pointer for this argument.
1183 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1184 // The argument area starts at %fp+BIAS+128 in the callee frame,
1185 // %sp+BIAS+128 in ours.
1186 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1187 Subtarget->getStackPointerBias() +
1189 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1190 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1191 MachinePointerInfo(),
1195 // Emit all stores, make sure they occur before the call.
1196 if (!MemOpChains.empty())
1197 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1198 &MemOpChains[0], MemOpChains.size());
1200 // Build a sequence of CopyToReg nodes glued together with token chain and
1201 // glue operands which copy the outgoing args into registers. The InGlue is
1202 // necessary since all emitted instructions must be stuck together in order
1203 // to pass the live physical registers.
1205 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1206 Chain = DAG.getCopyToReg(Chain, DL,
1207 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1208 InGlue = Chain.getValue(1);
1211 // If the callee is a GlobalAddress node (quite common, every direct call is)
1212 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1213 // Likewise ExternalSymbol -> TargetExternalSymbol.
1214 SDValue Callee = CLI.Callee;
1215 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1216 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1217 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
1218 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1219 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
1221 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1222 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF);
1224 // Build the operands for the call instruction itself.
1225 SmallVector<SDValue, 8> Ops;
1226 Ops.push_back(Chain);
1227 Ops.push_back(Callee);
1228 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1229 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1230 RegsToPass[i].second.getValueType()));
1232 // Add a register mask operand representing the call-preserved registers.
1233 const SparcRegisterInfo *TRI =
1234 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
1235 const uint32_t *Mask = ((hasReturnsTwice)
1236 ? TRI->getRTCallPreservedMask(CLI.CallConv)
1237 : TRI->getCallPreservedMask(CLI.CallConv));
1238 assert(Mask && "Missing call preserved mask for calling convention");
1239 Ops.push_back(DAG.getRegisterMask(Mask));
1241 // Make sure the CopyToReg nodes are glued to the call instruction which
1242 // consumes the registers.
1243 if (InGlue.getNode())
1244 Ops.push_back(InGlue);
1246 // Now the call itself.
1247 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1248 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
1249 InGlue = Chain.getValue(1);
1251 // Revert the stack pointer immediately after the call.
1252 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1253 DAG.getIntPtrConstant(0, true), InGlue, DL);
1254 InGlue = Chain.getValue(1);
1256 // Now extract the return values. This is more or less the same as
1257 // LowerFormalArguments_64.
1259 // Assign locations to each value returned by this call.
1260 SmallVector<CCValAssign, 16> RVLocs;
1261 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1262 DAG.getTarget(), RVLocs, *DAG.getContext());
1264 // Set inreg flag manually for codegen generated library calls that
1266 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0)
1267 CLI.Ins[0].Flags.setInReg();
1269 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1271 // Copy all of the result registers out of their specified physreg.
1272 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1273 CCValAssign &VA = RVLocs[i];
1274 unsigned Reg = toCallerWindow(VA.getLocReg());
1276 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1277 // reside in the same register in the high and low bits. Reuse the
1278 // CopyFromReg previous node to avoid duplicate copies.
1280 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1281 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1282 RV = Chain.getValue(0);
1284 // But usually we'll create a new CopyFromReg for a different register.
1285 if (!RV.getNode()) {
1286 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1287 Chain = RV.getValue(1);
1288 InGlue = Chain.getValue(2);
1291 // Get the high bits for i32 struct elements.
1292 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1293 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1294 DAG.getConstant(32, MVT::i32));
1296 // The callee promoted the return value, so insert an Assert?ext SDNode so
1297 // we won't promote the value again in this function.
1298 switch (VA.getLocInfo()) {
1299 case CCValAssign::SExt:
1300 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1301 DAG.getValueType(VA.getValVT()));
1303 case CCValAssign::ZExt:
1304 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1305 DAG.getValueType(VA.getValVT()));
1311 // Truncate the register down to the return value type.
1312 if (VA.isExtInLoc())
1313 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1315 InVals.push_back(RV);
1321 //===----------------------------------------------------------------------===//
1322 // TargetLowering Implementation
1323 //===----------------------------------------------------------------------===//
1325 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1327 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1329 default: llvm_unreachable("Unknown integer condition code!");
1330 case ISD::SETEQ: return SPCC::ICC_E;
1331 case ISD::SETNE: return SPCC::ICC_NE;
1332 case ISD::SETLT: return SPCC::ICC_L;
1333 case ISD::SETGT: return SPCC::ICC_G;
1334 case ISD::SETLE: return SPCC::ICC_LE;
1335 case ISD::SETGE: return SPCC::ICC_GE;
1336 case ISD::SETULT: return SPCC::ICC_CS;
1337 case ISD::SETULE: return SPCC::ICC_LEU;
1338 case ISD::SETUGT: return SPCC::ICC_GU;
1339 case ISD::SETUGE: return SPCC::ICC_CC;
1343 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1345 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1347 default: llvm_unreachable("Unknown fp condition code!");
1349 case ISD::SETOEQ: return SPCC::FCC_E;
1351 case ISD::SETUNE: return SPCC::FCC_NE;
1353 case ISD::SETOLT: return SPCC::FCC_L;
1355 case ISD::SETOGT: return SPCC::FCC_G;
1357 case ISD::SETOLE: return SPCC::FCC_LE;
1359 case ISD::SETOGE: return SPCC::FCC_GE;
1360 case ISD::SETULT: return SPCC::FCC_UL;
1361 case ISD::SETULE: return SPCC::FCC_ULE;
1362 case ISD::SETUGT: return SPCC::FCC_UG;
1363 case ISD::SETUGE: return SPCC::FCC_UGE;
1364 case ISD::SETUO: return SPCC::FCC_U;
1365 case ISD::SETO: return SPCC::FCC_O;
1366 case ISD::SETONE: return SPCC::FCC_LG;
1367 case ISD::SETUEQ: return SPCC::FCC_UE;
1371 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1372 : TargetLowering(TM, new SparcELFTargetObjectFile()) {
1373 Subtarget = &TM.getSubtarget<SparcSubtarget>();
1375 // Set up the register classes.
1376 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1377 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1378 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1379 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1380 if (Subtarget->is64Bit())
1381 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1383 // Turn FP extload into load/fextend
1384 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1385 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
1387 // Sparc doesn't have i1 sign extending load
1388 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1390 // Turn FP truncstore into trunc + store.
1391 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1392 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1393 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1395 // Custom legalize GlobalAddress nodes into LO/HI parts.
1396 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1397 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1398 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1399 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1401 // Sparc doesn't have sext_inreg, replace them with shl/sra
1402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1406 // Sparc has no REM or DIVREM operations.
1407 setOperationAction(ISD::UREM, MVT::i32, Expand);
1408 setOperationAction(ISD::SREM, MVT::i32, Expand);
1409 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1410 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1412 // ... nor does SparcV9.
1413 if (Subtarget->is64Bit()) {
1414 setOperationAction(ISD::UREM, MVT::i64, Expand);
1415 setOperationAction(ISD::SREM, MVT::i64, Expand);
1416 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1417 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1420 // Custom expand fp<->sint
1421 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1426 // Custom Expand fp<->uint
1427 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1428 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1430 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1432 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1433 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1435 // Sparc has no select or setcc: expand to SELECT_CC.
1436 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1437 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1438 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1439 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1441 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1442 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1443 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1444 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1446 // Sparc doesn't have BRCOND either, it has BR_CC.
1447 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1448 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1449 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1450 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1451 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1452 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1453 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1455 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1458 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1460 if (Subtarget->is64Bit()) {
1461 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1462 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1463 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1464 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1465 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1466 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1467 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1468 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1469 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1470 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1472 setOperationAction(ISD::CTPOP, MVT::i64,
1473 Subtarget->usePopc() ? Legal : Expand);
1474 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1476 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1478 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1479 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1480 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1481 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1485 // FIXME: We insert fences for each atomics and generate sub-optimal code
1486 // for PSO/TSO. Also, implement other atomicrmw operations.
1488 setInsertFencesForAtomic(true);
1490 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1491 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
1492 (Subtarget->isV9() ? Legal: Expand));
1495 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1497 // Custom Lower Atomic LOAD/STORE
1498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1499 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1501 if (Subtarget->is64Bit()) {
1502 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1503 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1505 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1508 if (!Subtarget->isV9()) {
1509 // SparcV8 does not have FNEGD and FABSD.
1510 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1511 setOperationAction(ISD::FABS, MVT::f64, Custom);
1514 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1515 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1516 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1517 setOperationAction(ISD::FREM , MVT::f128, Expand);
1518 setOperationAction(ISD::FMA , MVT::f128, Expand);
1519 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1520 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1521 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1522 setOperationAction(ISD::FREM , MVT::f64, Expand);
1523 setOperationAction(ISD::FMA , MVT::f64, Expand);
1524 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1525 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1526 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1527 setOperationAction(ISD::FREM , MVT::f32, Expand);
1528 setOperationAction(ISD::FMA , MVT::f32, Expand);
1529 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1531 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1532 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1533 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1534 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1535 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1536 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1537 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1538 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1539 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1540 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1541 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1543 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1544 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1545 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1547 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1548 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1549 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1551 if (Subtarget->is64Bit()) {
1552 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1553 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1554 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1555 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1557 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1558 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1560 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1561 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1562 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1565 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1566 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1567 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1568 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1570 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1572 // Use the default implementation.
1573 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1574 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1575 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1576 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1579 setExceptionPointerRegister(SP::I0);
1580 setExceptionSelectorRegister(SP::I1);
1582 setStackPointerRegisterToSaveRestore(SP::O6);
1584 setOperationAction(ISD::CTPOP, MVT::i32,
1585 Subtarget->usePopc() ? Legal : Expand);
1587 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1588 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1589 setOperationAction(ISD::STORE, MVT::f128, Legal);
1591 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1592 setOperationAction(ISD::STORE, MVT::f128, Custom);
1595 if (Subtarget->hasHardQuad()) {
1596 setOperationAction(ISD::FADD, MVT::f128, Legal);
1597 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1598 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1599 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1600 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1601 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1602 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1603 if (Subtarget->isV9()) {
1604 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1605 setOperationAction(ISD::FABS, MVT::f128, Legal);
1607 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1608 setOperationAction(ISD::FABS, MVT::f128, Custom);
1611 if (!Subtarget->is64Bit()) {
1612 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1613 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1614 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1615 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1619 // Custom legalize f128 operations.
1621 setOperationAction(ISD::FADD, MVT::f128, Custom);
1622 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1623 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1624 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1625 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1626 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1627 setOperationAction(ISD::FABS, MVT::f128, Custom);
1629 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1630 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1631 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1633 // Setup Runtime library names.
1634 if (Subtarget->is64Bit()) {
1635 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1636 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1637 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1638 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1639 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1640 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1641 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1642 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1643 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1644 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1645 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1646 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1647 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1648 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1649 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1650 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1651 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1653 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1654 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1655 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1656 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1657 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1658 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1659 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1660 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1661 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1662 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1663 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1664 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1665 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1666 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1667 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1668 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1669 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1673 setMinFunctionAlignment(2);
1675 computeRegisterProperties();
1678 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1681 case SPISD::CMPICC: return "SPISD::CMPICC";
1682 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1683 case SPISD::BRICC: return "SPISD::BRICC";
1684 case SPISD::BRXCC: return "SPISD::BRXCC";
1685 case SPISD::BRFCC: return "SPISD::BRFCC";
1686 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1687 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1688 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1689 case SPISD::Hi: return "SPISD::Hi";
1690 case SPISD::Lo: return "SPISD::Lo";
1691 case SPISD::FTOI: return "SPISD::FTOI";
1692 case SPISD::ITOF: return "SPISD::ITOF";
1693 case SPISD::FTOX: return "SPISD::FTOX";
1694 case SPISD::XTOF: return "SPISD::XTOF";
1695 case SPISD::CALL: return "SPISD::CALL";
1696 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1697 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1698 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1699 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1700 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1701 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1705 EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1708 return VT.changeVectorElementTypeToInteger();
1711 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1712 /// be zero. Op is expected to be a target specific node. Used by DAG
1714 void SparcTargetLowering::computeMaskedBitsForTargetNode
1718 const SelectionDAG &DAG,
1719 unsigned Depth) const {
1720 APInt KnownZero2, KnownOne2;
1721 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1723 switch (Op.getOpcode()) {
1725 case SPISD::SELECT_ICC:
1726 case SPISD::SELECT_XCC:
1727 case SPISD::SELECT_FCC:
1728 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1729 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1730 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1731 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1733 // Only known if known in both the LHS and RHS.
1734 KnownOne &= KnownOne2;
1735 KnownZero &= KnownZero2;
1740 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1741 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1742 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1743 ISD::CondCode CC, unsigned &SPCC) {
1744 if (isa<ConstantSDNode>(RHS) &&
1745 cast<ConstantSDNode>(RHS)->isNullValue() &&
1747 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1748 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1749 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1750 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1751 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1752 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1753 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1754 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1755 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1756 SDValue CMPCC = LHS.getOperand(3);
1757 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1758 LHS = CMPCC.getOperand(0);
1759 RHS = CMPCC.getOperand(1);
1763 // Convert to a target node and set target flags.
1764 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1765 SelectionDAG &DAG) const {
1766 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1767 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1769 GA->getValueType(0),
1770 GA->getOffset(), TF);
1772 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1773 return DAG.getTargetConstantPool(CP->getConstVal(),
1774 CP->getValueType(0),
1776 CP->getOffset(), TF);
1778 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1779 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1784 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1785 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1786 ES->getValueType(0), TF);
1788 llvm_unreachable("Unhandled address SDNode");
1791 // Split Op into high and low parts according to HiTF and LoTF.
1792 // Return an ADD node combining the parts.
1793 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1794 unsigned HiTF, unsigned LoTF,
1795 SelectionDAG &DAG) const {
1797 EVT VT = Op.getValueType();
1798 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1799 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1800 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1803 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1804 // or ExternalSymbol SDNode.
1805 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1807 EVT VT = getPointerTy();
1809 // Handle PIC mode first.
1810 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1811 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1812 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1813 SparcMCExpr::VK_Sparc_GOT10, DAG);
1814 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1815 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1816 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1817 // function has calls.
1818 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1819 MFI->setHasCalls(true);
1820 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1821 MachinePointerInfo::getGOT(), false, false, false, 0);
1824 // This is one of the absolute code models.
1825 switch(getTargetMachine().getCodeModel()) {
1827 llvm_unreachable("Unsupported absolute code model");
1828 case CodeModel::Small:
1830 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1831 SparcMCExpr::VK_Sparc_LO, DAG);
1832 case CodeModel::Medium: {
1834 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1835 SparcMCExpr::VK_Sparc_M44, DAG);
1836 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1837 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1838 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1839 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1841 case CodeModel::Large: {
1843 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1844 SparcMCExpr::VK_Sparc_HM, DAG);
1845 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1846 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1847 SparcMCExpr::VK_Sparc_LO, DAG);
1848 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1853 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1854 SelectionDAG &DAG) const {
1855 return makeAddress(Op, DAG);
1858 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1859 SelectionDAG &DAG) const {
1860 return makeAddress(Op, DAG);
1863 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1864 SelectionDAG &DAG) const {
1865 return makeAddress(Op, DAG);
1868 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1869 SelectionDAG &DAG) const {
1871 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1873 const GlobalValue *GV = GA->getGlobal();
1874 EVT PtrVT = getPointerTy();
1876 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1878 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1879 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1880 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
1881 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
1882 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1883 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
1884 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
1885 unsigned addTF = ((model == TLSModel::GeneralDynamic)
1886 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
1887 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
1888 unsigned callTF = ((model == TLSModel::GeneralDynamic)
1889 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
1890 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
1892 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1893 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1894 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1895 withTargetFlags(Op, addTF, DAG));
1897 SDValue Chain = DAG.getEntryNode();
1900 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
1901 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1902 InFlag = Chain.getValue(1);
1903 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1904 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1907 SmallVector<SDValue, 4> Ops;
1908 Ops.push_back(Chain);
1909 Ops.push_back(Callee);
1910 Ops.push_back(Symbol);
1911 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1912 const uint32_t *Mask = getTargetMachine()
1913 .getRegisterInfo()->getCallPreservedMask(CallingConv::C);
1914 assert(Mask && "Missing call preserved mask for calling convention");
1915 Ops.push_back(DAG.getRegisterMask(Mask));
1916 Ops.push_back(InFlag);
1917 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size());
1918 InFlag = Chain.getValue(1);
1919 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
1920 DAG.getIntPtrConstant(0, true), InFlag, DL);
1921 InFlag = Chain.getValue(1);
1922 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1924 if (model != TLSModel::LocalDynamic)
1927 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1928 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
1929 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1930 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
1931 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1932 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1933 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
1936 if (model == TLSModel::InitialExec) {
1937 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
1938 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
1940 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1942 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1943 // function has calls.
1944 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1945 MFI->setHasCalls(true);
1947 SDValue TGA = makeHiLoPair(Op,
1948 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
1949 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
1950 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1951 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1953 withTargetFlags(Op, ldTF, DAG));
1954 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1955 DAG.getRegister(SP::G7, PtrVT), Offset,
1957 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
1960 assert(model == TLSModel::LocalExec);
1961 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1962 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
1963 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1964 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
1965 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1967 return DAG.getNode(ISD::ADD, DL, PtrVT,
1968 DAG.getRegister(SP::G7, PtrVT), Offset);
1972 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1973 SDValue Arg, SDLoc DL,
1974 SelectionDAG &DAG) const {
1975 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1976 EVT ArgVT = Arg.getValueType();
1977 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1983 if (ArgTy->isFP128Ty()) {
1984 // Create a stack object and pass the pointer to the library function.
1985 int FI = MFI->CreateStackObject(16, 8, false);
1986 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1987 Chain = DAG.getStore(Chain,
1991 MachinePointerInfo(),
1997 Entry.Ty = PointerType::getUnqual(ArgTy);
1999 Args.push_back(Entry);
2004 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2005 const char *LibFuncName,
2006 unsigned numArgs) const {
2010 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2012 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
2013 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2014 Type *RetTyABI = RetTy;
2015 SDValue Chain = DAG.getEntryNode();
2018 if (RetTy->isFP128Ty()) {
2019 // Create a Stack Object to receive the return value of type f128.
2021 int RetFI = MFI->CreateStackObject(16, 8, false);
2022 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
2023 Entry.Node = RetPtr;
2024 Entry.Ty = PointerType::getUnqual(RetTy);
2025 if (!Subtarget->is64Bit())
2026 Entry.isSRet = true;
2027 Entry.isReturned = false;
2028 Args.push_back(Entry);
2029 RetTyABI = Type::getVoidTy(*DAG.getContext());
2032 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2033 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2034 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2037 CallLoweringInfo CLI(Chain,
2039 false, false, false, false,
2042 Callee, Args, DAG, SDLoc(Op));
2043 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2045 // chain is in second result.
2046 if (RetTyABI == RetTy)
2047 return CallInfo.first;
2049 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2051 Chain = CallInfo.second;
2053 // Load RetPtr to get the return value.
2054 return DAG.getLoad(Op.getValueType(),
2058 MachinePointerInfo(),
2059 false, false, false, 8);
2063 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2066 SelectionDAG &DAG) const {
2068 const char *LibCall = 0;
2069 bool is64Bit = Subtarget->is64Bit();
2071 default: llvm_unreachable("Unhandled conditional code!");
2072 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2073 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2074 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2075 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2076 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2077 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2085 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2088 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
2089 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2091 SDValue Chain = DAG.getEntryNode();
2092 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2093 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2096 CallLoweringInfo CLI(Chain,
2098 false, false, false, false,
2101 Callee, Args, DAG, DL);
2103 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2105 // result is in first, and chain is in second result.
2106 SDValue Result = CallInfo.first;
2110 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2111 SPCC = SPCC::ICC_NE;
2112 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2114 case SPCC::FCC_UL : {
2115 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
2116 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2117 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2118 SPCC = SPCC::ICC_NE;
2119 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2121 case SPCC::FCC_ULE: {
2122 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
2123 SPCC = SPCC::ICC_NE;
2124 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2126 case SPCC::FCC_UG : {
2127 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2129 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2131 case SPCC::FCC_UGE: {
2132 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2133 SPCC = SPCC::ICC_NE;
2134 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2137 case SPCC::FCC_U : {
2138 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2140 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2142 case SPCC::FCC_O : {
2143 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2144 SPCC = SPCC::ICC_NE;
2145 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2147 case SPCC::FCC_LG : {
2148 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2149 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2150 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2151 SPCC = SPCC::ICC_NE;
2152 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2154 case SPCC::FCC_UE : {
2155 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2156 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2157 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2159 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2165 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2166 const SparcTargetLowering &TLI) {
2168 if (Op.getOperand(0).getValueType() == MVT::f64)
2169 return TLI.LowerF128Op(Op, DAG,
2170 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2172 if (Op.getOperand(0).getValueType() == MVT::f32)
2173 return TLI.LowerF128Op(Op, DAG,
2174 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2176 llvm_unreachable("fpextend with non-float operand!");
2177 return SDValue(0, 0);
2181 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2182 const SparcTargetLowering &TLI) {
2183 // FP_ROUND on f64 and f32 are legal.
2184 if (Op.getOperand(0).getValueType() != MVT::f128)
2187 if (Op.getValueType() == MVT::f64)
2188 return TLI.LowerF128Op(Op, DAG,
2189 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2190 if (Op.getValueType() == MVT::f32)
2191 return TLI.LowerF128Op(Op, DAG,
2192 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2194 llvm_unreachable("fpround to non-float!");
2195 return SDValue(0, 0);
2198 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2199 const SparcTargetLowering &TLI,
2202 EVT VT = Op.getValueType();
2203 assert(VT == MVT::i32 || VT == MVT::i64);
2205 // Expand f128 operations to fp128 abi calls.
2206 if (Op.getOperand(0).getValueType() == MVT::f128
2207 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2208 const char *libName = TLI.getLibcallName(VT == MVT::i32
2209 ? RTLIB::FPTOSINT_F128_I32
2210 : RTLIB::FPTOSINT_F128_I64);
2211 return TLI.LowerF128Op(Op, DAG, libName, 1);
2214 // Expand if the resulting type is illegal.
2215 if (!TLI.isTypeLegal(VT))
2216 return SDValue(0, 0);
2218 // Otherwise, Convert the fp value to integer in an FP register.
2220 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2222 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2224 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2227 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2228 const SparcTargetLowering &TLI,
2231 EVT OpVT = Op.getOperand(0).getValueType();
2232 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2234 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2236 // Expand f128 operations to fp128 ABI calls.
2237 if (Op.getValueType() == MVT::f128
2238 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2239 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2240 ? RTLIB::SINTTOFP_I32_F128
2241 : RTLIB::SINTTOFP_I64_F128);
2242 return TLI.LowerF128Op(Op, DAG, libName, 1);
2245 // Expand if the operand type is illegal.
2246 if (!TLI.isTypeLegal(OpVT))
2247 return SDValue(0, 0);
2249 // Otherwise, Convert the int value to FP in an FP register.
2250 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2251 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2252 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2255 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2256 const SparcTargetLowering &TLI,
2259 EVT VT = Op.getValueType();
2261 // Expand if it does not involve f128 or the target has support for
2262 // quad floating point instructions and the resulting type is legal.
2263 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2264 (hasHardQuad && TLI.isTypeLegal(VT)))
2265 return SDValue(0, 0);
2267 assert(VT == MVT::i32 || VT == MVT::i64);
2269 return TLI.LowerF128Op(Op, DAG,
2270 TLI.getLibcallName(VT == MVT::i32
2271 ? RTLIB::FPTOUINT_F128_I32
2272 : RTLIB::FPTOUINT_F128_I64),
2276 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2277 const SparcTargetLowering &TLI,
2280 EVT OpVT = Op.getOperand(0).getValueType();
2281 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2283 // Expand if it does not involve f128 or the target has support for
2284 // quad floating point instructions and the operand type is legal.
2285 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2286 return SDValue(0, 0);
2288 return TLI.LowerF128Op(Op, DAG,
2289 TLI.getLibcallName(OpVT == MVT::i32
2290 ? RTLIB::UINTTOFP_I32_F128
2291 : RTLIB::UINTTOFP_I64_F128),
2295 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2296 const SparcTargetLowering &TLI,
2298 SDValue Chain = Op.getOperand(0);
2299 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2300 SDValue LHS = Op.getOperand(2);
2301 SDValue RHS = Op.getOperand(3);
2302 SDValue Dest = Op.getOperand(4);
2304 unsigned Opc, SPCC = ~0U;
2306 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2307 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2308 LookThroughSetCC(LHS, RHS, CC, SPCC);
2310 // Get the condition flag.
2311 SDValue CompareFlag;
2312 if (LHS.getValueType().isInteger()) {
2313 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2314 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2315 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2316 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2318 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2319 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2320 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2323 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2324 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2328 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2329 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2332 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2333 const SparcTargetLowering &TLI,
2335 SDValue LHS = Op.getOperand(0);
2336 SDValue RHS = Op.getOperand(1);
2337 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2338 SDValue TrueVal = Op.getOperand(2);
2339 SDValue FalseVal = Op.getOperand(3);
2341 unsigned Opc, SPCC = ~0U;
2343 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2344 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2345 LookThroughSetCC(LHS, RHS, CC, SPCC);
2347 SDValue CompareFlag;
2348 if (LHS.getValueType().isInteger()) {
2349 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2350 Opc = LHS.getValueType() == MVT::i32 ?
2351 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2352 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2354 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2355 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2356 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2357 Opc = SPISD::SELECT_ICC;
2359 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2360 Opc = SPISD::SELECT_FCC;
2361 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2364 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2365 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2368 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2369 const SparcTargetLowering &TLI) {
2370 MachineFunction &MF = DAG.getMachineFunction();
2371 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2373 // Need frame address to find the address of VarArgsFrameIndex.
2374 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2376 // vastart just stores the address of the VarArgsFrameIndex slot into the
2377 // memory location argument.
2380 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2381 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2382 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2383 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2384 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2385 MachinePointerInfo(SV), false, false, 0);
2388 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2389 SDNode *Node = Op.getNode();
2390 EVT VT = Node->getValueType(0);
2391 SDValue InChain = Node->getOperand(0);
2392 SDValue VAListPtr = Node->getOperand(1);
2393 EVT PtrVT = VAListPtr.getValueType();
2394 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2396 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2397 MachinePointerInfo(SV), false, false, false, 0);
2398 // Increment the pointer, VAList, to the next vaarg.
2399 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2400 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2401 // Store the incremented VAList to the legalized pointer.
2402 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2403 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2404 // Load the actual argument out of the pointer VAList.
2405 // We can't count on greater alignment than the word size.
2406 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2407 false, false, false,
2408 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2411 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2412 const SparcSubtarget *Subtarget) {
2413 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2414 SDValue Size = Op.getOperand(1); // Legalize the size.
2415 EVT VT = Size->getValueType(0);
2418 unsigned SPReg = SP::O6;
2419 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2420 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2421 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2423 // The resultant pointer is actually 16 words from the bottom of the stack,
2424 // to provide a register spill area.
2425 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2426 regSpillArea += Subtarget->getStackPointerBias();
2428 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2429 DAG.getConstant(regSpillArea, VT));
2430 SDValue Ops[2] = { NewVal, Chain };
2431 return DAG.getMergeValues(Ops, 2, dl);
2435 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2437 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2438 dl, MVT::Other, DAG.getEntryNode());
2442 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2443 const SparcSubtarget *Subtarget) {
2444 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2445 MFI->setFrameAddressIsTaken(true);
2447 EVT VT = Op.getValueType();
2449 unsigned FrameReg = SP::I6;
2450 unsigned stackBias = Subtarget->getStackPointerBias();
2455 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2456 if (Subtarget->is64Bit())
2457 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2458 DAG.getIntPtrConstant(stackBias));
2462 // flush first to make sure the windowed registers' values are in stack
2463 SDValue Chain = getFLUSHW(Op, DAG);
2464 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2466 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2469 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2470 DAG.getIntPtrConstant(Offset));
2471 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2472 false, false, false, 0);
2474 if (Subtarget->is64Bit())
2475 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2476 DAG.getIntPtrConstant(stackBias));
2481 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2482 const SparcSubtarget *Subtarget) {
2484 uint64_t depth = Op.getConstantOperandVal(0);
2486 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2490 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2491 const SparcTargetLowering &TLI,
2492 const SparcSubtarget *Subtarget) {
2493 MachineFunction &MF = DAG.getMachineFunction();
2494 MachineFrameInfo *MFI = MF.getFrameInfo();
2495 MFI->setReturnAddressIsTaken(true);
2497 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2500 EVT VT = Op.getValueType();
2502 uint64_t depth = Op.getConstantOperandVal(0);
2506 unsigned RetReg = MF.addLiveIn(SP::I7,
2507 TLI.getRegClassFor(TLI.getPointerTy()));
2508 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2512 // Need frame address to find return address of the caller.
2513 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2515 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2516 SDValue Ptr = DAG.getNode(ISD::ADD,
2519 DAG.getIntPtrConstant(Offset));
2520 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2521 MachinePointerInfo(), false, false, false, 0);
2526 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2530 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2531 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2533 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2534 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2535 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2537 SDValue SrcReg64 = Op.getOperand(0);
2538 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2540 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2543 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2545 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2547 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2549 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2554 // Lower a f128 load into two f64 loads.
2555 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2558 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2559 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2560 && "Unexpected node type");
2562 unsigned alignment = LdNode->getAlignment();
2566 SDValue Hi64 = DAG.getLoad(MVT::f64,
2569 LdNode->getBasePtr(),
2570 LdNode->getPointerInfo(),
2571 false, false, false, alignment);
2572 EVT addrVT = LdNode->getBasePtr().getValueType();
2573 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2574 LdNode->getBasePtr(),
2575 DAG.getConstant(8, addrVT));
2576 SDValue Lo64 = DAG.getLoad(MVT::f64,
2580 LdNode->getPointerInfo(),
2581 false, false, false, alignment);
2583 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2584 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2586 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2588 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2590 SDValue(InFP128, 0),
2593 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2595 SDValue(InFP128, 0),
2598 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2599 SDValue(Lo64.getNode(), 1) };
2600 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2602 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2603 return DAG.getMergeValues(Ops, 2, dl);
2606 // Lower a f128 store into two f64 stores.
2607 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2609 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2610 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2611 && "Unexpected node type");
2612 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2613 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2615 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2620 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2626 unsigned alignment = StNode->getAlignment();
2630 SDValue OutChains[2];
2631 OutChains[0] = DAG.getStore(StNode->getChain(),
2634 StNode->getBasePtr(),
2635 MachinePointerInfo(),
2636 false, false, alignment);
2637 EVT addrVT = StNode->getBasePtr().getValueType();
2638 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2639 StNode->getBasePtr(),
2640 DAG.getConstant(8, addrVT));
2641 OutChains[1] = DAG.getStore(StNode->getChain(),
2645 MachinePointerInfo(),
2646 false, false, alignment);
2647 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2651 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
2652 const SparcTargetLowering &TLI,
2654 if (Op.getValueType() == MVT::f64)
2655 return LowerF64Op(Op, DAG, ISD::FNEG);
2656 if (Op.getValueType() == MVT::f128)
2657 return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
2661 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2662 if (Op.getValueType() == MVT::f64)
2663 return LowerF64Op(Op, DAG, ISD::FABS);
2664 if (Op.getValueType() != MVT::f128)
2667 // Lower fabs on f128 to fabs on f64
2668 // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
2671 SDValue SrcReg128 = Op.getOperand(0);
2672 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2674 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2677 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2679 Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
2681 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2683 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2685 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2690 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2692 if (Op.getValueType() != MVT::i64)
2696 SDValue Src1 = Op.getOperand(0);
2697 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2698 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2699 DAG.getConstant(32, MVT::i64));
2700 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2702 SDValue Src2 = Op.getOperand(1);
2703 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2704 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2705 DAG.getConstant(32, MVT::i64));
2706 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2709 bool hasChain = false;
2710 unsigned hiOpc = Op.getOpcode();
2711 switch (Op.getOpcode()) {
2712 default: llvm_unreachable("Invalid opcode");
2713 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2714 case ISD::ADDE: hasChain = true; break;
2715 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2716 case ISD::SUBE: hasChain = true; break;
2719 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2721 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2724 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2726 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2727 SDValue Carry = Hi.getValue(1);
2729 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2730 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2731 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2732 DAG.getConstant(32, MVT::i64));
2734 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2735 SDValue Ops[2] = { Dst, Carry };
2736 return DAG.getMergeValues(Ops, 2, dl);
2739 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2740 // in LegalizeDAG.cpp except the order of arguments to the library function.
2741 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2742 const SparcTargetLowering &TLI)
2744 unsigned opcode = Op.getOpcode();
2745 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2747 bool isSigned = (opcode == ISD::SMULO);
2749 EVT WideVT = MVT::i128;
2751 SDValue LHS = Op.getOperand(0);
2753 if (LHS.getValueType() != VT)
2756 SDValue ShiftAmt = DAG.getConstant(63, VT);
2758 SDValue RHS = Op.getOperand(1);
2759 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2760 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2761 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2763 SDValue MulResult = TLI.makeLibCall(DAG,
2764 RTLIB::MUL_I128, WideVT,
2765 Args, 4, isSigned, dl).first;
2766 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2767 MulResult, DAG.getIntPtrConstant(0));
2768 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2769 MulResult, DAG.getIntPtrConstant(1));
2771 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2772 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2774 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
2777 // MulResult is a node with an illegal type. Because such things are not
2778 // generally permitted during this phase of legalization, delete the
2779 // node. The above EXTRACT_ELEMENT nodes should have been folded.
2780 DAG.DeleteNode(MulResult.getNode());
2782 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2783 return DAG.getMergeValues(Ops, 2, dl);
2786 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2787 // Monotonic load/stores are legal.
2788 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2791 // Otherwise, expand with a fence.
2796 SDValue SparcTargetLowering::
2797 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2799 bool hasHardQuad = Subtarget->hasHardQuad();
2800 bool is64Bit = Subtarget->is64Bit();
2801 bool isV9 = Subtarget->isV9();
2803 switch (Op.getOpcode()) {
2804 default: llvm_unreachable("Should not custom lower this!");
2806 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2808 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2810 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2811 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2812 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2813 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2814 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2816 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2818 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2820 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2822 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2824 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2826 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2827 case ISD::VAARG: return LowerVAARG(Op, DAG);
2828 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2831 case ISD::LOAD: return LowerF128Load(Op, DAG);
2832 case ISD::STORE: return LowerF128Store(Op, DAG);
2833 case ISD::FADD: return LowerF128Op(Op, DAG,
2834 getLibcallName(RTLIB::ADD_F128), 2);
2835 case ISD::FSUB: return LowerF128Op(Op, DAG,
2836 getLibcallName(RTLIB::SUB_F128), 2);
2837 case ISD::FMUL: return LowerF128Op(Op, DAG,
2838 getLibcallName(RTLIB::MUL_F128), 2);
2839 case ISD::FDIV: return LowerF128Op(Op, DAG,
2840 getLibcallName(RTLIB::DIV_F128), 2);
2841 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2842 getLibcallName(RTLIB::SQRT_F128),1);
2843 case ISD::FNEG: return LowerFNEG(Op, DAG, *this, is64Bit);
2844 case ISD::FABS: return LowerFABS(Op, DAG, isV9);
2845 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2846 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2850 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2852 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2853 case ISD::ATOMIC_LOAD:
2854 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2859 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2860 MachineBasicBlock *BB) const {
2861 switch (MI->getOpcode()) {
2862 default: llvm_unreachable("Unknown SELECT_CC!");
2863 case SP::SELECT_CC_Int_ICC:
2864 case SP::SELECT_CC_FP_ICC:
2865 case SP::SELECT_CC_DFP_ICC:
2866 case SP::SELECT_CC_QFP_ICC:
2867 return expandSelectCC(MI, BB, SP::BCOND);
2868 case SP::SELECT_CC_Int_FCC:
2869 case SP::SELECT_CC_FP_FCC:
2870 case SP::SELECT_CC_DFP_FCC:
2871 case SP::SELECT_CC_QFP_FCC:
2872 return expandSelectCC(MI, BB, SP::FBCOND);
2874 case SP::ATOMIC_LOAD_ADD_32:
2875 return expandAtomicRMW(MI, BB, SP::ADDrr);
2876 case SP::ATOMIC_LOAD_ADD_64:
2877 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2878 case SP::ATOMIC_LOAD_SUB_32:
2879 return expandAtomicRMW(MI, BB, SP::SUBrr);
2880 case SP::ATOMIC_LOAD_SUB_64:
2881 return expandAtomicRMW(MI, BB, SP::SUBXrr);
2882 case SP::ATOMIC_LOAD_AND_32:
2883 return expandAtomicRMW(MI, BB, SP::ANDrr);
2884 case SP::ATOMIC_LOAD_AND_64:
2885 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2886 case SP::ATOMIC_LOAD_OR_32:
2887 return expandAtomicRMW(MI, BB, SP::ORrr);
2888 case SP::ATOMIC_LOAD_OR_64:
2889 return expandAtomicRMW(MI, BB, SP::ORXrr);
2890 case SP::ATOMIC_LOAD_XOR_32:
2891 return expandAtomicRMW(MI, BB, SP::XORrr);
2892 case SP::ATOMIC_LOAD_XOR_64:
2893 return expandAtomicRMW(MI, BB, SP::XORXrr);
2894 case SP::ATOMIC_LOAD_NAND_32:
2895 return expandAtomicRMW(MI, BB, SP::ANDrr);
2896 case SP::ATOMIC_LOAD_NAND_64:
2897 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2899 case SP::ATOMIC_SWAP_64:
2900 return expandAtomicRMW(MI, BB, 0);
2902 case SP::ATOMIC_LOAD_MAX_32:
2903 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2904 case SP::ATOMIC_LOAD_MAX_64:
2905 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2906 case SP::ATOMIC_LOAD_MIN_32:
2907 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2908 case SP::ATOMIC_LOAD_MIN_64:
2909 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2910 case SP::ATOMIC_LOAD_UMAX_32:
2911 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2912 case SP::ATOMIC_LOAD_UMAX_64:
2913 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2914 case SP::ATOMIC_LOAD_UMIN_32:
2915 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2916 case SP::ATOMIC_LOAD_UMIN_64:
2917 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2922 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
2923 MachineBasicBlock *BB,
2924 unsigned BROpcode) const {
2925 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2926 DebugLoc dl = MI->getDebugLoc();
2927 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2929 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2930 // control-flow pattern. The incoming instruction knows the destination vreg
2931 // to set, the condition code register to branch on, the true/false values to
2932 // select between, and a branch opcode to use.
2933 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2934 MachineFunction::iterator It = BB;
2941 // fallthrough --> copy0MBB
2942 MachineBasicBlock *thisMBB = BB;
2943 MachineFunction *F = BB->getParent();
2944 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2945 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2946 F->insert(It, copy0MBB);
2947 F->insert(It, sinkMBB);
2949 // Transfer the remainder of BB and its successor edges to sinkMBB.
2950 sinkMBB->splice(sinkMBB->begin(), BB,
2951 llvm::next(MachineBasicBlock::iterator(MI)),
2953 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2955 // Add the true and fallthrough blocks as its successors.
2956 BB->addSuccessor(copy0MBB);
2957 BB->addSuccessor(sinkMBB);
2959 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2962 // %FalseValue = ...
2963 // # fallthrough to sinkMBB
2966 // Update machine-CFG edges
2967 BB->addSuccessor(sinkMBB);
2970 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2973 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2974 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2975 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2977 MI->eraseFromParent(); // The pseudo instruction is gone now.
2982 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
2983 MachineBasicBlock *MBB,
2985 unsigned CondCode) const {
2986 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2987 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2988 DebugLoc DL = MI->getDebugLoc();
2990 // MI is an atomic read-modify-write instruction of the form:
2992 // rd = atomicrmw<op> addr, rs2
2994 // All three operands are registers.
2995 unsigned DestReg = MI->getOperand(0).getReg();
2996 unsigned AddrReg = MI->getOperand(1).getReg();
2997 unsigned Rs2Reg = MI->getOperand(2).getReg();
2999 // SelectionDAG has already inserted memory barriers before and after MI, so
3000 // we simply have to implement the operatiuon in terms of compare-and-swap.
3002 // %val0 = load %addr
3004 // %val = phi %val0, %dest
3005 // %upd = op %val, %rs2
3006 // %dest = cas %addr, %val, %upd
3011 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
3012 const TargetRegisterClass *ValueRC =
3013 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
3014 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
3016 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3017 .addReg(AddrReg).addImm(0);
3019 // Split the basic block MBB before MI and insert the loop block in the hole.
3020 MachineFunction::iterator MFI = MBB;
3021 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3022 MachineFunction *MF = MBB->getParent();
3023 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3024 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3026 MF->insert(MFI, LoopMBB);
3027 MF->insert(MFI, DoneMBB);
3029 // Move MI and following instructions to DoneMBB.
3030 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3031 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3033 // Connect the CFG again.
3034 MBB->addSuccessor(LoopMBB);
3035 LoopMBB->addSuccessor(LoopMBB);
3036 LoopMBB->addSuccessor(DoneMBB);
3038 // Build the loop block.
3039 unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3040 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3041 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3043 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3044 .addReg(Val0Reg).addMBB(MBB)
3045 .addReg(DestReg).addMBB(LoopMBB);
3048 // This is one of the min/max operations. We need a CMPrr followed by a
3050 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3051 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3052 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3053 } else if (Opcode) {
3054 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3055 .addReg(ValReg).addReg(Rs2Reg);
3058 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3059 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3060 unsigned TmpReg = UpdReg;
3061 UpdReg = MRI.createVirtualRegister(ValueRC);
3062 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3065 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3066 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3067 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3068 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3069 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3070 .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3072 MI->eraseFromParent();
3076 //===----------------------------------------------------------------------===//
3077 // Sparc Inline Assembly Support
3078 //===----------------------------------------------------------------------===//
3080 /// getConstraintType - Given a constraint letter, return the type of
3081 /// constraint it is for this target.
3082 SparcTargetLowering::ConstraintType
3083 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
3084 if (Constraint.size() == 1) {
3085 switch (Constraint[0]) {
3087 case 'r': return C_RegisterClass;
3093 return TargetLowering::getConstraintType(Constraint);
3096 TargetLowering::ConstraintWeight SparcTargetLowering::
3097 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3098 const char *constraint) const {
3099 ConstraintWeight weight = CW_Invalid;
3100 Value *CallOperandVal = info.CallOperandVal;
3101 // If we don't have a value, we can't do a match,
3102 // but allow it at the lowest weight.
3103 if (CallOperandVal == NULL)
3106 // Look at the constraint type.
3107 switch (*constraint) {
3109 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3112 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3113 if (isInt<13>(C->getSExtValue()))
3114 weight = CW_Constant;
3121 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3122 /// vector. If it is invalid, don't add anything to Ops.
3123 void SparcTargetLowering::
3124 LowerAsmOperandForConstraint(SDValue Op,
3125 std::string &Constraint,
3126 std::vector<SDValue> &Ops,
3127 SelectionDAG &DAG) const {
3128 SDValue Result(0, 0);
3130 // Only support length 1 constraints for now.
3131 if (Constraint.length() > 1)
3134 char ConstraintLetter = Constraint[0];
3135 switch (ConstraintLetter) {
3138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3139 if (isInt<13>(C->getSExtValue())) {
3140 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
3147 if (Result.getNode()) {
3148 Ops.push_back(Result);
3151 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3154 std::pair<unsigned, const TargetRegisterClass*>
3155 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3157 if (Constraint.size() == 1) {
3158 switch (Constraint[0]) {
3160 return std::make_pair(0U, &SP::IntRegsRegClass);
3162 } else if (!Constraint.empty() && Constraint.size() <= 5
3163 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3164 // constraint = '{r<d>}'
3165 // Remove the braces from around the name.
3166 StringRef name(Constraint.data()+1, Constraint.size()-2);
3167 // Handle register aliases:
3172 uint64_t intVal = 0;
3173 if (name.substr(0, 1).equals("r")
3174 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3175 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3176 char regType = regTypes[intVal/8];
3177 char regIdx = '0' + (intVal % 8);
3178 char tmp[] = { '{', regType, regIdx, '}', 0 };
3179 std::string newConstraint = std::string(tmp);
3180 return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT);
3184 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3188 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3189 // The Sparc target isn't yet aware of offsets.
3193 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3194 SmallVectorImpl<SDValue>& Results,
3195 SelectionDAG &DAG) const {
3199 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3201 switch (N->getOpcode()) {
3203 llvm_unreachable("Do not know how to custom type legalize this operation!");
3205 case ISD::FP_TO_SINT:
3206 case ISD::FP_TO_UINT:
3207 // Custom lower only if it involves f128 or i64.
3208 if (N->getOperand(0).getValueType() != MVT::f128
3209 || N->getValueType(0) != MVT::i64)
3211 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3212 ? RTLIB::FPTOSINT_F128_I64
3213 : RTLIB::FPTOUINT_F128_I64);
3215 Results.push_back(LowerF128Op(SDValue(N, 0),
3217 getLibcallName(libCall),
3221 case ISD::SINT_TO_FP:
3222 case ISD::UINT_TO_FP:
3223 // Custom lower only if it involves f128 or i64.
3224 if (N->getValueType(0) != MVT::f128
3225 || N->getOperand(0).getValueType() != MVT::i64)
3228 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3229 ? RTLIB::SINTTOFP_I64_F128
3230 : RTLIB::UINTTOFP_I64_F128);
3232 Results.push_back(LowerF128Op(SDValue(N, 0),
3234 getLibcallName(libCall),