1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcTargetMachine.h"
18 #include "MCTargetDesc/SparcBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/Support/ErrorHandling.h"
33 //===----------------------------------------------------------------------===//
34 // Calling Convention Implementation
35 //===----------------------------------------------------------------------===//
37 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
38 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
39 ISD::ArgFlagsTy &ArgFlags, CCState &State)
41 assert (ArgFlags.isSRet());
43 //Assign SRet argument
44 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
50 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
51 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags, CCState &State)
54 static const uint16_t RegList[] = {
55 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
57 //Try to get first reg
58 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
59 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
61 //Assign whole thing in stack
62 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
63 State.AllocateStack(8,4),
68 //Try to get second reg
69 if (unsigned Reg = State.AllocateReg(RegList, 6))
70 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
72 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
73 State.AllocateStack(4,4),
78 // Allocate a full-sized argument for the 64-bit ABI.
79 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
80 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
82 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
83 "Can't handle non-64 bits locations");
85 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
86 unsigned Offset = State.AllocateStack(8, 8);
89 if (LocVT == MVT::i64 && Offset < 6*8)
90 // Promote integers to %i0-%i5.
91 Reg = SP::I0 + Offset/8;
92 else if (LocVT == MVT::f64 && Offset < 16*8)
93 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
94 Reg = SP::D0 + Offset/8;
95 else if (LocVT == MVT::f32 && Offset < 16*8)
96 // Promote floats to %f1, %f3, ...
97 Reg = SP::F1 + Offset/4;
99 // Promote to register when possible, otherwise use the stack slot.
101 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
105 // This argument goes on the stack in an 8-byte slot.
106 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
107 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
108 if (LocVT == MVT::f32)
111 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
115 // Allocate a half-sized argument for the 64-bit ABI.
117 // This is used when passing { float, int } structs by value in registers.
118 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
119 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
120 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
121 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
122 unsigned Offset = State.AllocateStack(4, 4);
124 if (LocVT == MVT::f32 && Offset < 16*8) {
125 // Promote floats to %f0-%f31.
126 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
131 if (LocVT == MVT::i32 && Offset < 6*8) {
132 // Promote integers to %i0-%i5, using half the register.
133 unsigned Reg = SP::I0 + Offset/8;
135 LocInfo = CCValAssign::AExt;
137 // Set the Custom bit if this i32 goes in the high bits of a register.
139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
142 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
146 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
150 #include "SparcGenCallingConv.inc"
152 // The calling conventions in SparcCallingConv.td are described in terms of the
153 // callee's register window. This function translates registers to the
154 // corresponding caller window %o register.
155 static unsigned toCallerWindow(unsigned Reg) {
156 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
157 if (Reg >= SP::I0 && Reg <= SP::I7)
158 return Reg - SP::I0 + SP::O0;
163 SparcTargetLowering::LowerReturn(SDValue Chain,
164 CallingConv::ID CallConv, bool IsVarArg,
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
166 const SmallVectorImpl<SDValue> &OutVals,
167 DebugLoc DL, SelectionDAG &DAG) const {
168 if (Subtarget->is64Bit())
169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
174 SparcTargetLowering::LowerReturn_32(SDValue Chain,
175 CallingConv::ID CallConv, bool IsVarArg,
176 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 const SmallVectorImpl<SDValue> &OutVals,
178 DebugLoc DL, SelectionDAG &DAG) const {
179 MachineFunction &MF = DAG.getMachineFunction();
181 // CCValAssign - represent the assignment of the return value to locations.
182 SmallVector<CCValAssign, 16> RVLocs;
184 // CCState - Info about the registers and stack slot.
185 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
186 DAG.getTarget(), RVLocs, *DAG.getContext());
188 // Analyze return values.
189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
192 SmallVector<SDValue, 4> RetOps(1, Chain);
193 // Make room for the return address offset.
194 RetOps.push_back(SDValue());
196 // Copy the result values into the output registers.
197 for (unsigned i = 0; i != RVLocs.size(); ++i) {
198 CCValAssign &VA = RVLocs[i];
199 assert(VA.isRegLoc() && "Can only return in registers!");
201 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
204 // Guarantee that all emitted copies are stuck together with flags.
205 Flag = Chain.getValue(1);
206 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
209 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot
210 // If the function returns a struct, copy the SRetReturnReg to I0
211 if (MF.getFunction()->hasStructRetAttr()) {
212 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
213 unsigned Reg = SFI->getSRetReturnReg();
215 llvm_unreachable("sret virtual register not created in the entry block");
216 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
217 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
218 Flag = Chain.getValue(1);
219 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
220 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
223 RetOps[0] = Chain; // Update chain.
224 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
226 // Add the flag if we have it.
228 RetOps.push_back(Flag);
230 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
231 &RetOps[0], RetOps.size());
234 // Lower return values for the 64-bit ABI.
235 // Return values are passed the exactly the same way as function arguments.
237 SparcTargetLowering::LowerReturn_64(SDValue Chain,
238 CallingConv::ID CallConv, bool IsVarArg,
239 const SmallVectorImpl<ISD::OutputArg> &Outs,
240 const SmallVectorImpl<SDValue> &OutVals,
241 DebugLoc DL, SelectionDAG &DAG) const {
242 // CCValAssign - represent the assignment of the return value to locations.
243 SmallVector<CCValAssign, 16> RVLocs;
245 // CCState - Info about the registers and stack slot.
246 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
247 DAG.getTarget(), RVLocs, *DAG.getContext());
249 // Analyze return values.
250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
253 SmallVector<SDValue, 4> RetOps(1, Chain);
255 // The second operand on the return instruction is the return address offset.
256 // The return address is always %i7+8 with the 64-bit ABI.
257 RetOps.push_back(DAG.getConstant(8, MVT::i32));
259 // Copy the result values into the output registers.
260 for (unsigned i = 0; i != RVLocs.size(); ++i) {
261 CCValAssign &VA = RVLocs[i];
262 assert(VA.isRegLoc() && "Can only return in registers!");
263 SDValue OutVal = OutVals[i];
265 // Integer return values must be sign or zero extended by the callee.
266 switch (VA.getLocInfo()) {
267 case CCValAssign::SExt:
268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
270 case CCValAssign::ZExt:
271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
273 case CCValAssign::AExt:
274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
279 // The custom bit on an i32 return value indicates that it should be passed
280 // in the high bits of the register.
281 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
282 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
283 DAG.getConstant(32, MVT::i32));
285 // The next value may go in the low bits of the same register.
286 // Handle both at once.
287 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
288 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
289 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
290 // Skip the next value, it's already done.
295 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
297 // Guarantee that all emitted copies are stuck together with flags.
298 Flag = Chain.getValue(1);
299 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
302 RetOps[0] = Chain; // Update chain.
304 // Add the flag if we have it.
306 RetOps.push_back(Flag);
308 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
309 &RetOps[0], RetOps.size());
312 SDValue SparcTargetLowering::
313 LowerFormalArguments(SDValue Chain,
314 CallingConv::ID CallConv,
316 const SmallVectorImpl<ISD::InputArg> &Ins,
319 SmallVectorImpl<SDValue> &InVals) const {
320 if (Subtarget->is64Bit())
321 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
323 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
327 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
328 /// passed in either one or two GPRs, including FP values. TODO: we should
329 /// pass FP values in FP registers for fastcc functions.
330 SDValue SparcTargetLowering::
331 LowerFormalArguments_32(SDValue Chain,
332 CallingConv::ID CallConv,
334 const SmallVectorImpl<ISD::InputArg> &Ins,
337 SmallVectorImpl<SDValue> &InVals) const {
338 MachineFunction &MF = DAG.getMachineFunction();
339 MachineRegisterInfo &RegInfo = MF.getRegInfo();
340 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
342 // Assign locations to all of the incoming arguments.
343 SmallVector<CCValAssign, 16> ArgLocs;
344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
345 getTargetMachine(), ArgLocs, *DAG.getContext());
346 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
348 const unsigned StackOffset = 92;
350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
351 CCValAssign &VA = ArgLocs[i];
353 if (i == 0 && Ins[i].Flags.isSRet()) {
354 //Get SRet from [%fp+64]
355 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
356 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
357 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
358 MachinePointerInfo(),
359 false, false, false, 0);
360 InVals.push_back(Arg);
365 if (VA.needsCustom()) {
366 assert(VA.getLocVT() == MVT::f64);
367 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
368 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
369 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
372 CCValAssign &NextVA = ArgLocs[++i];
375 if (NextVA.isMemLoc()) {
376 int FrameIdx = MF.getFrameInfo()->
377 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
378 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
379 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
380 MachinePointerInfo(),
381 false, false, false, 0);
383 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
384 &SP::IntRegsRegClass);
385 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
388 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
389 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
390 InVals.push_back(WholeValue);
393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
395 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
396 if (VA.getLocVT() == MVT::f32)
397 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
398 else if (VA.getLocVT() != MVT::i32) {
399 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
400 DAG.getValueType(VA.getLocVT()));
401 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
403 InVals.push_back(Arg);
407 assert(VA.isMemLoc());
409 unsigned Offset = VA.getLocMemOffset()+StackOffset;
411 if (VA.needsCustom()) {
412 assert(VA.getValVT() == MVT::f64);
413 //If it is double-word aligned, just load.
414 if (Offset % 8 == 0) {
415 int FI = MF.getFrameInfo()->CreateFixedObject(8,
418 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
419 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
420 MachinePointerInfo(),
421 false,false, false, 0);
422 InVals.push_back(Load);
426 int FI = MF.getFrameInfo()->CreateFixedObject(4,
429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
430 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
431 MachinePointerInfo(),
432 false, false, false, 0);
433 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
436 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
438 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
439 MachinePointerInfo(),
440 false, false, false, 0);
443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
444 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
445 InVals.push_back(WholeValue);
449 int FI = MF.getFrameInfo()->CreateFixedObject(4,
452 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
454 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
455 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
456 MachinePointerInfo(),
457 false, false, false, 0);
459 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
460 // Sparc is big endian, so add an offset based on the ObjectVT.
461 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
462 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
463 DAG.getConstant(Offset, MVT::i32));
464 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
465 MachinePointerInfo(),
466 VA.getValVT(), false, false,0);
467 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
469 InVals.push_back(Load);
472 if (MF.getFunction()->hasStructRetAttr()) {
473 //Copy the SRet Argument to SRetReturnReg
474 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
475 unsigned Reg = SFI->getSRetReturnReg();
477 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
478 SFI->setSRetReturnReg(Reg);
480 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
481 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
484 // Store remaining ArgRegs to the stack if this is a varargs function.
486 static const uint16_t ArgRegs[] = {
487 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
489 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
490 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
491 unsigned ArgOffset = CCInfo.getNextStackOffset();
492 if (NumAllocated == 6)
493 ArgOffset += StackOffset;
496 ArgOffset = 68+4*NumAllocated;
499 // Remember the vararg offset for the va_start implementation.
500 FuncInfo->setVarArgsFrameOffset(ArgOffset);
502 std::vector<SDValue> OutChains;
504 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
507 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
509 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
511 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
513 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
514 MachinePointerInfo(),
519 if (!OutChains.empty()) {
520 OutChains.push_back(Chain);
521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
522 &OutChains[0], OutChains.size());
529 // Lower formal arguments for the 64 bit ABI.
530 SDValue SparcTargetLowering::
531 LowerFormalArguments_64(SDValue Chain,
532 CallingConv::ID CallConv,
534 const SmallVectorImpl<ISD::InputArg> &Ins,
537 SmallVectorImpl<SDValue> &InVals) const {
538 MachineFunction &MF = DAG.getMachineFunction();
540 // Analyze arguments according to CC_Sparc64.
541 SmallVector<CCValAssign, 16> ArgLocs;
542 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
543 getTargetMachine(), ArgLocs, *DAG.getContext());
544 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
546 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
547 CCValAssign &VA = ArgLocs[i];
549 // This argument is passed in a register.
550 // All integer register arguments are promoted by the caller to i64.
552 // Create a virtual register for the promoted live-in value.
553 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
554 getRegClassFor(VA.getLocVT()));
555 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
557 // Get the high bits for i32 struct elements.
558 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
559 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
560 DAG.getConstant(32, MVT::i32));
562 // The caller promoted the argument, so insert an Assert?ext SDNode so we
563 // won't promote the value again in this function.
564 switch (VA.getLocInfo()) {
565 case CCValAssign::SExt:
566 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
567 DAG.getValueType(VA.getValVT()));
569 case CCValAssign::ZExt:
570 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
571 DAG.getValueType(VA.getValVT()));
577 // Truncate the register down to the argument type.
579 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
581 InVals.push_back(Arg);
585 // The registers are exhausted. This argument was passed on the stack.
586 assert(VA.isMemLoc());
587 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
588 // beginning of the arguments area at %fp+BIAS+128.
589 unsigned Offset = VA.getLocMemOffset() + 128;
590 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
591 // Adjust offset for extended arguments, SPARC is big-endian.
592 // The caller will have written the full slot with extended bytes, but we
593 // prefer our own extending loads.
595 Offset += 8 - ValSize;
596 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
597 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
598 DAG.getFrameIndex(FI, getPointerTy()),
599 MachinePointerInfo::getFixedStack(FI),
600 false, false, false, 0));
606 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
607 SmallVectorImpl<SDValue> &InVals) const {
608 if (Subtarget->is64Bit())
609 return LowerCall_64(CLI, InVals);
610 return LowerCall_32(CLI, InVals);
613 // Lower a call for the 32-bit ABI.
615 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
616 SmallVectorImpl<SDValue> &InVals) const {
617 SelectionDAG &DAG = CLI.DAG;
618 DebugLoc &dl = CLI.DL;
619 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
620 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
621 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
622 SDValue Chain = CLI.Chain;
623 SDValue Callee = CLI.Callee;
624 bool &isTailCall = CLI.IsTailCall;
625 CallingConv::ID CallConv = CLI.CallConv;
626 bool isVarArg = CLI.IsVarArg;
628 // Sparc target does not yet support tail call optimization.
631 // Analyze operands of the call, assigning locations to each operand.
632 SmallVector<CCValAssign, 16> ArgLocs;
633 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
634 DAG.getTarget(), ArgLocs, *DAG.getContext());
635 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
637 // Get the size of the outgoing arguments stack space requirement.
638 unsigned ArgsSize = CCInfo.getNextStackOffset();
640 // Keep stack frames 8-byte aligned.
641 ArgsSize = (ArgsSize+7) & ~7;
643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
645 //Create local copies for byval args.
646 SmallVector<SDValue, 8> ByValArgs;
647 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
648 ISD::ArgFlagsTy Flags = Outs[i].Flags;
649 if (!Flags.isByVal())
652 SDValue Arg = OutVals[i];
653 unsigned Size = Flags.getByValSize();
654 unsigned Align = Flags.getByValAlign();
656 int FI = MFI->CreateStackObject(Size, Align, false);
657 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
658 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
660 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
662 (Size <= 32), //AlwaysInline if size <= 32
663 MachinePointerInfo(), MachinePointerInfo());
664 ByValArgs.push_back(FIPtr);
667 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
669 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
670 SmallVector<SDValue, 8> MemOpChains;
672 const unsigned StackOffset = 92;
673 bool hasStructRetAttr = false;
674 // Walk the register/memloc assignments, inserting copies/loads.
675 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
678 CCValAssign &VA = ArgLocs[i];
679 SDValue Arg = OutVals[realArgIdx];
681 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
683 //Use local copy if it is a byval arg.
685 Arg = ByValArgs[byvalArgIdx++];
687 // Promote the value if needed.
688 switch (VA.getLocInfo()) {
689 default: llvm_unreachable("Unknown loc info!");
690 case CCValAssign::Full: break;
691 case CCValAssign::SExt:
692 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
694 case CCValAssign::ZExt:
695 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
697 case CCValAssign::AExt:
698 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
700 case CCValAssign::BCvt:
701 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
705 if (Flags.isSRet()) {
706 assert(VA.needsCustom());
707 // store SRet argument in %sp+64
708 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
709 SDValue PtrOff = DAG.getIntPtrConstant(64);
710 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
711 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
712 MachinePointerInfo(),
714 hasStructRetAttr = true;
718 if (VA.needsCustom()) {
719 assert(VA.getLocVT() == MVT::f64);
722 unsigned Offset = VA.getLocMemOffset() + StackOffset;
723 //if it is double-word aligned, just store.
724 if (Offset % 8 == 0) {
725 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
726 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
727 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
728 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
729 MachinePointerInfo(),
735 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
736 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
737 Arg, StackPtr, MachinePointerInfo(),
739 // Sparc is big-endian, so the high part comes first.
740 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
741 MachinePointerInfo(), false, false, false, 0);
742 // Increment the pointer to the other half.
743 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
744 DAG.getIntPtrConstant(4));
745 // Load the low part.
746 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
747 MachinePointerInfo(), false, false, false, 0);
750 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
752 CCValAssign &NextVA = ArgLocs[++i];
753 if (NextVA.isRegLoc()) {
754 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
756 //Store the low part in stack.
757 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
758 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
759 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
760 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
761 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
762 MachinePointerInfo(),
766 unsigned Offset = VA.getLocMemOffset() + StackOffset;
767 // Store the high part.
768 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
769 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
770 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
771 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
772 MachinePointerInfo(),
774 // Store the low part.
775 PtrOff = DAG.getIntPtrConstant(Offset+4);
776 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
777 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
778 MachinePointerInfo(),
784 // Arguments that can be passed on register must be kept at
787 if (VA.getLocVT() != MVT::f32) {
788 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
791 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
792 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
796 assert(VA.isMemLoc());
798 // Create a store off the stack pointer for this argument.
799 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
800 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
801 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
802 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
803 MachinePointerInfo(),
808 // Emit all stores, make sure the occur before any copies into physregs.
809 if (!MemOpChains.empty())
810 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
811 &MemOpChains[0], MemOpChains.size());
813 // Build a sequence of copy-to-reg nodes chained together with token
814 // chain and flag operands which copy the outgoing args into registers.
815 // The InFlag in necessary since all emitted instructions must be
818 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
819 unsigned Reg = toCallerWindow(RegsToPass[i].first);
820 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
821 InFlag = Chain.getValue(1);
824 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
826 // If the callee is a GlobalAddress node (quite common, every direct call is)
827 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
828 // Likewise ExternalSymbol -> TargetExternalSymbol.
829 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
830 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
831 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
832 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
834 // Returns a chain & a flag for retval copy to use
835 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
836 SmallVector<SDValue, 8> Ops;
837 Ops.push_back(Chain);
838 Ops.push_back(Callee);
839 if (hasStructRetAttr)
840 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
841 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
842 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
843 RegsToPass[i].second.getValueType()));
844 if (InFlag.getNode())
845 Ops.push_back(InFlag);
847 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
848 InFlag = Chain.getValue(1);
850 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
851 DAG.getIntPtrConstant(0, true), InFlag);
852 InFlag = Chain.getValue(1);
854 // Assign locations to each value returned by this call.
855 SmallVector<CCValAssign, 16> RVLocs;
856 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
857 DAG.getTarget(), RVLocs, *DAG.getContext());
859 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
861 // Copy all of the result registers out of their specified physreg.
862 for (unsigned i = 0; i != RVLocs.size(); ++i) {
863 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
864 RVLocs[i].getValVT(), InFlag).getValue(1);
865 InFlag = Chain.getValue(2);
866 InVals.push_back(Chain.getValue(0));
873 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
875 const Function *CalleeFn = 0;
876 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
877 CalleeFn = dyn_cast<Function>(G->getGlobal());
878 } else if (ExternalSymbolSDNode *E =
879 dyn_cast<ExternalSymbolSDNode>(Callee)) {
880 const Function *Fn = DAG.getMachineFunction().getFunction();
881 const Module *M = Fn->getParent();
882 CalleeFn = M->getFunction(E->getSymbol());
888 assert(CalleeFn->hasStructRetAttr() &&
889 "Callee does not have the StructRet attribute.");
891 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
892 Type *ElementTy = Ty->getElementType();
893 return getDataLayout()->getTypeAllocSize(ElementTy);
896 // Lower a call for the 64-bit ABI.
898 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
899 SmallVectorImpl<SDValue> &InVals) const {
900 SelectionDAG &DAG = CLI.DAG;
901 DebugLoc DL = CLI.DL;
902 SDValue Chain = CLI.Chain;
904 // Analyze operands of the call, assigning locations to each operand.
905 SmallVector<CCValAssign, 16> ArgLocs;
906 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
907 DAG.getTarget(), ArgLocs, *DAG.getContext());
908 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
910 // Get the size of the outgoing arguments stack space requirement.
911 // The stack offset computed by CC_Sparc64 includes all arguments.
912 // Called functions expect 6 argument words to exist in the stack frame, used
914 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
916 // Keep stack frames 16-byte aligned.
917 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
919 // Adjust the stack pointer to make room for the arguments.
920 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
921 // with more than 6 arguments.
922 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
924 // Collect the set of registers to pass to the function and their values.
925 // This will be emitted as a sequence of CopyToReg nodes glued to the call
927 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
929 // Collect chains from all the memory opeations that copy arguments to the
930 // stack. They must follow the stack pointer adjustment above and precede the
931 // call instruction itself.
932 SmallVector<SDValue, 8> MemOpChains;
934 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
935 const CCValAssign &VA = ArgLocs[i];
936 SDValue Arg = CLI.OutVals[i];
938 // Promote the value if needed.
939 switch (VA.getLocInfo()) {
941 llvm_unreachable("Unknown location info!");
942 case CCValAssign::Full:
944 case CCValAssign::SExt:
945 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
947 case CCValAssign::ZExt:
948 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
950 case CCValAssign::AExt:
951 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
953 case CCValAssign::BCvt:
954 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
959 // The custom bit on an i32 return value indicates that it should be
960 // passed in the high bits of the register.
961 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
962 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
963 DAG.getConstant(32, MVT::i32));
965 // The next value may go in the low bits of the same register.
966 // Handle both at once.
967 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
968 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
969 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
971 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
972 // Skip the next value, it's already done.
976 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
980 assert(VA.isMemLoc());
982 // Create a store off the stack pointer for this argument.
983 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
984 // The argument area starts at %fp+BIAS+128 in the callee frame,
985 // %sp+BIAS+128 in ours.
986 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
987 Subtarget->getStackPointerBias() +
989 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
990 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
991 MachinePointerInfo(),
995 // Emit all stores, make sure they occur before the call.
996 if (!MemOpChains.empty())
997 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
998 &MemOpChains[0], MemOpChains.size());
1000 // Build a sequence of CopyToReg nodes glued together with token chain and
1001 // glue operands which copy the outgoing args into registers. The InGlue is
1002 // necessary since all emitted instructions must be stuck together in order
1003 // to pass the live physical registers.
1005 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1006 Chain = DAG.getCopyToReg(Chain, DL,
1007 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1008 InGlue = Chain.getValue(1);
1011 // If the callee is a GlobalAddress node (quite common, every direct call is)
1012 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1013 // Likewise ExternalSymbol -> TargetExternalSymbol.
1014 SDValue Callee = CLI.Callee;
1015 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1016 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy());
1017 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1018 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
1020 // Build the operands for the call instruction itself.
1021 SmallVector<SDValue, 8> Ops;
1022 Ops.push_back(Chain);
1023 Ops.push_back(Callee);
1024 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1025 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1026 RegsToPass[i].second.getValueType()));
1028 // Make sure the CopyToReg nodes are glued to the call instruction which
1029 // consumes the registers.
1030 if (InGlue.getNode())
1031 Ops.push_back(InGlue);
1033 // Now the call itself.
1034 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1035 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
1036 InGlue = Chain.getValue(1);
1038 // Revert the stack pointer immediately after the call.
1039 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1040 DAG.getIntPtrConstant(0, true), InGlue);
1041 InGlue = Chain.getValue(1);
1043 // Now extract the return values. This is more or less the same as
1044 // LowerFormalArguments_64.
1046 // Assign locations to each value returned by this call.
1047 SmallVector<CCValAssign, 16> RVLocs;
1048 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1049 DAG.getTarget(), RVLocs, *DAG.getContext());
1050 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
1052 // Copy all of the result registers out of their specified physreg.
1053 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1054 CCValAssign &VA = RVLocs[i];
1055 unsigned Reg = toCallerWindow(VA.getLocReg());
1057 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1058 // reside in the same register in the high and low bits. Reuse the
1059 // CopyFromReg previous node to avoid duplicate copies.
1061 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1062 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1063 RV = Chain.getValue(0);
1065 // But usually we'll create a new CopyFromReg for a different register.
1066 if (!RV.getNode()) {
1067 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1068 Chain = RV.getValue(1);
1069 InGlue = Chain.getValue(2);
1072 // Get the high bits for i32 struct elements.
1073 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1074 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1075 DAG.getConstant(32, MVT::i32));
1077 // The callee promoted the return value, so insert an Assert?ext SDNode so
1078 // we won't promote the value again in this function.
1079 switch (VA.getLocInfo()) {
1080 case CCValAssign::SExt:
1081 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1082 DAG.getValueType(VA.getValVT()));
1084 case CCValAssign::ZExt:
1085 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1086 DAG.getValueType(VA.getValVT()));
1092 // Truncate the register down to the return value type.
1093 if (VA.isExtInLoc())
1094 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1096 InVals.push_back(RV);
1102 //===----------------------------------------------------------------------===//
1103 // TargetLowering Implementation
1104 //===----------------------------------------------------------------------===//
1106 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1108 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1110 default: llvm_unreachable("Unknown integer condition code!");
1111 case ISD::SETEQ: return SPCC::ICC_E;
1112 case ISD::SETNE: return SPCC::ICC_NE;
1113 case ISD::SETLT: return SPCC::ICC_L;
1114 case ISD::SETGT: return SPCC::ICC_G;
1115 case ISD::SETLE: return SPCC::ICC_LE;
1116 case ISD::SETGE: return SPCC::ICC_GE;
1117 case ISD::SETULT: return SPCC::ICC_CS;
1118 case ISD::SETULE: return SPCC::ICC_LEU;
1119 case ISD::SETUGT: return SPCC::ICC_GU;
1120 case ISD::SETUGE: return SPCC::ICC_CC;
1124 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1126 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1128 default: llvm_unreachable("Unknown fp condition code!");
1130 case ISD::SETOEQ: return SPCC::FCC_E;
1132 case ISD::SETUNE: return SPCC::FCC_NE;
1134 case ISD::SETOLT: return SPCC::FCC_L;
1136 case ISD::SETOGT: return SPCC::FCC_G;
1138 case ISD::SETOLE: return SPCC::FCC_LE;
1140 case ISD::SETOGE: return SPCC::FCC_GE;
1141 case ISD::SETULT: return SPCC::FCC_UL;
1142 case ISD::SETULE: return SPCC::FCC_ULE;
1143 case ISD::SETUGT: return SPCC::FCC_UG;
1144 case ISD::SETUGE: return SPCC::FCC_UGE;
1145 case ISD::SETUO: return SPCC::FCC_U;
1146 case ISD::SETO: return SPCC::FCC_O;
1147 case ISD::SETONE: return SPCC::FCC_LG;
1148 case ISD::SETUEQ: return SPCC::FCC_UE;
1152 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1153 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
1154 Subtarget = &TM.getSubtarget<SparcSubtarget>();
1156 // Set up the register classes.
1157 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1158 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1159 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1160 if (Subtarget->is64Bit())
1161 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1163 // Turn FP extload into load/fextend
1164 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1165 // Sparc doesn't have i1 sign extending load
1166 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1167 // Turn FP truncstore into trunc + store.
1168 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1170 // Custom legalize GlobalAddress nodes into LO/HI parts.
1171 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1172 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1173 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1175 // Sparc doesn't have sext_inreg, replace them with shl/sra
1176 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1177 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1178 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1180 // Sparc has no REM or DIVREM operations.
1181 setOperationAction(ISD::UREM, MVT::i32, Expand);
1182 setOperationAction(ISD::SREM, MVT::i32, Expand);
1183 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1184 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1186 // Custom expand fp<->sint
1187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1188 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1191 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1194 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1195 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1197 // Sparc has no select or setcc: expand to SELECT_CC.
1198 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1199 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1200 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1201 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1202 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1203 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1205 // Sparc doesn't have BRCOND either, it has BR_CC.
1206 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1207 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1208 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1209 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1210 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1211 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1213 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1214 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1215 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1217 if (Subtarget->is64Bit()) {
1218 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1219 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1222 // FIXME: There are instructions available for ATOMIC_FENCE
1223 // on SparcV8 and later.
1224 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
1225 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
1227 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1228 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1229 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1230 setOperationAction(ISD::FREM , MVT::f64, Expand);
1231 setOperationAction(ISD::FMA , MVT::f64, Expand);
1232 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1233 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1234 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1235 setOperationAction(ISD::FREM , MVT::f32, Expand);
1236 setOperationAction(ISD::FMA , MVT::f32, Expand);
1237 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1238 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1239 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1240 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1241 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1242 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1243 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1244 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1245 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1246 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1247 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1248 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1250 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1251 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1252 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1254 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1255 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1256 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1258 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
1260 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1261 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1262 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1263 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1265 // Use the default implementation.
1266 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1267 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1268 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1269 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1270 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1272 // No debug info support yet.
1273 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
1275 setStackPointerRegisterToSaveRestore(SP::O6);
1277 if (TM.getSubtarget<SparcSubtarget>().isV9())
1278 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1280 setMinFunctionAlignment(2);
1282 computeRegisterProperties();
1285 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1288 case SPISD::CMPICC: return "SPISD::CMPICC";
1289 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1290 case SPISD::BRICC: return "SPISD::BRICC";
1291 case SPISD::BRXCC: return "SPISD::BRXCC";
1292 case SPISD::BRFCC: return "SPISD::BRFCC";
1293 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1294 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1295 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1296 case SPISD::Hi: return "SPISD::Hi";
1297 case SPISD::Lo: return "SPISD::Lo";
1298 case SPISD::FTOI: return "SPISD::FTOI";
1299 case SPISD::ITOF: return "SPISD::ITOF";
1300 case SPISD::CALL: return "SPISD::CALL";
1301 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1302 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1303 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1307 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1308 /// be zero. Op is expected to be a target specific node. Used by DAG
1310 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1313 const SelectionDAG &DAG,
1314 unsigned Depth) const {
1315 APInt KnownZero2, KnownOne2;
1316 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1318 switch (Op.getOpcode()) {
1320 case SPISD::SELECT_ICC:
1321 case SPISD::SELECT_XCC:
1322 case SPISD::SELECT_FCC:
1323 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1324 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1325 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1326 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1328 // Only known if known in both the LHS and RHS.
1329 KnownOne &= KnownOne2;
1330 KnownZero &= KnownZero2;
1335 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1336 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1337 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1338 ISD::CondCode CC, unsigned &SPCC) {
1339 if (isa<ConstantSDNode>(RHS) &&
1340 cast<ConstantSDNode>(RHS)->isNullValue() &&
1342 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1343 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1344 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1345 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1346 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1347 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1348 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1349 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1350 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1351 SDValue CMPCC = LHS.getOperand(3);
1352 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1353 LHS = CMPCC.getOperand(0);
1354 RHS = CMPCC.getOperand(1);
1358 // Convert to a target node and set target flags.
1359 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1360 SelectionDAG &DAG) const {
1361 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1362 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1364 GA->getValueType(0),
1365 GA->getOffset(), TF);
1367 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1368 return DAG.getTargetConstantPool(CP->getConstVal(),
1369 CP->getValueType(0),
1371 CP->getOffset(), TF);
1373 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1374 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1375 ES->getValueType(0), TF);
1377 llvm_unreachable("Unhandled address SDNode");
1380 // Split Op into high and low parts according to HiTF and LoTF.
1381 // Return an ADD node combining the parts.
1382 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1383 unsigned HiTF, unsigned LoTF,
1384 SelectionDAG &DAG) const {
1385 DebugLoc DL = Op.getDebugLoc();
1386 EVT VT = Op.getValueType();
1387 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1388 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1389 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1392 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1393 // or ExternalSymbol SDNode.
1394 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1395 DebugLoc DL = Op.getDebugLoc();
1396 EVT VT = getPointerTy();
1398 // Handle PIC mode first.
1399 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1400 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1401 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1402 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1403 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1404 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1405 MachinePointerInfo::getGOT(), false, false, false, 0);
1408 // This is one of the absolute code models.
1409 switch(getTargetMachine().getCodeModel()) {
1411 llvm_unreachable("Unsupported absolute code model");
1412 case CodeModel::Small:
1413 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1414 case CodeModel::Medium: {
1415 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
1416 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getIntPtrConstant(12));
1417 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
1418 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1419 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1424 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1425 SelectionDAG &DAG) const {
1426 return makeAddress(Op, DAG);
1429 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1430 SelectionDAG &DAG) const {
1431 return makeAddress(Op, DAG);
1434 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1435 DebugLoc dl = Op.getDebugLoc();
1436 // Convert the fp value to integer in an FP register.
1437 assert(Op.getValueType() == MVT::i32);
1438 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
1439 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
1442 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1443 DebugLoc dl = Op.getDebugLoc();
1444 assert(Op.getOperand(0).getValueType() == MVT::i32);
1445 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
1446 // Convert the int value to FP in an FP register.
1447 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
1450 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1451 SDValue Chain = Op.getOperand(0);
1452 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1453 SDValue LHS = Op.getOperand(2);
1454 SDValue RHS = Op.getOperand(3);
1455 SDValue Dest = Op.getOperand(4);
1456 DebugLoc dl = Op.getDebugLoc();
1457 unsigned Opc, SPCC = ~0U;
1459 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1460 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1461 LookThroughSetCC(LHS, RHS, CC, SPCC);
1463 // Get the condition flag.
1464 SDValue CompareFlag;
1465 if (LHS.getValueType().isInteger()) {
1466 EVT VTs[] = { LHS.getValueType(), MVT::Glue };
1467 SDValue Ops[2] = { LHS, RHS };
1468 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
1469 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1470 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
1471 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
1473 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1474 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1477 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
1478 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1481 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1482 SDValue LHS = Op.getOperand(0);
1483 SDValue RHS = Op.getOperand(1);
1484 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1485 SDValue TrueVal = Op.getOperand(2);
1486 SDValue FalseVal = Op.getOperand(3);
1487 DebugLoc dl = Op.getDebugLoc();
1488 unsigned Opc, SPCC = ~0U;
1490 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1491 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1492 LookThroughSetCC(LHS, RHS, CC, SPCC);
1494 SDValue CompareFlag;
1495 if (LHS.getValueType().isInteger()) {
1496 // subcc returns a value
1497 EVT VTs[] = { LHS.getValueType(), MVT::Glue };
1498 SDValue Ops[2] = { LHS, RHS };
1499 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
1500 Opc = LHS.getValueType() == MVT::i32 ?
1501 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
1502 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1504 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1505 Opc = SPISD::SELECT_FCC;
1506 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1508 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
1509 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1512 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1513 const SparcTargetLowering &TLI) {
1514 MachineFunction &MF = DAG.getMachineFunction();
1515 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1517 // vastart just stores the address of the VarArgsFrameIndex slot into the
1518 // memory location argument.
1519 DebugLoc dl = Op.getDebugLoc();
1521 DAG.getNode(ISD::ADD, dl, MVT::i32,
1522 DAG.getRegister(SP::I6, MVT::i32),
1523 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
1525 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1526 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
1527 MachinePointerInfo(SV), false, false, 0);
1530 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
1531 SDNode *Node = Op.getNode();
1532 EVT VT = Node->getValueType(0);
1533 SDValue InChain = Node->getOperand(0);
1534 SDValue VAListPtr = Node->getOperand(1);
1535 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1536 DebugLoc dl = Node->getDebugLoc();
1537 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
1538 MachinePointerInfo(SV), false, false, false, 0);
1539 // Increment the pointer, VAList, to the next vaarg
1540 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
1541 DAG.getConstant(VT.getSizeInBits()/8,
1543 // Store the incremented VAList to the legalized pointer
1544 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
1545 VAListPtr, MachinePointerInfo(SV), false, false, 0);
1546 // Load the actual argument out of the pointer VAList, unless this is an
1549 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
1550 false, false, false, 0);
1552 // Otherwise, load it as i64, then do a bitconvert.
1553 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
1554 false, false, false, 0);
1556 // Bit-Convert the value to f64.
1558 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
1561 return DAG.getMergeValues(Ops, 2, dl);
1564 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1565 SDValue Chain = Op.getOperand(0); // Legalize the chain.
1566 SDValue Size = Op.getOperand(1); // Legalize the size.
1567 DebugLoc dl = Op.getDebugLoc();
1569 unsigned SPReg = SP::O6;
1570 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
1571 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
1572 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
1574 // The resultant pointer is actually 16 words from the bottom of the stack,
1575 // to provide a register spill area.
1576 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
1577 DAG.getConstant(96, MVT::i32));
1578 SDValue Ops[2] = { NewVal, Chain };
1579 return DAG.getMergeValues(Ops, 2, dl);
1583 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
1584 DebugLoc dl = Op.getDebugLoc();
1585 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
1586 dl, MVT::Other, DAG.getEntryNode());
1590 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1591 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1592 MFI->setFrameAddressIsTaken(true);
1594 EVT VT = Op.getValueType();
1595 DebugLoc dl = Op.getDebugLoc();
1596 unsigned FrameReg = SP::I6;
1598 uint64_t depth = Op.getConstantOperandVal(0);
1602 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1604 // flush first to make sure the windowed registers' values are in stack
1605 SDValue Chain = getFLUSHW(Op, DAG);
1606 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
1608 for (uint64_t i = 0; i != depth; ++i) {
1609 SDValue Ptr = DAG.getNode(ISD::ADD,
1611 FrameAddr, DAG.getIntPtrConstant(56));
1612 FrameAddr = DAG.getLoad(MVT::i32, dl,
1615 MachinePointerInfo(), false, false, false, 0);
1621 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
1622 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1623 MFI->setReturnAddressIsTaken(true);
1625 EVT VT = Op.getValueType();
1626 DebugLoc dl = Op.getDebugLoc();
1627 unsigned RetReg = SP::I7;
1629 uint64_t depth = Op.getConstantOperandVal(0);
1633 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
1635 // flush first to make sure the windowed registers' values are in stack
1636 SDValue Chain = getFLUSHW(Op, DAG);
1637 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
1639 for (uint64_t i = 0; i != depth; ++i) {
1640 SDValue Ptr = DAG.getNode(ISD::ADD,
1643 DAG.getIntPtrConstant((i == depth-1)?60:56));
1644 RetAddr = DAG.getLoad(MVT::i32, dl,
1647 MachinePointerInfo(), false, false, false, 0);
1653 SDValue SparcTargetLowering::
1654 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1655 switch (Op.getOpcode()) {
1656 default: llvm_unreachable("Should not custom lower this!");
1657 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1658 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1659 case ISD::GlobalTLSAddress:
1660 llvm_unreachable("TLS not implemented for Sparc.");
1661 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1662 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1663 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1664 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1665 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1666 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1667 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
1668 case ISD::VAARG: return LowerVAARG(Op, DAG);
1669 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1674 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1675 MachineBasicBlock *BB) const {
1676 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1679 DebugLoc dl = MI->getDebugLoc();
1680 // Figure out the conditional branch opcode to use for this select_cc.
1681 switch (MI->getOpcode()) {
1682 default: llvm_unreachable("Unknown SELECT_CC!");
1683 case SP::SELECT_CC_Int_ICC:
1684 case SP::SELECT_CC_FP_ICC:
1685 case SP::SELECT_CC_DFP_ICC:
1686 BROpcode = SP::BCOND;
1688 case SP::SELECT_CC_Int_FCC:
1689 case SP::SELECT_CC_FP_FCC:
1690 case SP::SELECT_CC_DFP_FCC:
1691 BROpcode = SP::FBCOND;
1695 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
1697 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1698 // control-flow pattern. The incoming instruction knows the destination vreg
1699 // to set, the condition code register to branch on, the true/false values to
1700 // select between, and a branch opcode to use.
1701 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1702 MachineFunction::iterator It = BB;
1709 // fallthrough --> copy0MBB
1710 MachineBasicBlock *thisMBB = BB;
1711 MachineFunction *F = BB->getParent();
1712 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1713 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1714 F->insert(It, copy0MBB);
1715 F->insert(It, sinkMBB);
1717 // Transfer the remainder of BB and its successor edges to sinkMBB.
1718 sinkMBB->splice(sinkMBB->begin(), BB,
1719 llvm::next(MachineBasicBlock::iterator(MI)),
1721 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1723 // Add the true and fallthrough blocks as its successors.
1724 BB->addSuccessor(copy0MBB);
1725 BB->addSuccessor(sinkMBB);
1727 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1730 // %FalseValue = ...
1731 // # fallthrough to sinkMBB
1734 // Update machine-CFG edges
1735 BB->addSuccessor(sinkMBB);
1738 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1741 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1742 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1743 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1745 MI->eraseFromParent(); // The pseudo instruction is gone now.
1749 //===----------------------------------------------------------------------===//
1750 // Sparc Inline Assembly Support
1751 //===----------------------------------------------------------------------===//
1753 /// getConstraintType - Given a constraint letter, return the type of
1754 /// constraint it is for this target.
1755 SparcTargetLowering::ConstraintType
1756 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1757 if (Constraint.size() == 1) {
1758 switch (Constraint[0]) {
1760 case 'r': return C_RegisterClass;
1764 return TargetLowering::getConstraintType(Constraint);
1767 std::pair<unsigned, const TargetRegisterClass*>
1768 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1770 if (Constraint.size() == 1) {
1771 switch (Constraint[0]) {
1773 return std::make_pair(0U, &SP::IntRegsRegClass);
1777 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1781 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1782 // The Sparc target isn't yet aware of offsets.