1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "MCTargetDesc/SparcMCExpr.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/ErrorHandling.h"
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags, CCState &State)
43 assert (ArgFlags.isSRet());
45 // Assign SRet argument.
46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags, CCState &State)
56 static const MCPhysReg RegList[] = {
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
63 // Assign whole thing in stack.
64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65 State.AllocateStack(8,4),
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75 State.AllocateStack(4,4),
80 // Allocate a full-sized argument for the 64-bit ABI.
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128
85 || LocVT.getSizeInBits() == 64) &&
86 "Can't handle non-64 bits locations");
88 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
91 unsigned Offset = State.AllocateStack(size, alignment);
94 if (LocVT == MVT::i64 && Offset < 6*8)
95 // Promote integers to %i0-%i5.
96 Reg = SP::I0 + Offset/8;
97 else if (LocVT == MVT::f64 && Offset < 16*8)
98 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
99 Reg = SP::D0 + Offset/8;
100 else if (LocVT == MVT::f32 && Offset < 16*8)
101 // Promote floats to %f1, %f3, ...
102 Reg = SP::F1 + Offset/4;
103 else if (LocVT == MVT::f128 && Offset < 16*8)
104 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
105 Reg = SP::Q0 + Offset/16;
107 // Promote to register when possible, otherwise use the stack slot.
109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113 // This argument goes on the stack in an 8-byte slot.
114 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
115 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
116 if (LocVT == MVT::f32)
119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
123 // Allocate a half-sized argument for the 64-bit ABI.
125 // This is used when passing { float, int } structs by value in registers.
126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
127 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
129 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
130 unsigned Offset = State.AllocateStack(4, 4);
132 if (LocVT == MVT::f32 && Offset < 16*8) {
133 // Promote floats to %f0-%f31.
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
139 if (LocVT == MVT::i32 && Offset < 6*8) {
140 // Promote integers to %i0-%i5, using half the register.
141 unsigned Reg = SP::I0 + Offset/8;
143 LocInfo = CCValAssign::AExt;
145 // Set the Custom bit if this i32 goes in the high bits of a register.
147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
158 #include "SparcGenCallingConv.inc"
160 // The calling conventions in SparcCallingConv.td are described in terms of the
161 // callee's register window. This function translates registers to the
162 // corresponding caller window %o register.
163 static unsigned toCallerWindow(unsigned Reg) {
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
171 SparcTargetLowering::LowerReturn(SDValue Chain,
172 CallingConv::ID CallConv, bool IsVarArg,
173 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<SDValue> &OutVals,
175 SDLoc DL, SelectionDAG &DAG) const {
176 if (Subtarget->is64Bit())
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
182 SparcTargetLowering::LowerReturn_32(SDValue Chain,
183 CallingConv::ID CallConv, bool IsVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
189 // CCValAssign - represent the assignment of the return value to locations.
190 SmallVector<CCValAssign, 16> RVLocs;
192 // CCState - Info about the registers and stack slot.
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
196 // Analyze return values.
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
200 SmallVector<SDValue, 4> RetOps(1, Chain);
201 // Make room for the return address offset.
202 RetOps.push_back(SDValue());
204 // Copy the result values into the output registers.
205 for (unsigned i = 0; i != RVLocs.size(); ++i) {
206 CCValAssign &VA = RVLocs[i];
207 assert(VA.isRegLoc() && "Can only return in registers!");
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
212 // Guarantee that all emitted copies are stuck together with flags.
213 Flag = Chain.getValue(1);
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
217 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
218 // If the function returns a struct, copy the SRetReturnReg to I0
219 if (MF.getFunction()->hasStructRetAttr()) {
220 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
221 unsigned Reg = SFI->getSRetReturnReg();
223 llvm_unreachable("sret virtual register not created in the entry block");
224 auto PtrVT = getPointerTy(DAG.getDataLayout());
225 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
226 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
227 Flag = Chain.getValue(1);
228 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
229 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
232 RetOps[0] = Chain; // Update chain.
233 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
235 // Add the flag if we have it.
237 RetOps.push_back(Flag);
239 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
242 // Lower return values for the 64-bit ABI.
243 // Return values are passed the exactly the same way as function arguments.
245 SparcTargetLowering::LowerReturn_64(SDValue Chain,
246 CallingConv::ID CallConv, bool IsVarArg,
247 const SmallVectorImpl<ISD::OutputArg> &Outs,
248 const SmallVectorImpl<SDValue> &OutVals,
249 SDLoc DL, SelectionDAG &DAG) const {
250 // CCValAssign - represent the assignment of the return value to locations.
251 SmallVector<CCValAssign, 16> RVLocs;
253 // CCState - Info about the registers and stack slot.
254 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
257 // Analyze return values.
258 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
261 SmallVector<SDValue, 4> RetOps(1, Chain);
263 // The second operand on the return instruction is the return address offset.
264 // The return address is always %i7+8 with the 64-bit ABI.
265 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
267 // Copy the result values into the output registers.
268 for (unsigned i = 0; i != RVLocs.size(); ++i) {
269 CCValAssign &VA = RVLocs[i];
270 assert(VA.isRegLoc() && "Can only return in registers!");
271 SDValue OutVal = OutVals[i];
273 // Integer return values must be sign or zero extended by the callee.
274 switch (VA.getLocInfo()) {
275 case CCValAssign::Full: break;
276 case CCValAssign::SExt:
277 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
279 case CCValAssign::ZExt:
280 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
282 case CCValAssign::AExt:
283 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
286 llvm_unreachable("Unknown loc info!");
289 // The custom bit on an i32 return value indicates that it should be passed
290 // in the high bits of the register.
291 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
292 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
293 DAG.getConstant(32, DL, MVT::i32));
295 // The next value may go in the low bits of the same register.
296 // Handle both at once.
297 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
298 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
299 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
300 // Skip the next value, it's already done.
305 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
307 // Guarantee that all emitted copies are stuck together with flags.
308 Flag = Chain.getValue(1);
309 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
312 RetOps[0] = Chain; // Update chain.
314 // Add the flag if we have it.
316 RetOps.push_back(Flag);
318 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
321 SDValue SparcTargetLowering::
322 LowerFormalArguments(SDValue Chain,
323 CallingConv::ID CallConv,
325 const SmallVectorImpl<ISD::InputArg> &Ins,
328 SmallVectorImpl<SDValue> &InVals) const {
329 if (Subtarget->is64Bit())
330 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
332 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
336 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
337 /// passed in either one or two GPRs, including FP values. TODO: we should
338 /// pass FP values in FP registers for fastcc functions.
339 SDValue SparcTargetLowering::
340 LowerFormalArguments_32(SDValue Chain,
341 CallingConv::ID CallConv,
343 const SmallVectorImpl<ISD::InputArg> &Ins,
346 SmallVectorImpl<SDValue> &InVals) const {
347 MachineFunction &MF = DAG.getMachineFunction();
348 MachineRegisterInfo &RegInfo = MF.getRegInfo();
349 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
351 // Assign locations to all of the incoming arguments.
352 SmallVector<CCValAssign, 16> ArgLocs;
353 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
355 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
357 const unsigned StackOffset = 92;
360 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
361 CCValAssign &VA = ArgLocs[i];
363 if (Ins[InIdx].Flags.isSRet()) {
365 report_fatal_error("sparc only supports sret on the first parameter");
366 // Get SRet from [%fp+64].
367 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
368 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
369 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
370 MachinePointerInfo(),
371 false, false, false, 0);
372 InVals.push_back(Arg);
377 if (VA.needsCustom()) {
378 assert(VA.getLocVT() == MVT::f64);
379 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
380 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
381 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
384 CCValAssign &NextVA = ArgLocs[++i];
387 if (NextVA.isMemLoc()) {
388 int FrameIdx = MF.getFrameInfo()->
389 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
390 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
391 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
392 MachinePointerInfo(),
393 false, false, false, 0);
395 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
396 &SP::IntRegsRegClass);
397 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
400 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
401 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
402 InVals.push_back(WholeValue);
405 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
406 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
407 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
408 if (VA.getLocVT() == MVT::f32)
409 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
410 else if (VA.getLocVT() != MVT::i32) {
411 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
412 DAG.getValueType(VA.getLocVT()));
413 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
415 InVals.push_back(Arg);
419 assert(VA.isMemLoc());
421 unsigned Offset = VA.getLocMemOffset()+StackOffset;
422 auto PtrVT = getPointerTy(DAG.getDataLayout());
424 if (VA.needsCustom()) {
425 assert(VA.getValVT() == MVT::f64);
426 // If it is double-word aligned, just load.
427 if (Offset % 8 == 0) {
428 int FI = MF.getFrameInfo()->CreateFixedObject(8,
431 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
432 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
433 MachinePointerInfo(),
434 false,false, false, 0);
435 InVals.push_back(Load);
439 int FI = MF.getFrameInfo()->CreateFixedObject(4,
442 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
443 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
444 MachinePointerInfo(),
445 false, false, false, 0);
446 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
449 SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
451 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
452 MachinePointerInfo(),
453 false, false, false, 0);
456 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
457 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
458 InVals.push_back(WholeValue);
462 int FI = MF.getFrameInfo()->CreateFixedObject(4,
465 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
467 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
468 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
469 MachinePointerInfo(),
470 false, false, false, 0);
472 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
473 // Sparc is big endian, so add an offset based on the ObjectVT.
474 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
475 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
476 DAG.getConstant(Offset, dl, MVT::i32));
477 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
478 MachinePointerInfo(),
479 VA.getValVT(), false, false, false,0);
480 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
482 InVals.push_back(Load);
485 if (MF.getFunction()->hasStructRetAttr()) {
486 // Copy the SRet Argument to SRetReturnReg.
487 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
488 unsigned Reg = SFI->getSRetReturnReg();
490 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
491 SFI->setSRetReturnReg(Reg);
493 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
494 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
497 // Store remaining ArgRegs to the stack if this is a varargs function.
499 static const MCPhysReg ArgRegs[] = {
500 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
502 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
503 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
504 unsigned ArgOffset = CCInfo.getNextStackOffset();
505 if (NumAllocated == 6)
506 ArgOffset += StackOffset;
509 ArgOffset = 68+4*NumAllocated;
512 // Remember the vararg offset for the va_start implementation.
513 FuncInfo->setVarArgsFrameOffset(ArgOffset);
515 std::vector<SDValue> OutChains;
517 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
518 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
519 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
520 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
522 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
524 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
526 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
527 MachinePointerInfo(),
532 if (!OutChains.empty()) {
533 OutChains.push_back(Chain);
534 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
541 // Lower formal arguments for the 64 bit ABI.
542 SDValue SparcTargetLowering::
543 LowerFormalArguments_64(SDValue Chain,
544 CallingConv::ID CallConv,
546 const SmallVectorImpl<ISD::InputArg> &Ins,
549 SmallVectorImpl<SDValue> &InVals) const {
550 MachineFunction &MF = DAG.getMachineFunction();
552 // Analyze arguments according to CC_Sparc64.
553 SmallVector<CCValAssign, 16> ArgLocs;
554 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
556 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
558 // The argument array begins at %fp+BIAS+128, after the register save area.
559 const unsigned ArgArea = 128;
561 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
562 CCValAssign &VA = ArgLocs[i];
564 // This argument is passed in a register.
565 // All integer register arguments are promoted by the caller to i64.
567 // Create a virtual register for the promoted live-in value.
568 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
569 getRegClassFor(VA.getLocVT()));
570 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
572 // Get the high bits for i32 struct elements.
573 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
574 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
575 DAG.getConstant(32, DL, MVT::i32));
577 // The caller promoted the argument, so insert an Assert?ext SDNode so we
578 // won't promote the value again in this function.
579 switch (VA.getLocInfo()) {
580 case CCValAssign::SExt:
581 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
582 DAG.getValueType(VA.getValVT()));
584 case CCValAssign::ZExt:
585 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
586 DAG.getValueType(VA.getValVT()));
592 // Truncate the register down to the argument type.
594 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
596 InVals.push_back(Arg);
600 // The registers are exhausted. This argument was passed on the stack.
601 assert(VA.isMemLoc());
602 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
603 // beginning of the arguments area at %fp+BIAS+128.
604 unsigned Offset = VA.getLocMemOffset() + ArgArea;
605 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
606 // Adjust offset for extended arguments, SPARC is big-endian.
607 // The caller will have written the full slot with extended bytes, but we
608 // prefer our own extending loads.
610 Offset += 8 - ValSize;
611 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
612 InVals.push_back(DAG.getLoad(
613 VA.getValVT(), DL, Chain,
614 DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),
615 MachinePointerInfo::getFixedStack(FI), false, false, false, 0));
621 // This function takes variable arguments, some of which may have been passed
622 // in registers %i0-%i5. Variable floating point arguments are never passed
623 // in floating point registers. They go on %i0-%i5 or on the stack like
624 // integer arguments.
626 // The va_start intrinsic needs to know the offset to the first variable
628 unsigned ArgOffset = CCInfo.getNextStackOffset();
629 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
630 // Skip the 128 bytes of register save area.
631 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
632 Subtarget->getStackPointerBias());
634 // Save the variable arguments that were passed in registers.
635 // The caller is required to reserve stack space for 6 arguments regardless
636 // of how many arguments were actually passed.
637 SmallVector<SDValue, 8> OutChains;
638 for (; ArgOffset < 6*8; ArgOffset += 8) {
639 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
640 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
641 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
642 auto PtrVT = getPointerTy(MF.getDataLayout());
644 DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
645 MachinePointerInfo::getFixedStack(FI), false, false, 0));
648 if (!OutChains.empty())
649 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
655 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
656 SmallVectorImpl<SDValue> &InVals) const {
657 if (Subtarget->is64Bit())
658 return LowerCall_64(CLI, InVals);
659 return LowerCall_32(CLI, InVals);
662 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
663 ImmutableCallSite *CS) {
665 return CS->hasFnAttr(Attribute::ReturnsTwice);
667 const Function *CalleeFn = nullptr;
668 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
669 CalleeFn = dyn_cast<Function>(G->getGlobal());
670 } else if (ExternalSymbolSDNode *E =
671 dyn_cast<ExternalSymbolSDNode>(Callee)) {
672 const Function *Fn = DAG.getMachineFunction().getFunction();
673 const Module *M = Fn->getParent();
674 const char *CalleeName = E->getSymbol();
675 CalleeFn = M->getFunction(CalleeName);
680 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
683 // Lower a call for the 32-bit ABI.
685 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
686 SmallVectorImpl<SDValue> &InVals) const {
687 SelectionDAG &DAG = CLI.DAG;
689 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
690 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
691 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
692 SDValue Chain = CLI.Chain;
693 SDValue Callee = CLI.Callee;
694 bool &isTailCall = CLI.IsTailCall;
695 CallingConv::ID CallConv = CLI.CallConv;
696 bool isVarArg = CLI.IsVarArg;
698 // Sparc target does not yet support tail call optimization.
701 // Analyze operands of the call, assigning locations to each operand.
702 SmallVector<CCValAssign, 16> ArgLocs;
703 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
705 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
707 // Get the size of the outgoing arguments stack space requirement.
708 unsigned ArgsSize = CCInfo.getNextStackOffset();
710 // Keep stack frames 8-byte aligned.
711 ArgsSize = (ArgsSize+7) & ~7;
713 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
715 // Create local copies for byval args.
716 SmallVector<SDValue, 8> ByValArgs;
717 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
718 ISD::ArgFlagsTy Flags = Outs[i].Flags;
719 if (!Flags.isByVal())
722 SDValue Arg = OutVals[i];
723 unsigned Size = Flags.getByValSize();
724 unsigned Align = Flags.getByValAlign();
726 int FI = MFI->CreateStackObject(Size, Align, false);
727 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
728 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
730 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
731 false, // isVolatile,
732 (Size <= 32), // AlwaysInline if size <= 32,
734 MachinePointerInfo(), MachinePointerInfo());
735 ByValArgs.push_back(FIPtr);
738 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
741 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
742 SmallVector<SDValue, 8> MemOpChains;
744 const unsigned StackOffset = 92;
745 bool hasStructRetAttr = false;
746 // Walk the register/memloc assignments, inserting copies/loads.
747 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
750 CCValAssign &VA = ArgLocs[i];
751 SDValue Arg = OutVals[realArgIdx];
753 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
755 // Use local copy if it is a byval arg.
757 Arg = ByValArgs[byvalArgIdx++];
759 // Promote the value if needed.
760 switch (VA.getLocInfo()) {
761 default: llvm_unreachable("Unknown loc info!");
762 case CCValAssign::Full: break;
763 case CCValAssign::SExt:
764 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
766 case CCValAssign::ZExt:
767 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
769 case CCValAssign::AExt:
770 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
772 case CCValAssign::BCvt:
773 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
777 if (Flags.isSRet()) {
778 assert(VA.needsCustom());
779 // store SRet argument in %sp+64
780 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
781 SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
782 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
783 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
784 MachinePointerInfo(),
786 hasStructRetAttr = true;
790 if (VA.needsCustom()) {
791 assert(VA.getLocVT() == MVT::f64);
794 unsigned Offset = VA.getLocMemOffset() + StackOffset;
795 // if it is double-word aligned, just store.
796 if (Offset % 8 == 0) {
797 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
798 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
799 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
800 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
801 MachinePointerInfo(),
807 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
808 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
809 Arg, StackPtr, MachinePointerInfo(),
811 // Sparc is big-endian, so the high part comes first.
812 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
813 MachinePointerInfo(), false, false, false, 0);
814 // Increment the pointer to the other half.
815 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
816 DAG.getIntPtrConstant(4, dl));
817 // Load the low part.
818 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
819 MachinePointerInfo(), false, false, false, 0);
822 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
824 CCValAssign &NextVA = ArgLocs[++i];
825 if (NextVA.isRegLoc()) {
826 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
828 // Store the low part in stack.
829 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
830 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
831 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
832 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
833 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
834 MachinePointerInfo(),
838 unsigned Offset = VA.getLocMemOffset() + StackOffset;
839 // Store the high part.
840 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
841 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
842 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
843 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
844 MachinePointerInfo(),
846 // Store the low part.
847 PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
848 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
849 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
850 MachinePointerInfo(),
856 // Arguments that can be passed on register must be kept at
859 if (VA.getLocVT() != MVT::f32) {
860 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
863 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
864 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
868 assert(VA.isMemLoc());
870 // Create a store off the stack pointer for this argument.
871 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
872 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
874 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
875 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
876 MachinePointerInfo(),
881 // Emit all stores, make sure the occur before any copies into physregs.
882 if (!MemOpChains.empty())
883 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
885 // Build a sequence of copy-to-reg nodes chained together with token
886 // chain and flag operands which copy the outgoing args into registers.
887 // The InFlag in necessary since all emitted instructions must be
890 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
891 unsigned Reg = toCallerWindow(RegsToPass[i].first);
892 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
893 InFlag = Chain.getValue(1);
896 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
897 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
899 // If the callee is a GlobalAddress node (quite common, every direct call is)
900 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
901 // Likewise ExternalSymbol -> TargetExternalSymbol.
902 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
903 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
904 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
905 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
906 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
907 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
909 // Returns a chain & a flag for retval copy to use
910 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
911 SmallVector<SDValue, 8> Ops;
912 Ops.push_back(Chain);
913 Ops.push_back(Callee);
914 if (hasStructRetAttr)
915 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
916 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
917 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
918 RegsToPass[i].second.getValueType()));
920 // Add a register mask operand representing the call-preserved registers.
921 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
922 const uint32_t *Mask =
924 ? TRI->getRTCallPreservedMask(CallConv)
925 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
926 assert(Mask && "Missing call preserved mask for calling convention");
927 Ops.push_back(DAG.getRegisterMask(Mask));
929 if (InFlag.getNode())
930 Ops.push_back(InFlag);
932 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
933 InFlag = Chain.getValue(1);
935 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
936 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
937 InFlag = Chain.getValue(1);
939 // Assign locations to each value returned by this call.
940 SmallVector<CCValAssign, 16> RVLocs;
941 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
944 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
946 // Copy all of the result registers out of their specified physreg.
947 for (unsigned i = 0; i != RVLocs.size(); ++i) {
948 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
949 RVLocs[i].getValVT(), InFlag).getValue(1);
950 InFlag = Chain.getValue(2);
951 InVals.push_back(Chain.getValue(0));
957 // This functions returns true if CalleeName is a ABI function that returns
958 // a long double (fp128).
959 static bool isFP128ABICall(const char *CalleeName)
961 static const char *const ABICalls[] =
962 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
964 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
965 "_Q_lltoq", "_Q_ulltoq",
968 for (const char * const *I = ABICalls; *I != nullptr; ++I)
969 if (strcmp(CalleeName, *I) == 0)
975 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
977 const Function *CalleeFn = nullptr;
978 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
979 CalleeFn = dyn_cast<Function>(G->getGlobal());
980 } else if (ExternalSymbolSDNode *E =
981 dyn_cast<ExternalSymbolSDNode>(Callee)) {
982 const Function *Fn = DAG.getMachineFunction().getFunction();
983 const Module *M = Fn->getParent();
984 const char *CalleeName = E->getSymbol();
985 CalleeFn = M->getFunction(CalleeName);
986 if (!CalleeFn && isFP128ABICall(CalleeName))
987 return 16; // Return sizeof(fp128)
993 assert(CalleeFn->hasStructRetAttr() &&
994 "Callee does not have the StructRet attribute.");
996 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
997 Type *ElementTy = Ty->getElementType();
998 return DAG.getDataLayout().getTypeAllocSize(ElementTy);
1002 // Fixup floating point arguments in the ... part of a varargs call.
1004 // The SPARC v9 ABI requires that floating point arguments are treated the same
1005 // as integers when calling a varargs function. This does not apply to the
1006 // fixed arguments that are part of the function's prototype.
1008 // This function post-processes a CCValAssign array created by
1009 // AnalyzeCallOperands().
1010 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1011 ArrayRef<ISD::OutputArg> Outs) {
1012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1013 const CCValAssign &VA = ArgLocs[i];
1014 MVT ValTy = VA.getLocVT();
1015 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1016 // varargs functions.
1017 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1019 // The fixed arguments to a varargs function still go in FP registers.
1020 if (Outs[VA.getValNo()].IsFixed)
1023 // This floating point argument should be reassigned.
1026 // Determine the offset into the argument array.
1027 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1028 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1029 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1030 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1033 // This argument should go in %i0-%i5.
1034 unsigned IReg = SP::I0 + Offset/8;
1035 if (ValTy == MVT::f64)
1036 // Full register, just bitconvert into i64.
1037 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1038 IReg, MVT::i64, CCValAssign::BCvt);
1040 assert(ValTy == MVT::f128 && "Unexpected type!");
1041 // Full register, just bitconvert into i128 -- We will lower this into
1042 // two i64s in LowerCall_64.
1043 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1044 IReg, MVT::i128, CCValAssign::BCvt);
1047 // This needs to go to memory, we're out of integer registers.
1048 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1049 Offset, VA.getLocVT(), VA.getLocInfo());
1055 // Lower a call for the 64-bit ABI.
1057 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1058 SmallVectorImpl<SDValue> &InVals) const {
1059 SelectionDAG &DAG = CLI.DAG;
1061 SDValue Chain = CLI.Chain;
1062 auto PtrVT = getPointerTy(DAG.getDataLayout());
1064 // Sparc target does not yet support tail call optimization.
1065 CLI.IsTailCall = false;
1067 // Analyze operands of the call, assigning locations to each operand.
1068 SmallVector<CCValAssign, 16> ArgLocs;
1069 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1071 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1073 // Get the size of the outgoing arguments stack space requirement.
1074 // The stack offset computed by CC_Sparc64 includes all arguments.
1075 // Called functions expect 6 argument words to exist in the stack frame, used
1077 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1079 // Keep stack frames 16-byte aligned.
1080 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1082 // Varargs calls require special treatment.
1084 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1086 // Adjust the stack pointer to make room for the arguments.
1087 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1088 // with more than 6 arguments.
1089 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1092 // Collect the set of registers to pass to the function and their values.
1093 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1095 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1097 // Collect chains from all the memory opeations that copy arguments to the
1098 // stack. They must follow the stack pointer adjustment above and precede the
1099 // call instruction itself.
1100 SmallVector<SDValue, 8> MemOpChains;
1102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1103 const CCValAssign &VA = ArgLocs[i];
1104 SDValue Arg = CLI.OutVals[i];
1106 // Promote the value if needed.
1107 switch (VA.getLocInfo()) {
1109 llvm_unreachable("Unknown location info!");
1110 case CCValAssign::Full:
1112 case CCValAssign::SExt:
1113 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1115 case CCValAssign::ZExt:
1116 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1118 case CCValAssign::AExt:
1119 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1121 case CCValAssign::BCvt:
1122 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1123 // SPARC does not support i128 natively. Lower it into two i64, see below.
1124 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1125 || VA.getLocVT() != MVT::i128)
1126 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1130 if (VA.isRegLoc()) {
1131 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1132 && VA.getLocVT() == MVT::i128) {
1133 // Store and reload into the interger register reg and reg+1.
1134 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1135 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1136 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1137 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1138 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1139 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1140 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1142 // Store to %sp+BIAS+128+Offset
1143 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1144 MachinePointerInfo(),
1146 // Load into Reg and Reg+1
1147 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1148 MachinePointerInfo(),
1149 false, false, false, 0);
1150 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1151 MachinePointerInfo(),
1152 false, false, false, 0);
1153 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1155 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1160 // The custom bit on an i32 return value indicates that it should be
1161 // passed in the high bits of the register.
1162 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1163 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1164 DAG.getConstant(32, DL, MVT::i32));
1166 // The next value may go in the low bits of the same register.
1167 // Handle both at once.
1168 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1169 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1170 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1172 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1173 // Skip the next value, it's already done.
1177 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1181 assert(VA.isMemLoc());
1183 // Create a store off the stack pointer for this argument.
1184 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1185 // The argument area starts at %fp+BIAS+128 in the callee frame,
1186 // %sp+BIAS+128 in ours.
1187 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1188 Subtarget->getStackPointerBias() +
1190 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1191 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1192 MachinePointerInfo(),
1196 // Emit all stores, make sure they occur before the call.
1197 if (!MemOpChains.empty())
1198 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1200 // Build a sequence of CopyToReg nodes glued together with token chain and
1201 // glue operands which copy the outgoing args into registers. The InGlue is
1202 // necessary since all emitted instructions must be stuck together in order
1203 // to pass the live physical registers.
1205 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1206 Chain = DAG.getCopyToReg(Chain, DL,
1207 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1208 InGlue = Chain.getValue(1);
1211 // If the callee is a GlobalAddress node (quite common, every direct call is)
1212 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1213 // Likewise ExternalSymbol -> TargetExternalSymbol.
1214 SDValue Callee = CLI.Callee;
1215 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1216 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1217 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
1218 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1219 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1220 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1221 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1223 // Build the operands for the call instruction itself.
1224 SmallVector<SDValue, 8> Ops;
1225 Ops.push_back(Chain);
1226 Ops.push_back(Callee);
1227 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1228 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1229 RegsToPass[i].second.getValueType()));
1231 // Add a register mask operand representing the call-preserved registers.
1232 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1233 const uint32_t *Mask =
1234 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1235 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1237 assert(Mask && "Missing call preserved mask for calling convention");
1238 Ops.push_back(DAG.getRegisterMask(Mask));
1240 // Make sure the CopyToReg nodes are glued to the call instruction which
1241 // consumes the registers.
1242 if (InGlue.getNode())
1243 Ops.push_back(InGlue);
1245 // Now the call itself.
1246 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1247 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1248 InGlue = Chain.getValue(1);
1250 // Revert the stack pointer immediately after the call.
1251 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1252 DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
1253 InGlue = Chain.getValue(1);
1255 // Now extract the return values. This is more or less the same as
1256 // LowerFormalArguments_64.
1258 // Assign locations to each value returned by this call.
1259 SmallVector<CCValAssign, 16> RVLocs;
1260 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1263 // Set inreg flag manually for codegen generated library calls that
1265 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1266 CLI.Ins[0].Flags.setInReg();
1268 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1270 // Copy all of the result registers out of their specified physreg.
1271 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1272 CCValAssign &VA = RVLocs[i];
1273 unsigned Reg = toCallerWindow(VA.getLocReg());
1275 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1276 // reside in the same register in the high and low bits. Reuse the
1277 // CopyFromReg previous node to avoid duplicate copies.
1279 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1280 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1281 RV = Chain.getValue(0);
1283 // But usually we'll create a new CopyFromReg for a different register.
1284 if (!RV.getNode()) {
1285 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1286 Chain = RV.getValue(1);
1287 InGlue = Chain.getValue(2);
1290 // Get the high bits for i32 struct elements.
1291 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1292 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1293 DAG.getConstant(32, DL, MVT::i32));
1295 // The callee promoted the return value, so insert an Assert?ext SDNode so
1296 // we won't promote the value again in this function.
1297 switch (VA.getLocInfo()) {
1298 case CCValAssign::SExt:
1299 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1300 DAG.getValueType(VA.getValVT()));
1302 case CCValAssign::ZExt:
1303 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1304 DAG.getValueType(VA.getValVT()));
1310 // Truncate the register down to the return value type.
1311 if (VA.isExtInLoc())
1312 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1314 InVals.push_back(RV);
1320 //===----------------------------------------------------------------------===//
1321 // TargetLowering Implementation
1322 //===----------------------------------------------------------------------===//
1324 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1326 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1328 default: llvm_unreachable("Unknown integer condition code!");
1329 case ISD::SETEQ: return SPCC::ICC_E;
1330 case ISD::SETNE: return SPCC::ICC_NE;
1331 case ISD::SETLT: return SPCC::ICC_L;
1332 case ISD::SETGT: return SPCC::ICC_G;
1333 case ISD::SETLE: return SPCC::ICC_LE;
1334 case ISD::SETGE: return SPCC::ICC_GE;
1335 case ISD::SETULT: return SPCC::ICC_CS;
1336 case ISD::SETULE: return SPCC::ICC_LEU;
1337 case ISD::SETUGT: return SPCC::ICC_GU;
1338 case ISD::SETUGE: return SPCC::ICC_CC;
1342 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1344 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1346 default: llvm_unreachable("Unknown fp condition code!");
1348 case ISD::SETOEQ: return SPCC::FCC_E;
1350 case ISD::SETUNE: return SPCC::FCC_NE;
1352 case ISD::SETOLT: return SPCC::FCC_L;
1354 case ISD::SETOGT: return SPCC::FCC_G;
1356 case ISD::SETOLE: return SPCC::FCC_LE;
1358 case ISD::SETOGE: return SPCC::FCC_GE;
1359 case ISD::SETULT: return SPCC::FCC_UL;
1360 case ISD::SETULE: return SPCC::FCC_ULE;
1361 case ISD::SETUGT: return SPCC::FCC_UG;
1362 case ISD::SETUGE: return SPCC::FCC_UGE;
1363 case ISD::SETUO: return SPCC::FCC_U;
1364 case ISD::SETO: return SPCC::FCC_O;
1365 case ISD::SETONE: return SPCC::FCC_LG;
1366 case ISD::SETUEQ: return SPCC::FCC_UE;
1370 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
1371 const SparcSubtarget &STI)
1372 : TargetLowering(TM), Subtarget(&STI) {
1373 auto &DL = *TM.getDataLayout();
1375 // Set up the register classes.
1376 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1377 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1378 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1379 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1380 if (Subtarget->is64Bit())
1381 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1383 // Turn FP extload into load/fextend
1384 for (MVT VT : MVT::fp_valuetypes()) {
1385 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1386 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1389 // Sparc doesn't have i1 sign extending load
1390 for (MVT VT : MVT::integer_valuetypes())
1391 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1393 // Turn FP truncstore into trunc + store.
1394 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1395 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1396 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1398 // Custom legalize GlobalAddress nodes into LO/HI parts.
1399 setOperationAction(ISD::GlobalAddress, getPointerTy(DL), Custom);
1400 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(DL), Custom);
1401 setOperationAction(ISD::ConstantPool, getPointerTy(DL), Custom);
1402 setOperationAction(ISD::BlockAddress, getPointerTy(DL), Custom);
1404 // Sparc doesn't have sext_inreg, replace them with shl/sra
1405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1409 // Sparc has no REM or DIVREM operations.
1410 setOperationAction(ISD::UREM, MVT::i32, Expand);
1411 setOperationAction(ISD::SREM, MVT::i32, Expand);
1412 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1413 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1415 // ... nor does SparcV9.
1416 if (Subtarget->is64Bit()) {
1417 setOperationAction(ISD::UREM, MVT::i64, Expand);
1418 setOperationAction(ISD::SREM, MVT::i64, Expand);
1419 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1420 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1423 // Custom expand fp<->sint
1424 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1425 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1427 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1429 // Custom Expand fp<->uint
1430 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1431 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1432 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1435 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1436 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1438 // Sparc has no select or setcc: expand to SELECT_CC.
1439 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1440 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1441 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1442 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1444 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1445 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1446 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1447 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1449 // Sparc doesn't have BRCOND either, it has BR_CC.
1450 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1451 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1452 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1453 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1454 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1455 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1456 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1458 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1459 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1460 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1461 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1463 if (Subtarget->is64Bit()) {
1464 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1465 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1466 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1467 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1468 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1469 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1470 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1471 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1472 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1473 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1475 setOperationAction(ISD::CTPOP, MVT::i64,
1476 Subtarget->usePopc() ? Legal : Expand);
1477 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1478 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1479 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1481 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1482 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1483 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1484 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1488 // FIXME: We insert fences for each atomics and generate sub-optimal code
1489 // for PSO/TSO. Also, implement other atomicrmw operations.
1491 setInsertFencesForAtomic(true);
1493 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1494 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
1495 (Subtarget->isV9() ? Legal: Expand));
1498 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1500 // Custom Lower Atomic LOAD/STORE
1501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1504 if (Subtarget->is64Bit()) {
1505 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1507 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1508 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1511 if (!Subtarget->isV9()) {
1512 // SparcV8 does not have FNEGD and FABSD.
1513 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1514 setOperationAction(ISD::FABS, MVT::f64, Custom);
1517 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1518 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1519 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1520 setOperationAction(ISD::FREM , MVT::f128, Expand);
1521 setOperationAction(ISD::FMA , MVT::f128, Expand);
1522 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1523 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1524 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1525 setOperationAction(ISD::FREM , MVT::f64, Expand);
1526 setOperationAction(ISD::FMA , MVT::f64, Expand);
1527 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1528 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1529 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1530 setOperationAction(ISD::FREM , MVT::f32, Expand);
1531 setOperationAction(ISD::FMA , MVT::f32, Expand);
1532 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1534 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1536 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1537 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1538 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1539 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1540 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1541 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1542 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1543 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1544 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1546 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1547 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1548 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1550 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1551 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1552 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1554 if (Subtarget->is64Bit()) {
1555 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1556 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1557 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1558 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1560 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1561 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1563 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1564 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1565 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1568 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1569 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1570 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1571 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1573 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1575 // Use the default implementation.
1576 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1577 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1578 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1579 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1580 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1582 setExceptionPointerRegister(SP::I0);
1583 setExceptionSelectorRegister(SP::I1);
1585 setStackPointerRegisterToSaveRestore(SP::O6);
1587 setOperationAction(ISD::CTPOP, MVT::i32,
1588 Subtarget->usePopc() ? Legal : Expand);
1590 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1591 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1592 setOperationAction(ISD::STORE, MVT::f128, Legal);
1594 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1595 setOperationAction(ISD::STORE, MVT::f128, Custom);
1598 if (Subtarget->hasHardQuad()) {
1599 setOperationAction(ISD::FADD, MVT::f128, Legal);
1600 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1601 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1602 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1603 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1604 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1605 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1606 if (Subtarget->isV9()) {
1607 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1608 setOperationAction(ISD::FABS, MVT::f128, Legal);
1610 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1611 setOperationAction(ISD::FABS, MVT::f128, Custom);
1614 if (!Subtarget->is64Bit()) {
1615 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1616 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1617 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1618 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1622 // Custom legalize f128 operations.
1624 setOperationAction(ISD::FADD, MVT::f128, Custom);
1625 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1626 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1627 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1628 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1629 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1630 setOperationAction(ISD::FABS, MVT::f128, Custom);
1632 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1633 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1634 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1636 // Setup Runtime library names.
1637 if (Subtarget->is64Bit()) {
1638 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1639 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1640 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1641 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1642 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1643 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1644 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1645 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1646 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1647 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1648 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1649 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1650 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1651 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1652 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1653 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1654 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1656 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1657 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1658 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1659 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1660 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1661 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1662 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1663 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1664 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1665 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1666 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1667 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1668 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1669 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1670 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1671 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1672 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1676 setMinFunctionAlignment(2);
1678 computeRegisterProperties(Subtarget->getRegisterInfo());
1681 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1682 switch ((SPISD::NodeType)Opcode) {
1683 case SPISD::FIRST_NUMBER: break;
1684 case SPISD::CMPICC: return "SPISD::CMPICC";
1685 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1686 case SPISD::BRICC: return "SPISD::BRICC";
1687 case SPISD::BRXCC: return "SPISD::BRXCC";
1688 case SPISD::BRFCC: return "SPISD::BRFCC";
1689 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1690 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1691 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1692 case SPISD::Hi: return "SPISD::Hi";
1693 case SPISD::Lo: return "SPISD::Lo";
1694 case SPISD::FTOI: return "SPISD::FTOI";
1695 case SPISD::ITOF: return "SPISD::ITOF";
1696 case SPISD::FTOX: return "SPISD::FTOX";
1697 case SPISD::XTOF: return "SPISD::XTOF";
1698 case SPISD::CALL: return "SPISD::CALL";
1699 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1700 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1701 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1702 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1703 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1704 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1709 EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
1713 return VT.changeVectorElementTypeToInteger();
1716 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1717 /// be zero. Op is expected to be a target specific node. Used by DAG
1719 void SparcTargetLowering::computeKnownBitsForTargetNode
1723 const SelectionDAG &DAG,
1724 unsigned Depth) const {
1725 APInt KnownZero2, KnownOne2;
1726 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1728 switch (Op.getOpcode()) {
1730 case SPISD::SELECT_ICC:
1731 case SPISD::SELECT_XCC:
1732 case SPISD::SELECT_FCC:
1733 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1734 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1736 // Only known if known in both the LHS and RHS.
1737 KnownOne &= KnownOne2;
1738 KnownZero &= KnownZero2;
1743 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1744 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1745 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1746 ISD::CondCode CC, unsigned &SPCC) {
1747 if (isa<ConstantSDNode>(RHS) &&
1748 cast<ConstantSDNode>(RHS)->isNullValue() &&
1750 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1751 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1752 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1753 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1754 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1755 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1756 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1757 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1758 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1759 SDValue CMPCC = LHS.getOperand(3);
1760 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1761 LHS = CMPCC.getOperand(0);
1762 RHS = CMPCC.getOperand(1);
1766 // Convert to a target node and set target flags.
1767 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1768 SelectionDAG &DAG) const {
1769 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1770 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1772 GA->getValueType(0),
1773 GA->getOffset(), TF);
1775 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1776 return DAG.getTargetConstantPool(CP->getConstVal(),
1777 CP->getValueType(0),
1779 CP->getOffset(), TF);
1781 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1782 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1787 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1788 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1789 ES->getValueType(0), TF);
1791 llvm_unreachable("Unhandled address SDNode");
1794 // Split Op into high and low parts according to HiTF and LoTF.
1795 // Return an ADD node combining the parts.
1796 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1797 unsigned HiTF, unsigned LoTF,
1798 SelectionDAG &DAG) const {
1800 EVT VT = Op.getValueType();
1801 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1802 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1803 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1806 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1807 // or ExternalSymbol SDNode.
1808 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1810 EVT VT = getPointerTy(DAG.getDataLayout());
1812 // Handle PIC mode first.
1813 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1814 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1815 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1816 SparcMCExpr::VK_Sparc_GOT10, DAG);
1817 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1818 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1819 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1820 // function has calls.
1821 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1822 MFI->setHasCalls(true);
1823 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1824 MachinePointerInfo::getGOT(), false, false, false, 0);
1827 // This is one of the absolute code models.
1828 switch(getTargetMachine().getCodeModel()) {
1830 llvm_unreachable("Unsupported absolute code model");
1831 case CodeModel::Small:
1833 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1834 SparcMCExpr::VK_Sparc_LO, DAG);
1835 case CodeModel::Medium: {
1837 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1838 SparcMCExpr::VK_Sparc_M44, DAG);
1839 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
1840 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1841 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1842 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1844 case CodeModel::Large: {
1846 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1847 SparcMCExpr::VK_Sparc_HM, DAG);
1848 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
1849 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1850 SparcMCExpr::VK_Sparc_LO, DAG);
1851 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1856 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1857 SelectionDAG &DAG) const {
1858 return makeAddress(Op, DAG);
1861 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1862 SelectionDAG &DAG) const {
1863 return makeAddress(Op, DAG);
1866 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1867 SelectionDAG &DAG) const {
1868 return makeAddress(Op, DAG);
1871 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1872 SelectionDAG &DAG) const {
1874 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1876 const GlobalValue *GV = GA->getGlobal();
1877 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1879 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1881 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1882 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1883 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
1884 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
1885 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1886 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
1887 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
1888 unsigned addTF = ((model == TLSModel::GeneralDynamic)
1889 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
1890 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
1891 unsigned callTF = ((model == TLSModel::GeneralDynamic)
1892 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
1893 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
1895 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1896 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1897 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1898 withTargetFlags(Op, addTF, DAG));
1900 SDValue Chain = DAG.getEntryNode();
1903 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
1904 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1905 InFlag = Chain.getValue(1);
1906 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1907 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1909 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1910 SmallVector<SDValue, 4> Ops;
1911 Ops.push_back(Chain);
1912 Ops.push_back(Callee);
1913 Ops.push_back(Symbol);
1914 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1915 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1916 DAG.getMachineFunction(), CallingConv::C);
1917 assert(Mask && "Missing call preserved mask for calling convention");
1918 Ops.push_back(DAG.getRegisterMask(Mask));
1919 Ops.push_back(InFlag);
1920 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
1921 InFlag = Chain.getValue(1);
1922 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
1923 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1924 InFlag = Chain.getValue(1);
1925 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1927 if (model != TLSModel::LocalDynamic)
1930 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1931 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
1932 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1933 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
1934 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1935 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1936 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
1939 if (model == TLSModel::InitialExec) {
1940 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
1941 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
1943 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1945 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1946 // function has calls.
1947 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1948 MFI->setHasCalls(true);
1950 SDValue TGA = makeHiLoPair(Op,
1951 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
1952 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
1953 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1954 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1956 withTargetFlags(Op, ldTF, DAG));
1957 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1958 DAG.getRegister(SP::G7, PtrVT), Offset,
1960 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
1963 assert(model == TLSModel::LocalExec);
1964 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1965 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
1966 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1967 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
1968 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1970 return DAG.getNode(ISD::ADD, DL, PtrVT,
1971 DAG.getRegister(SP::G7, PtrVT), Offset);
1975 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1976 SDValue Arg, SDLoc DL,
1977 SelectionDAG &DAG) const {
1978 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1979 EVT ArgVT = Arg.getValueType();
1980 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1986 if (ArgTy->isFP128Ty()) {
1987 // Create a stack object and pass the pointer to the library function.
1988 int FI = MFI->CreateStackObject(16, 8, false);
1989 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1990 Chain = DAG.getStore(Chain,
1994 MachinePointerInfo(),
2000 Entry.Ty = PointerType::getUnqual(ArgTy);
2002 Args.push_back(Entry);
2007 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2008 const char *LibFuncName,
2009 unsigned numArgs) const {
2013 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2014 auto PtrVT = getPointerTy(DAG.getDataLayout());
2016 SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2017 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2018 Type *RetTyABI = RetTy;
2019 SDValue Chain = DAG.getEntryNode();
2022 if (RetTy->isFP128Ty()) {
2023 // Create a Stack Object to receive the return value of type f128.
2025 int RetFI = MFI->CreateStackObject(16, 8, false);
2026 RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2027 Entry.Node = RetPtr;
2028 Entry.Ty = PointerType::getUnqual(RetTy);
2029 if (!Subtarget->is64Bit())
2030 Entry.isSRet = true;
2031 Entry.isReturned = false;
2032 Args.push_back(Entry);
2033 RetTyABI = Type::getVoidTy(*DAG.getContext());
2036 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2037 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2038 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2040 TargetLowering::CallLoweringInfo CLI(DAG);
2041 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2042 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0);
2044 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2046 // chain is in second result.
2047 if (RetTyABI == RetTy)
2048 return CallInfo.first;
2050 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2052 Chain = CallInfo.second;
2054 // Load RetPtr to get the return value.
2055 return DAG.getLoad(Op.getValueType(),
2059 MachinePointerInfo(),
2060 false, false, false, 8);
2064 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2067 SelectionDAG &DAG) const {
2069 const char *LibCall = nullptr;
2070 bool is64Bit = Subtarget->is64Bit();
2072 default: llvm_unreachable("Unhandled conditional code!");
2073 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2074 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2075 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2076 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2077 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2078 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2086 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2089 auto PtrVT = getPointerTy(DAG.getDataLayout());
2090 SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2091 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2093 SDValue Chain = DAG.getEntryNode();
2094 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2095 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2097 TargetLowering::CallLoweringInfo CLI(DAG);
2098 CLI.setDebugLoc(DL).setChain(Chain)
2099 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
2101 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2103 // result is in first, and chain is in second result.
2104 SDValue Result = CallInfo.first;
2108 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2109 SPCC = SPCC::ICC_NE;
2110 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2112 case SPCC::FCC_UL : {
2113 SDValue Mask = DAG.getTargetConstant(1, DL, Result.getValueType());
2114 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2115 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2116 SPCC = SPCC::ICC_NE;
2117 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2119 case SPCC::FCC_ULE: {
2120 SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
2121 SPCC = SPCC::ICC_NE;
2122 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2124 case SPCC::FCC_UG : {
2125 SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2127 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2129 case SPCC::FCC_UGE: {
2130 SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2131 SPCC = SPCC::ICC_NE;
2132 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2135 case SPCC::FCC_U : {
2136 SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2138 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2140 case SPCC::FCC_O : {
2141 SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2142 SPCC = SPCC::ICC_NE;
2143 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2145 case SPCC::FCC_LG : {
2146 SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
2147 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2148 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2149 SPCC = SPCC::ICC_NE;
2150 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2152 case SPCC::FCC_UE : {
2153 SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
2154 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2155 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2157 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2163 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2164 const SparcTargetLowering &TLI) {
2166 if (Op.getOperand(0).getValueType() == MVT::f64)
2167 return TLI.LowerF128Op(Op, DAG,
2168 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2170 if (Op.getOperand(0).getValueType() == MVT::f32)
2171 return TLI.LowerF128Op(Op, DAG,
2172 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2174 llvm_unreachable("fpextend with non-float operand!");
2179 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2180 const SparcTargetLowering &TLI) {
2181 // FP_ROUND on f64 and f32 are legal.
2182 if (Op.getOperand(0).getValueType() != MVT::f128)
2185 if (Op.getValueType() == MVT::f64)
2186 return TLI.LowerF128Op(Op, DAG,
2187 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2188 if (Op.getValueType() == MVT::f32)
2189 return TLI.LowerF128Op(Op, DAG,
2190 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2192 llvm_unreachable("fpround to non-float!");
2196 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2197 const SparcTargetLowering &TLI,
2200 EVT VT = Op.getValueType();
2201 assert(VT == MVT::i32 || VT == MVT::i64);
2203 // Expand f128 operations to fp128 abi calls.
2204 if (Op.getOperand(0).getValueType() == MVT::f128
2205 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2206 const char *libName = TLI.getLibcallName(VT == MVT::i32
2207 ? RTLIB::FPTOSINT_F128_I32
2208 : RTLIB::FPTOSINT_F128_I64);
2209 return TLI.LowerF128Op(Op, DAG, libName, 1);
2212 // Expand if the resulting type is illegal.
2213 if (!TLI.isTypeLegal(VT))
2216 // Otherwise, Convert the fp value to integer in an FP register.
2218 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2220 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2222 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2225 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2226 const SparcTargetLowering &TLI,
2229 EVT OpVT = Op.getOperand(0).getValueType();
2230 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2232 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2234 // Expand f128 operations to fp128 ABI calls.
2235 if (Op.getValueType() == MVT::f128
2236 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2237 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2238 ? RTLIB::SINTTOFP_I32_F128
2239 : RTLIB::SINTTOFP_I64_F128);
2240 return TLI.LowerF128Op(Op, DAG, libName, 1);
2243 // Expand if the operand type is illegal.
2244 if (!TLI.isTypeLegal(OpVT))
2247 // Otherwise, Convert the int value to FP in an FP register.
2248 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2249 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2250 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2253 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2254 const SparcTargetLowering &TLI,
2257 EVT VT = Op.getValueType();
2259 // Expand if it does not involve f128 or the target has support for
2260 // quad floating point instructions and the resulting type is legal.
2261 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2262 (hasHardQuad && TLI.isTypeLegal(VT)))
2265 assert(VT == MVT::i32 || VT == MVT::i64);
2267 return TLI.LowerF128Op(Op, DAG,
2268 TLI.getLibcallName(VT == MVT::i32
2269 ? RTLIB::FPTOUINT_F128_I32
2270 : RTLIB::FPTOUINT_F128_I64),
2274 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2275 const SparcTargetLowering &TLI,
2278 EVT OpVT = Op.getOperand(0).getValueType();
2279 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2281 // Expand if it does not involve f128 or the target has support for
2282 // quad floating point instructions and the operand type is legal.
2283 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2286 return TLI.LowerF128Op(Op, DAG,
2287 TLI.getLibcallName(OpVT == MVT::i32
2288 ? RTLIB::UINTTOFP_I32_F128
2289 : RTLIB::UINTTOFP_I64_F128),
2293 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2294 const SparcTargetLowering &TLI,
2296 SDValue Chain = Op.getOperand(0);
2297 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2298 SDValue LHS = Op.getOperand(2);
2299 SDValue RHS = Op.getOperand(3);
2300 SDValue Dest = Op.getOperand(4);
2302 unsigned Opc, SPCC = ~0U;
2304 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2305 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2306 LookThroughSetCC(LHS, RHS, CC, SPCC);
2308 // Get the condition flag.
2309 SDValue CompareFlag;
2310 if (LHS.getValueType().isInteger()) {
2311 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2312 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2313 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2314 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2316 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2317 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2318 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2321 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2322 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2326 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2327 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2330 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2331 const SparcTargetLowering &TLI,
2333 SDValue LHS = Op.getOperand(0);
2334 SDValue RHS = Op.getOperand(1);
2335 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2336 SDValue TrueVal = Op.getOperand(2);
2337 SDValue FalseVal = Op.getOperand(3);
2339 unsigned Opc, SPCC = ~0U;
2341 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2342 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2343 LookThroughSetCC(LHS, RHS, CC, SPCC);
2345 SDValue CompareFlag;
2346 if (LHS.getValueType().isInteger()) {
2347 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2348 Opc = LHS.getValueType() == MVT::i32 ?
2349 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2350 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2352 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2353 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2354 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2355 Opc = SPISD::SELECT_ICC;
2357 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2358 Opc = SPISD::SELECT_FCC;
2359 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2362 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2363 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2366 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2367 const SparcTargetLowering &TLI) {
2368 MachineFunction &MF = DAG.getMachineFunction();
2369 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2370 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2372 // Need frame address to find the address of VarArgsFrameIndex.
2373 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2375 // vastart just stores the address of the VarArgsFrameIndex slot into the
2376 // memory location argument.
2379 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2380 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2381 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2382 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2383 MachinePointerInfo(SV), false, false, 0);
2386 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2387 SDNode *Node = Op.getNode();
2388 EVT VT = Node->getValueType(0);
2389 SDValue InChain = Node->getOperand(0);
2390 SDValue VAListPtr = Node->getOperand(1);
2391 EVT PtrVT = VAListPtr.getValueType();
2392 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2394 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2395 MachinePointerInfo(SV), false, false, false, 0);
2396 // Increment the pointer, VAList, to the next vaarg.
2397 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2398 DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2400 // Store the incremented VAList to the legalized pointer.
2401 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2402 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2403 // Load the actual argument out of the pointer VAList.
2404 // We can't count on greater alignment than the word size.
2405 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2406 false, false, false,
2407 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2410 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2411 const SparcSubtarget *Subtarget) {
2412 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2413 SDValue Size = Op.getOperand(1); // Legalize the size.
2414 EVT VT = Size->getValueType(0);
2417 unsigned SPReg = SP::O6;
2418 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2419 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2420 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2422 // The resultant pointer is actually 16 words from the bottom of the stack,
2423 // to provide a register spill area.
2424 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2425 regSpillArea += Subtarget->getStackPointerBias();
2427 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2428 DAG.getConstant(regSpillArea, dl, VT));
2429 SDValue Ops[2] = { NewVal, Chain };
2430 return DAG.getMergeValues(Ops, dl);
2434 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2436 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2437 dl, MVT::Other, DAG.getEntryNode());
2441 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2442 const SparcSubtarget *Subtarget) {
2443 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2444 MFI->setFrameAddressIsTaken(true);
2446 EVT VT = Op.getValueType();
2448 unsigned FrameReg = SP::I6;
2449 unsigned stackBias = Subtarget->getStackPointerBias();
2454 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2455 if (Subtarget->is64Bit())
2456 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2457 DAG.getIntPtrConstant(stackBias, dl));
2461 // flush first to make sure the windowed registers' values are in stack
2462 SDValue Chain = getFLUSHW(Op, DAG);
2463 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2465 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2468 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2469 DAG.getIntPtrConstant(Offset, dl));
2470 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2471 false, false, false, 0);
2473 if (Subtarget->is64Bit())
2474 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2475 DAG.getIntPtrConstant(stackBias, dl));
2480 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2481 const SparcSubtarget *Subtarget) {
2483 uint64_t depth = Op.getConstantOperandVal(0);
2485 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2489 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2490 const SparcTargetLowering &TLI,
2491 const SparcSubtarget *Subtarget) {
2492 MachineFunction &MF = DAG.getMachineFunction();
2493 MachineFrameInfo *MFI = MF.getFrameInfo();
2494 MFI->setReturnAddressIsTaken(true);
2496 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2499 EVT VT = Op.getValueType();
2501 uint64_t depth = Op.getConstantOperandVal(0);
2505 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2506 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2507 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2511 // Need frame address to find return address of the caller.
2512 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2514 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2515 SDValue Ptr = DAG.getNode(ISD::ADD,
2518 DAG.getIntPtrConstant(Offset, dl));
2519 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2520 MachinePointerInfo(), false, false, false, 0);
2525 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2529 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2530 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2532 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2533 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2534 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2536 SDValue SrcReg64 = Op.getOperand(0);
2537 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2539 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2542 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2544 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2546 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2548 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2553 // Lower a f128 load into two f64 loads.
2554 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2557 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2558 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2559 && "Unexpected node type");
2561 unsigned alignment = LdNode->getAlignment();
2565 SDValue Hi64 = DAG.getLoad(MVT::f64,
2568 LdNode->getBasePtr(),
2569 LdNode->getPointerInfo(),
2570 false, false, false, alignment);
2571 EVT addrVT = LdNode->getBasePtr().getValueType();
2572 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2573 LdNode->getBasePtr(),
2574 DAG.getConstant(8, dl, addrVT));
2575 SDValue Lo64 = DAG.getLoad(MVT::f64,
2579 LdNode->getPointerInfo(),
2580 false, false, false, alignment);
2582 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2583 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2585 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2587 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2589 SDValue(InFP128, 0),
2592 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2594 SDValue(InFP128, 0),
2597 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2598 SDValue(Lo64.getNode(), 1) };
2599 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2600 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2601 return DAG.getMergeValues(Ops, dl);
2604 // Lower a f128 store into two f64 stores.
2605 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2607 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2608 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2609 && "Unexpected node type");
2610 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2611 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2613 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2618 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2624 unsigned alignment = StNode->getAlignment();
2628 SDValue OutChains[2];
2629 OutChains[0] = DAG.getStore(StNode->getChain(),
2632 StNode->getBasePtr(),
2633 MachinePointerInfo(),
2634 false, false, alignment);
2635 EVT addrVT = StNode->getBasePtr().getValueType();
2636 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2637 StNode->getBasePtr(),
2638 DAG.getConstant(8, dl, addrVT));
2639 OutChains[1] = DAG.getStore(StNode->getChain(),
2643 MachinePointerInfo(),
2644 false, false, alignment);
2645 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2648 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2649 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2650 && "invalid opcode");
2652 if (Op.getValueType() == MVT::f64)
2653 return LowerF64Op(Op, DAG, Op.getOpcode());
2654 if (Op.getValueType() != MVT::f128)
2657 // Lower fabs/fneg on f128 to fabs/fneg on f64
2658 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2661 SDValue SrcReg128 = Op.getOperand(0);
2662 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2664 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2667 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2669 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
2671 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2673 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2675 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2680 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2682 if (Op.getValueType() != MVT::i64)
2686 SDValue Src1 = Op.getOperand(0);
2687 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2688 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2689 DAG.getConstant(32, dl, MVT::i64));
2690 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2692 SDValue Src2 = Op.getOperand(1);
2693 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2694 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2695 DAG.getConstant(32, dl, MVT::i64));
2696 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2699 bool hasChain = false;
2700 unsigned hiOpc = Op.getOpcode();
2701 switch (Op.getOpcode()) {
2702 default: llvm_unreachable("Invalid opcode");
2703 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2704 case ISD::ADDE: hasChain = true; break;
2705 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2706 case ISD::SUBE: hasChain = true; break;
2709 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2711 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2714 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2716 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2717 SDValue Carry = Hi.getValue(1);
2719 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2720 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2721 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2722 DAG.getConstant(32, dl, MVT::i64));
2724 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2725 SDValue Ops[2] = { Dst, Carry };
2726 return DAG.getMergeValues(Ops, dl);
2729 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2730 // in LegalizeDAG.cpp except the order of arguments to the library function.
2731 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2732 const SparcTargetLowering &TLI)
2734 unsigned opcode = Op.getOpcode();
2735 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2737 bool isSigned = (opcode == ISD::SMULO);
2739 EVT WideVT = MVT::i128;
2741 SDValue LHS = Op.getOperand(0);
2743 if (LHS.getValueType() != VT)
2746 SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2748 SDValue RHS = Op.getOperand(1);
2749 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2750 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2751 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2753 SDValue MulResult = TLI.makeLibCall(DAG,
2754 RTLIB::MUL_I128, WideVT,
2755 Args, 4, isSigned, dl).first;
2756 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2757 MulResult, DAG.getIntPtrConstant(0, dl));
2758 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2759 MulResult, DAG.getIntPtrConstant(1, dl));
2761 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2762 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2764 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
2767 // MulResult is a node with an illegal type. Because such things are not
2768 // generally permitted during this phase of legalization, ensure that
2769 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2771 assert(MulResult->use_empty() && "Illegally typed node still in use!");
2773 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2774 return DAG.getMergeValues(Ops, dl);
2777 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2778 // Monotonic load/stores are legal.
2779 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2782 // Otherwise, expand with a fence.
2787 SDValue SparcTargetLowering::
2788 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2790 bool hasHardQuad = Subtarget->hasHardQuad();
2791 bool isV9 = Subtarget->isV9();
2793 switch (Op.getOpcode()) {
2794 default: llvm_unreachable("Should not custom lower this!");
2796 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2798 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2800 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2801 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2802 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2803 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2804 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2806 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2808 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2810 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2812 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2814 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2816 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2817 case ISD::VAARG: return LowerVAARG(Op, DAG);
2818 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2821 case ISD::LOAD: return LowerF128Load(Op, DAG);
2822 case ISD::STORE: return LowerF128Store(Op, DAG);
2823 case ISD::FADD: return LowerF128Op(Op, DAG,
2824 getLibcallName(RTLIB::ADD_F128), 2);
2825 case ISD::FSUB: return LowerF128Op(Op, DAG,
2826 getLibcallName(RTLIB::SUB_F128), 2);
2827 case ISD::FMUL: return LowerF128Op(Op, DAG,
2828 getLibcallName(RTLIB::MUL_F128), 2);
2829 case ISD::FDIV: return LowerF128Op(Op, DAG,
2830 getLibcallName(RTLIB::DIV_F128), 2);
2831 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2832 getLibcallName(RTLIB::SQRT_F128),1);
2834 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
2835 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2836 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2840 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2842 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2843 case ISD::ATOMIC_LOAD:
2844 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2849 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2850 MachineBasicBlock *BB) const {
2851 switch (MI->getOpcode()) {
2852 default: llvm_unreachable("Unknown SELECT_CC!");
2853 case SP::SELECT_CC_Int_ICC:
2854 case SP::SELECT_CC_FP_ICC:
2855 case SP::SELECT_CC_DFP_ICC:
2856 case SP::SELECT_CC_QFP_ICC:
2857 return expandSelectCC(MI, BB, SP::BCOND);
2858 case SP::SELECT_CC_Int_FCC:
2859 case SP::SELECT_CC_FP_FCC:
2860 case SP::SELECT_CC_DFP_FCC:
2861 case SP::SELECT_CC_QFP_FCC:
2862 return expandSelectCC(MI, BB, SP::FBCOND);
2864 case SP::ATOMIC_LOAD_ADD_32:
2865 return expandAtomicRMW(MI, BB, SP::ADDrr);
2866 case SP::ATOMIC_LOAD_ADD_64:
2867 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2868 case SP::ATOMIC_LOAD_SUB_32:
2869 return expandAtomicRMW(MI, BB, SP::SUBrr);
2870 case SP::ATOMIC_LOAD_SUB_64:
2871 return expandAtomicRMW(MI, BB, SP::SUBXrr);
2872 case SP::ATOMIC_LOAD_AND_32:
2873 return expandAtomicRMW(MI, BB, SP::ANDrr);
2874 case SP::ATOMIC_LOAD_AND_64:
2875 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2876 case SP::ATOMIC_LOAD_OR_32:
2877 return expandAtomicRMW(MI, BB, SP::ORrr);
2878 case SP::ATOMIC_LOAD_OR_64:
2879 return expandAtomicRMW(MI, BB, SP::ORXrr);
2880 case SP::ATOMIC_LOAD_XOR_32:
2881 return expandAtomicRMW(MI, BB, SP::XORrr);
2882 case SP::ATOMIC_LOAD_XOR_64:
2883 return expandAtomicRMW(MI, BB, SP::XORXrr);
2884 case SP::ATOMIC_LOAD_NAND_32:
2885 return expandAtomicRMW(MI, BB, SP::ANDrr);
2886 case SP::ATOMIC_LOAD_NAND_64:
2887 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2889 case SP::ATOMIC_SWAP_64:
2890 return expandAtomicRMW(MI, BB, 0);
2892 case SP::ATOMIC_LOAD_MAX_32:
2893 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2894 case SP::ATOMIC_LOAD_MAX_64:
2895 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2896 case SP::ATOMIC_LOAD_MIN_32:
2897 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2898 case SP::ATOMIC_LOAD_MIN_64:
2899 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2900 case SP::ATOMIC_LOAD_UMAX_32:
2901 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2902 case SP::ATOMIC_LOAD_UMAX_64:
2903 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2904 case SP::ATOMIC_LOAD_UMIN_32:
2905 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2906 case SP::ATOMIC_LOAD_UMIN_64:
2907 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2912 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
2913 MachineBasicBlock *BB,
2914 unsigned BROpcode) const {
2915 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2916 DebugLoc dl = MI->getDebugLoc();
2917 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2919 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2920 // control-flow pattern. The incoming instruction knows the destination vreg
2921 // to set, the condition code register to branch on, the true/false values to
2922 // select between, and a branch opcode to use.
2923 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2924 MachineFunction::iterator It = BB;
2931 // fallthrough --> copy0MBB
2932 MachineBasicBlock *thisMBB = BB;
2933 MachineFunction *F = BB->getParent();
2934 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2935 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2936 F->insert(It, copy0MBB);
2937 F->insert(It, sinkMBB);
2939 // Transfer the remainder of BB and its successor edges to sinkMBB.
2940 sinkMBB->splice(sinkMBB->begin(), BB,
2941 std::next(MachineBasicBlock::iterator(MI)),
2943 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2945 // Add the true and fallthrough blocks as its successors.
2946 BB->addSuccessor(copy0MBB);
2947 BB->addSuccessor(sinkMBB);
2949 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2952 // %FalseValue = ...
2953 // # fallthrough to sinkMBB
2956 // Update machine-CFG edges
2957 BB->addSuccessor(sinkMBB);
2960 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2963 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2964 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2965 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2967 MI->eraseFromParent(); // The pseudo instruction is gone now.
2972 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
2973 MachineBasicBlock *MBB,
2975 unsigned CondCode) const {
2976 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2977 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2978 DebugLoc DL = MI->getDebugLoc();
2980 // MI is an atomic read-modify-write instruction of the form:
2982 // rd = atomicrmw<op> addr, rs2
2984 // All three operands are registers.
2985 unsigned DestReg = MI->getOperand(0).getReg();
2986 unsigned AddrReg = MI->getOperand(1).getReg();
2987 unsigned Rs2Reg = MI->getOperand(2).getReg();
2989 // SelectionDAG has already inserted memory barriers before and after MI, so
2990 // we simply have to implement the operatiuon in terms of compare-and-swap.
2992 // %val0 = load %addr
2994 // %val = phi %val0, %dest
2995 // %upd = op %val, %rs2
2996 // %dest = cas %addr, %val, %upd
3001 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
3002 const TargetRegisterClass *ValueRC =
3003 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
3004 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
3006 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3007 .addReg(AddrReg).addImm(0);
3009 // Split the basic block MBB before MI and insert the loop block in the hole.
3010 MachineFunction::iterator MFI = MBB;
3011 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3012 MachineFunction *MF = MBB->getParent();
3013 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3014 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3016 MF->insert(MFI, LoopMBB);
3017 MF->insert(MFI, DoneMBB);
3019 // Move MI and following instructions to DoneMBB.
3020 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3021 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3023 // Connect the CFG again.
3024 MBB->addSuccessor(LoopMBB);
3025 LoopMBB->addSuccessor(LoopMBB);
3026 LoopMBB->addSuccessor(DoneMBB);
3028 // Build the loop block.
3029 unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3030 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3031 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3033 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3034 .addReg(Val0Reg).addMBB(MBB)
3035 .addReg(DestReg).addMBB(LoopMBB);
3038 // This is one of the min/max operations. We need a CMPrr followed by a
3040 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3041 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3042 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3043 } else if (Opcode) {
3044 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3045 .addReg(ValReg).addReg(Rs2Reg);
3048 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3049 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3050 unsigned TmpReg = UpdReg;
3051 UpdReg = MRI.createVirtualRegister(ValueRC);
3052 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3055 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3056 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3057 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3058 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3059 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3060 .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3062 MI->eraseFromParent();
3066 //===----------------------------------------------------------------------===//
3067 // Sparc Inline Assembly Support
3068 //===----------------------------------------------------------------------===//
3070 /// getConstraintType - Given a constraint letter, return the type of
3071 /// constraint it is for this target.
3072 SparcTargetLowering::ConstraintType
3073 SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3074 if (Constraint.size() == 1) {
3075 switch (Constraint[0]) {
3077 case 'r': return C_RegisterClass;
3083 return TargetLowering::getConstraintType(Constraint);
3086 TargetLowering::ConstraintWeight SparcTargetLowering::
3087 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3088 const char *constraint) const {
3089 ConstraintWeight weight = CW_Invalid;
3090 Value *CallOperandVal = info.CallOperandVal;
3091 // If we don't have a value, we can't do a match,
3092 // but allow it at the lowest weight.
3093 if (!CallOperandVal)
3096 // Look at the constraint type.
3097 switch (*constraint) {
3099 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3102 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3103 if (isInt<13>(C->getSExtValue()))
3104 weight = CW_Constant;
3111 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3112 /// vector. If it is invalid, don't add anything to Ops.
3113 void SparcTargetLowering::
3114 LowerAsmOperandForConstraint(SDValue Op,
3115 std::string &Constraint,
3116 std::vector<SDValue> &Ops,
3117 SelectionDAG &DAG) const {
3118 SDValue Result(nullptr, 0);
3120 // Only support length 1 constraints for now.
3121 if (Constraint.length() > 1)
3124 char ConstraintLetter = Constraint[0];
3125 switch (ConstraintLetter) {
3128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3129 if (isInt<13>(C->getSExtValue())) {
3130 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3138 if (Result.getNode()) {
3139 Ops.push_back(Result);
3142 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3145 std::pair<unsigned, const TargetRegisterClass *>
3146 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3147 StringRef Constraint,
3149 if (Constraint.size() == 1) {
3150 switch (Constraint[0]) {
3152 return std::make_pair(0U, &SP::IntRegsRegClass);
3154 } else if (!Constraint.empty() && Constraint.size() <= 5
3155 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3156 // constraint = '{r<d>}'
3157 // Remove the braces from around the name.
3158 StringRef name(Constraint.data()+1, Constraint.size()-2);
3159 // Handle register aliases:
3164 uint64_t intVal = 0;
3165 if (name.substr(0, 1).equals("r")
3166 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3167 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3168 char regType = regTypes[intVal/8];
3169 char regIdx = '0' + (intVal % 8);
3170 char tmp[] = { '{', regType, regIdx, '}', 0 };
3171 std::string newConstraint = std::string(tmp);
3172 return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3177 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3181 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3182 // The Sparc target isn't yet aware of offsets.
3186 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3187 SmallVectorImpl<SDValue>& Results,
3188 SelectionDAG &DAG) const {
3192 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3194 switch (N->getOpcode()) {
3196 llvm_unreachable("Do not know how to custom type legalize this operation!");
3198 case ISD::FP_TO_SINT:
3199 case ISD::FP_TO_UINT:
3200 // Custom lower only if it involves f128 or i64.
3201 if (N->getOperand(0).getValueType() != MVT::f128
3202 || N->getValueType(0) != MVT::i64)
3204 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3205 ? RTLIB::FPTOSINT_F128_I64
3206 : RTLIB::FPTOUINT_F128_I64);
3208 Results.push_back(LowerF128Op(SDValue(N, 0),
3210 getLibcallName(libCall),
3214 case ISD::SINT_TO_FP:
3215 case ISD::UINT_TO_FP:
3216 // Custom lower only if it involves f128 or i64.
3217 if (N->getValueType(0) != MVT::f128
3218 || N->getOperand(0).getValueType() != MVT::i64)
3221 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3222 ? RTLIB::SINTTOFP_I64_F128
3223 : RTLIB::UINTTOFP_I64_F128);
3225 Results.push_back(LowerF128Op(SDValue(N, 0),
3227 getLibcallName(libCall),