1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcTargetMachine.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/ADT/VectorExtras.h"
28 //===----------------------------------------------------------------------===//
29 // Calling Convention Implementation
30 //===----------------------------------------------------------------------===//
32 #include "SparcGenCallingConv.inc"
34 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
35 // CCValAssign - represent the assignment of the return value to locations.
36 SmallVector<CCValAssign, 16> RVLocs;
37 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
38 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
40 // CCState - Info about the registers and stack slot.
41 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
43 // Analize return values of ISD::RET
44 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
46 // If this is the first return lowered for this function, add the regs to the
47 // liveout set for the function.
48 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
49 for (unsigned i = 0; i != RVLocs.size(); ++i)
50 if (RVLocs[i].isRegLoc())
51 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
54 SDValue Chain = Op.getOperand(0);
57 // Copy the result values into the output registers.
58 for (unsigned i = 0; i != RVLocs.size(); ++i) {
59 CCValAssign &VA = RVLocs[i];
60 assert(VA.isRegLoc() && "Can only return in registers!");
62 // ISD::RET => ret chain, (regnum1,val1), ...
63 // So i*2+1 index only the regnums.
64 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
66 // Guarantee that all emitted copies are stuck together with flags.
67 Flag = Chain.getValue(1);
71 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
72 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
75 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
76 /// either one or two GPRs, including FP values. TODO: we should pass FP values
77 /// in FP registers for fastcc functions.
79 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
80 SmallVectorImpl<SDValue> &ArgValues) {
81 MachineFunction &MF = DAG.getMachineFunction();
82 MachineRegisterInfo &RegInfo = MF.getRegInfo();
84 static const unsigned ArgRegs[] = {
85 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
88 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
89 unsigned ArgOffset = 68;
91 SDValue Root = DAG.getRoot();
92 std::vector<SDValue> OutChains;
94 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
95 MVT ObjectVT = getValueType(I->getType());
97 switch (ObjectVT.getSimpleVT()) {
98 default: assert(0 && "Unhandled argument type!");
103 if (I->use_empty()) { // Argument is dead.
104 if (CurArgReg < ArgRegEnd) ++CurArgReg;
105 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
106 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
107 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
108 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
109 SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
110 if (ObjectVT != MVT::i32) {
111 unsigned AssertOp = ISD::AssertSext;
112 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
113 DAG.getValueType(ObjectVT));
114 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
116 ArgValues.push_back(Arg);
118 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
119 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
121 if (ObjectVT == MVT::i32) {
122 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
124 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
126 // Sparc is big endian, so add an offset based on the ObjectVT.
127 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
128 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
129 DAG.getConstant(Offset, MVT::i32));
130 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
132 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
134 ArgValues.push_back(Load);
140 if (I->use_empty()) { // Argument is dead.
141 if (CurArgReg < ArgRegEnd) ++CurArgReg;
142 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
143 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
144 // FP value is passed in an integer register.
145 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
146 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
147 SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
149 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
150 ArgValues.push_back(Arg);
152 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
153 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
154 SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
155 ArgValues.push_back(Load);
162 if (I->use_empty()) { // Argument is dead.
163 if (CurArgReg < ArgRegEnd) ++CurArgReg;
164 if (CurArgReg < ArgRegEnd) ++CurArgReg;
165 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
168 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
169 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
170 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
171 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
173 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
175 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
179 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
180 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
181 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
182 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
184 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
185 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
186 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
189 // Compose the two halves together into an i64 unit.
191 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
193 // If we want a double, do a bit convert.
194 if (ObjectVT == MVT::f64)
195 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
197 ArgValues.push_back(WholeValue);
204 // Store remaining ArgRegs to the stack if this is a varargs function.
206 // Remember the vararg offset for the va_start implementation.
207 VarArgsFrameOffset = ArgOffset;
209 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
210 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
211 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
212 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
214 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
215 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
217 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
222 if (!OutChains.empty())
223 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
224 &OutChains[0], OutChains.size()));
227 static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
228 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
229 unsigned CallingConv = TheCall->getCallingConv();
230 SDValue Chain = TheCall->getChain();
231 SDValue Callee = TheCall->getCallee();
232 bool isVarArg = TheCall->isVarArg();
235 // Analyze operands of the call, assigning locations to each operand.
236 SmallVector<CCValAssign, 16> ArgLocs;
237 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
238 CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
240 // Get the size of the outgoing arguments stack space requirement.
241 unsigned ArgsSize = CCInfo.getNextStackOffset();
242 // FIXME: We can't use this until f64 is known to take two GPRs.
246 // Count the size of the outgoing arguments.
247 unsigned ArgsSize = 0;
248 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
249 switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
250 default: assert(0 && "Unknown value type!");
265 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
270 // Keep stack frames 8-byte aligned.
271 ArgsSize = (ArgsSize+7) & ~7;
273 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
275 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
276 SmallVector<SDValue, 8> MemOpChains;
279 // Walk the register/memloc assignments, inserting copies/loads.
280 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
281 CCValAssign &VA = ArgLocs[i];
283 // Arguments start after the 5 first operands of ISD::CALL
284 SDValue Arg = TheCall->getArg(i);
286 // Promote the value if needed.
287 switch (VA.getLocInfo()) {
288 default: assert(0 && "Unknown loc info!");
289 case CCValAssign::Full: break;
290 case CCValAssign::SExt:
291 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
293 case CCValAssign::ZExt:
294 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
296 case CCValAssign::AExt:
297 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
301 // Arguments that can be passed on register must be kept at
304 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
308 assert(VA.isMemLoc());
310 // Create a store off the stack pointer for this argument.
311 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
312 // FIXME: VERIFY THAT 68 IS RIGHT.
313 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
314 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
315 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
319 static const unsigned ArgRegs[] = {
320 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
322 unsigned ArgOffset = 68;
324 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
325 SDValue Val = TheCall->getArg(i);
326 MVT ObjectVT = Val.getValueType();
327 SDValue ValToStore(0, 0);
329 switch (ObjectVT.getSimpleVT()) {
330 default: assert(0 && "Unhandled argument type!");
334 if (RegsToPass.size() >= 6) {
337 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
342 if (RegsToPass.size() >= 6) {
345 // Convert this to a FP value in an int reg.
346 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
347 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
352 // Otherwise, convert this to a FP value in int regs.
353 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
357 if (RegsToPass.size() >= 6) {
358 ValToStore = Val; // Whole thing is passed in memory.
362 // Split the value into top and bottom part. Top part goes in a reg.
363 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
364 DAG.getConstant(1, MVT::i32));
365 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
366 DAG.getConstant(0, MVT::i32));
367 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
369 if (RegsToPass.size() >= 6) {
374 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
379 if (ValToStore.getNode()) {
380 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
381 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
382 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
383 MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
385 ArgOffset += ObjSize;
389 // Emit all stores, make sure the occur before any copies into physregs.
390 if (!MemOpChains.empty())
391 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
392 &MemOpChains[0], MemOpChains.size());
394 // Build a sequence of copy-to-reg nodes chained together with token
395 // chain and flag operands which copy the outgoing args into registers.
396 // The InFlag in necessary since all emited instructions must be
399 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
400 unsigned Reg = RegsToPass[i].first;
401 // Remap I0->I7 -> O0->O7.
402 if (Reg >= SP::I0 && Reg <= SP::I7)
403 Reg = Reg-SP::I0+SP::O0;
405 Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag);
406 InFlag = Chain.getValue(1);
409 // If the callee is a GlobalAddress node (quite common, every direct call is)
410 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
411 // Likewise ExternalSymbol -> TargetExternalSymbol.
412 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
413 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
414 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
415 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
417 std::vector<MVT> NodeTys;
418 NodeTys.push_back(MVT::Other); // Returns a chain
419 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
420 SDValue Ops[] = { Chain, Callee, InFlag };
421 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
422 InFlag = Chain.getValue(1);
424 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
425 DAG.getIntPtrConstant(0, true), InFlag);
426 InFlag = Chain.getValue(1);
428 // Assign locations to each value returned by this call.
429 SmallVector<CCValAssign, 16> RVLocs;
430 CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
432 RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
433 SmallVector<SDValue, 8> ResultVals;
435 // Copy all of the result registers out of their specified physreg.
436 for (unsigned i = 0; i != RVLocs.size(); ++i) {
437 unsigned Reg = RVLocs[i].getLocReg();
439 // Remap I0->I7 -> O0->O7.
440 if (Reg >= SP::I0 && Reg <= SP::I7)
441 Reg = Reg-SP::I0+SP::O0;
443 Chain = DAG.getCopyFromReg(Chain, Reg,
444 RVLocs[i].getValVT(), InFlag).getValue(1);
445 InFlag = Chain.getValue(2);
446 ResultVals.push_back(Chain.getValue(0));
449 ResultVals.push_back(Chain);
451 // Merge everything together with a MERGE_VALUES node.
452 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
458 //===----------------------------------------------------------------------===//
459 // TargetLowering Implementation
460 //===----------------------------------------------------------------------===//
462 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
464 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
466 default: assert(0 && "Unknown integer condition code!");
467 case ISD::SETEQ: return SPCC::ICC_E;
468 case ISD::SETNE: return SPCC::ICC_NE;
469 case ISD::SETLT: return SPCC::ICC_L;
470 case ISD::SETGT: return SPCC::ICC_G;
471 case ISD::SETLE: return SPCC::ICC_LE;
472 case ISD::SETGE: return SPCC::ICC_GE;
473 case ISD::SETULT: return SPCC::ICC_CS;
474 case ISD::SETULE: return SPCC::ICC_LEU;
475 case ISD::SETUGT: return SPCC::ICC_GU;
476 case ISD::SETUGE: return SPCC::ICC_CC;
480 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
482 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
484 default: assert(0 && "Unknown fp condition code!");
486 case ISD::SETOEQ: return SPCC::FCC_E;
488 case ISD::SETUNE: return SPCC::FCC_NE;
490 case ISD::SETOLT: return SPCC::FCC_L;
492 case ISD::SETOGT: return SPCC::FCC_G;
494 case ISD::SETOLE: return SPCC::FCC_LE;
496 case ISD::SETOGE: return SPCC::FCC_GE;
497 case ISD::SETULT: return SPCC::FCC_UL;
498 case ISD::SETULE: return SPCC::FCC_ULE;
499 case ISD::SETUGT: return SPCC::FCC_UG;
500 case ISD::SETUGE: return SPCC::FCC_UGE;
501 case ISD::SETUO: return SPCC::FCC_U;
502 case ISD::SETO: return SPCC::FCC_O;
503 case ISD::SETONE: return SPCC::FCC_LG;
504 case ISD::SETUEQ: return SPCC::FCC_UE;
509 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
510 : TargetLowering(TM) {
512 // Set up the register classes.
513 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
514 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
515 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
517 // Turn FP extload into load/fextend
518 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
519 // Sparc doesn't have i1 sign extending load
520 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
521 // Turn FP truncstore into trunc + store.
522 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
524 // Custom legalize GlobalAddress nodes into LO/HI parts.
525 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
526 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
527 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
529 // Sparc doesn't have sext_inreg, replace them with shl/sra
530 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
532 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
534 // Sparc has no REM or DIVREM operations.
535 setOperationAction(ISD::UREM, MVT::i32, Expand);
536 setOperationAction(ISD::SREM, MVT::i32, Expand);
537 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
538 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
540 // Custom expand fp<->sint
541 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
542 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
545 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
546 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
548 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
549 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
551 // Sparc has no select or setcc: expand to SELECT_CC.
552 setOperationAction(ISD::SELECT, MVT::i32, Expand);
553 setOperationAction(ISD::SELECT, MVT::f32, Expand);
554 setOperationAction(ISD::SELECT, MVT::f64, Expand);
555 setOperationAction(ISD::SETCC, MVT::i32, Expand);
556 setOperationAction(ISD::SETCC, MVT::f32, Expand);
557 setOperationAction(ISD::SETCC, MVT::f64, Expand);
559 // Sparc doesn't have BRCOND either, it has BR_CC.
560 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
561 setOperationAction(ISD::BRIND, MVT::Other, Expand);
562 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
563 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
564 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
565 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
567 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
568 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
569 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
571 // SPARC has no intrinsics for these particular operations.
572 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
574 setOperationAction(ISD::FSIN , MVT::f64, Expand);
575 setOperationAction(ISD::FCOS , MVT::f64, Expand);
576 setOperationAction(ISD::FREM , MVT::f64, Expand);
577 setOperationAction(ISD::FSIN , MVT::f32, Expand);
578 setOperationAction(ISD::FCOS , MVT::f32, Expand);
579 setOperationAction(ISD::FREM , MVT::f32, Expand);
580 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
581 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
582 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
583 setOperationAction(ISD::ROTL , MVT::i32, Expand);
584 setOperationAction(ISD::ROTR , MVT::i32, Expand);
585 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
586 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
587 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
588 setOperationAction(ISD::FPOW , MVT::f64, Expand);
589 setOperationAction(ISD::FPOW , MVT::f32, Expand);
591 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
592 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
593 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
595 // FIXME: Sparc provides these multiplies, but we don't have them yet.
596 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
597 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
599 // We don't have line number support yet.
600 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
601 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
602 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
603 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
605 // RET must be custom lowered, to meet ABI requirements
606 setOperationAction(ISD::RET , MVT::Other, Custom);
608 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
609 setOperationAction(ISD::VASTART , MVT::Other, Custom);
610 // VAARG needs to be lowered to not do unaligned accesses for doubles.
611 setOperationAction(ISD::VAARG , MVT::Other, Custom);
613 // Use the default implementation.
614 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
615 setOperationAction(ISD::VAEND , MVT::Other, Expand);
616 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
617 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
618 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
620 // No debug info support yet.
621 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
622 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
623 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
624 setOperationAction(ISD::DECLARE, MVT::Other, Expand);
626 setStackPointerRegisterToSaveRestore(SP::O6);
628 if (TM.getSubtarget<SparcSubtarget>().isV9())
629 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
631 computeRegisterProperties();
634 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
637 case SPISD::CMPICC: return "SPISD::CMPICC";
638 case SPISD::CMPFCC: return "SPISD::CMPFCC";
639 case SPISD::BRICC: return "SPISD::BRICC";
640 case SPISD::BRFCC: return "SPISD::BRFCC";
641 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
642 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
643 case SPISD::Hi: return "SPISD::Hi";
644 case SPISD::Lo: return "SPISD::Lo";
645 case SPISD::FTOI: return "SPISD::FTOI";
646 case SPISD::ITOF: return "SPISD::ITOF";
647 case SPISD::CALL: return "SPISD::CALL";
648 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
652 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
653 /// be zero. Op is expected to be a target specific node. Used by DAG
655 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
659 const SelectionDAG &DAG,
660 unsigned Depth) const {
661 APInt KnownZero2, KnownOne2;
662 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
664 switch (Op.getOpcode()) {
666 case SPISD::SELECT_ICC:
667 case SPISD::SELECT_FCC:
668 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
670 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
672 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
673 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
675 // Only known if known in both the LHS and RHS.
676 KnownOne &= KnownOne2;
677 KnownZero &= KnownZero2;
682 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
683 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
684 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
685 ISD::CondCode CC, unsigned &SPCC) {
686 if (isa<ConstantSDNode>(RHS) &&
687 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
689 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
690 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
691 (LHS.getOpcode() == SPISD::SELECT_FCC &&
692 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
693 isa<ConstantSDNode>(LHS.getOperand(0)) &&
694 isa<ConstantSDNode>(LHS.getOperand(1)) &&
695 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
696 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
697 SDValue CMPCC = LHS.getOperand(3);
698 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
699 LHS = CMPCC.getOperand(0);
700 RHS = CMPCC.getOperand(1);
704 static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
705 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
706 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
707 SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
708 SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
709 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
712 static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
713 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
714 Constant *C = N->getConstVal();
715 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
716 SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
717 SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
718 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
721 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
722 // Convert the fp value to integer in an FP register.
723 assert(Op.getValueType() == MVT::i32);
724 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
725 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
728 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
729 assert(Op.getOperand(0).getValueType() == MVT::i32);
730 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
731 // Convert the int value to FP in an FP register.
732 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
735 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
736 SDValue Chain = Op.getOperand(0);
737 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
738 SDValue LHS = Op.getOperand(2);
739 SDValue RHS = Op.getOperand(3);
740 SDValue Dest = Op.getOperand(4);
741 unsigned Opc, SPCC = ~0U;
743 // If this is a br_cc of a "setcc", and if the setcc got lowered into
744 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
745 LookThroughSetCC(LHS, RHS, CC, SPCC);
747 // Get the condition flag.
749 if (LHS.getValueType() == MVT::i32) {
750 std::vector<MVT> VTs;
751 VTs.push_back(MVT::i32);
752 VTs.push_back(MVT::Flag);
753 SDValue Ops[2] = { LHS, RHS };
754 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
755 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
758 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
759 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
762 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
763 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
766 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
767 SDValue LHS = Op.getOperand(0);
768 SDValue RHS = Op.getOperand(1);
769 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
770 SDValue TrueVal = Op.getOperand(2);
771 SDValue FalseVal = Op.getOperand(3);
772 unsigned Opc, SPCC = ~0U;
774 // If this is a select_cc of a "setcc", and if the setcc got lowered into
775 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
776 LookThroughSetCC(LHS, RHS, CC, SPCC);
779 if (LHS.getValueType() == MVT::i32) {
780 std::vector<MVT> VTs;
781 VTs.push_back(LHS.getValueType()); // subcc returns a value
782 VTs.push_back(MVT::Flag);
783 SDValue Ops[2] = { LHS, RHS };
784 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
785 Opc = SPISD::SELECT_ICC;
786 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
788 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
789 Opc = SPISD::SELECT_FCC;
790 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
792 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
793 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
796 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
797 SparcTargetLowering &TLI) {
798 // vastart just stores the address of the VarArgsFrameIndex slot into the
799 // memory location argument.
800 SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32,
801 DAG.getRegister(SP::I6, MVT::i32),
802 DAG.getConstant(TLI.getVarArgsFrameOffset(),
804 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
805 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
808 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
809 SDNode *Node = Op.getNode();
810 MVT VT = Node->getValueType(0);
811 SDValue InChain = Node->getOperand(0);
812 SDValue VAListPtr = Node->getOperand(1);
813 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
814 SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
815 // Increment the pointer, VAList, to the next vaarg
816 SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
817 DAG.getConstant(VT.getSizeInBits()/8,
819 // Store the incremented VAList to the legalized pointer
820 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
822 // Load the actual argument out of the pointer VAList, unless this is an
825 return DAG.getLoad(VT, InChain, VAList, NULL, 0);
827 // Otherwise, load it as i64, then do a bitconvert.
828 SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
830 // Bit-Convert the value to f64.
832 DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
835 return DAG.getMergeValues(Ops, 2);
838 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
839 SDValue Chain = Op.getOperand(0); // Legalize the chain.
840 SDValue Size = Op.getOperand(1); // Legalize the size.
842 unsigned SPReg = SP::O6;
843 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
844 SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
845 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
847 // The resultant pointer is actually 16 words from the bottom of the stack,
848 // to provide a register spill area.
849 SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
850 DAG.getConstant(96, MVT::i32));
851 SDValue Ops[2] = { NewVal, Chain };
852 return DAG.getMergeValues(Ops, 2);
856 SDValue SparcTargetLowering::
857 LowerOperation(SDValue Op, SelectionDAG &DAG) {
858 switch (Op.getOpcode()) {
859 default: assert(0 && "Should not custom lower this!");
860 // Frame & Return address. Currently unimplemented
861 case ISD::RETURNADDR: return SDValue();
862 case ISD::FRAMEADDR: return SDValue();
863 case ISD::GlobalTLSAddress:
864 assert(0 && "TLS not implemented for Sparc.");
865 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
866 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG);
867 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
868 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
869 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
870 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
871 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
872 case ISD::VAARG: return LowerVAARG(Op, DAG);
873 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
874 case ISD::CALL: return LowerCALL(Op, DAG);
875 case ISD::RET: return LowerRET(Op, DAG);
880 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
881 MachineBasicBlock *BB) {
882 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
885 // Figure out the conditional branch opcode to use for this select_cc.
886 switch (MI->getOpcode()) {
887 default: assert(0 && "Unknown SELECT_CC!");
888 case SP::SELECT_CC_Int_ICC:
889 case SP::SELECT_CC_FP_ICC:
890 case SP::SELECT_CC_DFP_ICC:
891 BROpcode = SP::BCOND;
893 case SP::SELECT_CC_Int_FCC:
894 case SP::SELECT_CC_FP_FCC:
895 case SP::SELECT_CC_DFP_FCC:
896 BROpcode = SP::FBCOND;
900 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
902 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
903 // control-flow pattern. The incoming instruction knows the destination vreg
904 // to set, the condition code register to branch on, the true/false values to
905 // select between, and a branch opcode to use.
906 const BasicBlock *LLVM_BB = BB->getBasicBlock();
907 MachineFunction::iterator It = BB;
914 // fallthrough --> copy0MBB
915 MachineBasicBlock *thisMBB = BB;
916 MachineFunction *F = BB->getParent();
917 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
918 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
919 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
920 F->insert(It, copy0MBB);
921 F->insert(It, sinkMBB);
922 // Update machine-CFG edges by transferring all successors of the current
923 // block to the new block which will contain the Phi node for the select.
924 sinkMBB->transferSuccessors(BB);
925 // Next, add the true and fallthrough blocks as its successors.
926 BB->addSuccessor(copy0MBB);
927 BB->addSuccessor(sinkMBB);
931 // # fallthrough to sinkMBB
934 // Update machine-CFG edges
935 BB->addSuccessor(sinkMBB);
938 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
941 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
942 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
943 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
945 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
949 //===----------------------------------------------------------------------===//
950 // Sparc Inline Assembly Support
951 //===----------------------------------------------------------------------===//
953 /// getConstraintType - Given a constraint letter, return the type of
954 /// constraint it is for this target.
955 SparcTargetLowering::ConstraintType
956 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
957 if (Constraint.size() == 1) {
958 switch (Constraint[0]) {
960 case 'r': return C_RegisterClass;
964 return TargetLowering::getConstraintType(Constraint);
967 std::pair<unsigned, const TargetRegisterClass*>
968 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
970 if (Constraint.size() == 1) {
971 switch (Constraint[0]) {
973 return std::make_pair(0U, SP::IntRegsRegisterClass);
977 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
980 std::vector<unsigned> SparcTargetLowering::
981 getRegClassForInlineAsmConstraint(const std::string &Constraint,
983 if (Constraint.size() != 1)
984 return std::vector<unsigned>();
986 switch (Constraint[0]) {
989 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
990 SP::L4, SP::L5, SP::L6, SP::L7,
991 SP::I0, SP::I1, SP::I2, SP::I3,
993 SP::O0, SP::O1, SP::O2, SP::O3,
994 SP::O4, SP::O5, SP::O7, 0);
997 return std::vector<unsigned>();
1001 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1002 // The Sparc target isn't yet aware of offsets.