1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "MCTargetDesc/SparcMCExpr.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/ErrorHandling.h"
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags, CCState &State)
43 assert (ArgFlags.isSRet());
45 // Assign SRet argument.
46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
52 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags, CCState &State)
56 static const MCPhysReg RegList[] = {
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
63 // Assign whole thing in stack.
64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65 State.AllocateStack(8,4),
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75 State.AllocateStack(4,4),
80 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
82 ISD::ArgFlagsTy &ArgFlags, CCState &State)
84 static const MCPhysReg RegList[] = {
85 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
88 // Try to get first reg.
89 if (unsigned Reg = State.AllocateReg(RegList))
90 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
94 // Try to get second reg.
95 if (unsigned Reg = State.AllocateReg(RegList))
96 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
103 // Allocate a full-sized argument for the 64-bit ABI.
104 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
105 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
107 assert((LocVT == MVT::f32 || LocVT == MVT::f128
108 || LocVT.getSizeInBits() == 64) &&
109 "Can't handle non-64 bits locations");
111 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
113 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
114 unsigned Offset = State.AllocateStack(size, alignment);
117 if (LocVT == MVT::i64 && Offset < 6*8)
118 // Promote integers to %i0-%i5.
119 Reg = SP::I0 + Offset/8;
120 else if (LocVT == MVT::f64 && Offset < 16*8)
121 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
122 Reg = SP::D0 + Offset/8;
123 else if (LocVT == MVT::f32 && Offset < 16*8)
124 // Promote floats to %f1, %f3, ...
125 Reg = SP::F1 + Offset/4;
126 else if (LocVT == MVT::f128 && Offset < 16*8)
127 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
128 Reg = SP::Q0 + Offset/16;
130 // Promote to register when possible, otherwise use the stack slot.
132 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
136 // This argument goes on the stack in an 8-byte slot.
137 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
138 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
139 if (LocVT == MVT::f32)
142 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
146 // Allocate a half-sized argument for the 64-bit ABI.
148 // This is used when passing { float, int } structs by value in registers.
149 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
150 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
151 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
152 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
153 unsigned Offset = State.AllocateStack(4, 4);
155 if (LocVT == MVT::f32 && Offset < 16*8) {
156 // Promote floats to %f0-%f31.
157 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
162 if (LocVT == MVT::i32 && Offset < 6*8) {
163 // Promote integers to %i0-%i5, using half the register.
164 unsigned Reg = SP::I0 + Offset/8;
166 LocInfo = CCValAssign::AExt;
168 // Set the Custom bit if this i32 goes in the high bits of a register.
170 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
173 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
177 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
181 #include "SparcGenCallingConv.inc"
183 // The calling conventions in SparcCallingConv.td are described in terms of the
184 // callee's register window. This function translates registers to the
185 // corresponding caller window %o register.
186 static unsigned toCallerWindow(unsigned Reg) {
187 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
188 if (Reg >= SP::I0 && Reg <= SP::I7)
189 return Reg - SP::I0 + SP::O0;
194 SparcTargetLowering::LowerReturn(SDValue Chain,
195 CallingConv::ID CallConv, bool IsVarArg,
196 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 const SmallVectorImpl<SDValue> &OutVals,
198 SDLoc DL, SelectionDAG &DAG) const {
199 if (Subtarget->is64Bit())
200 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
201 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
205 SparcTargetLowering::LowerReturn_32(SDValue Chain,
206 CallingConv::ID CallConv, bool IsVarArg,
207 const SmallVectorImpl<ISD::OutputArg> &Outs,
208 const SmallVectorImpl<SDValue> &OutVals,
209 SDLoc DL, SelectionDAG &DAG) const {
210 MachineFunction &MF = DAG.getMachineFunction();
212 // CCValAssign - represent the assignment of the return value to locations.
213 SmallVector<CCValAssign, 16> RVLocs;
215 // CCState - Info about the registers and stack slot.
216 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
219 // Analyze return values.
220 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
223 SmallVector<SDValue, 4> RetOps(1, Chain);
224 // Make room for the return address offset.
225 RetOps.push_back(SDValue());
227 // Copy the result values into the output registers.
228 for (unsigned i = 0, realRVLocIdx = 0;
230 ++i, ++realRVLocIdx) {
231 CCValAssign &VA = RVLocs[i];
232 assert(VA.isRegLoc() && "Can only return in registers!");
234 SDValue Arg = OutVals[realRVLocIdx];
236 if (VA.needsCustom()) {
237 assert(VA.getLocVT() == MVT::v2i32);
238 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
239 // happen by default if this wasn't a legal type)
241 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
243 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
244 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
246 DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout())));
248 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
249 Flag = Chain.getValue(1);
250 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
251 VA = RVLocs[++i]; // skip ahead to next loc
252 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
257 // Guarantee that all emitted copies are stuck together with flags.
258 Flag = Chain.getValue(1);
259 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
262 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
263 // If the function returns a struct, copy the SRetReturnReg to I0
264 if (MF.getFunction()->hasStructRetAttr()) {
265 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
266 unsigned Reg = SFI->getSRetReturnReg();
268 llvm_unreachable("sret virtual register not created in the entry block");
269 auto PtrVT = getPointerTy(DAG.getDataLayout());
270 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
271 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
272 Flag = Chain.getValue(1);
273 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
274 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
277 RetOps[0] = Chain; // Update chain.
278 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
280 // Add the flag if we have it.
282 RetOps.push_back(Flag);
284 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
287 // Lower return values for the 64-bit ABI.
288 // Return values are passed the exactly the same way as function arguments.
290 SparcTargetLowering::LowerReturn_64(SDValue Chain,
291 CallingConv::ID CallConv, bool IsVarArg,
292 const SmallVectorImpl<ISD::OutputArg> &Outs,
293 const SmallVectorImpl<SDValue> &OutVals,
294 SDLoc DL, SelectionDAG &DAG) const {
295 // CCValAssign - represent the assignment of the return value to locations.
296 SmallVector<CCValAssign, 16> RVLocs;
298 // CCState - Info about the registers and stack slot.
299 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
302 // Analyze return values.
303 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
306 SmallVector<SDValue, 4> RetOps(1, Chain);
308 // The second operand on the return instruction is the return address offset.
309 // The return address is always %i7+8 with the 64-bit ABI.
310 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
312 // Copy the result values into the output registers.
313 for (unsigned i = 0; i != RVLocs.size(); ++i) {
314 CCValAssign &VA = RVLocs[i];
315 assert(VA.isRegLoc() && "Can only return in registers!");
316 SDValue OutVal = OutVals[i];
318 // Integer return values must be sign or zero extended by the callee.
319 switch (VA.getLocInfo()) {
320 case CCValAssign::Full: break;
321 case CCValAssign::SExt:
322 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
324 case CCValAssign::ZExt:
325 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
327 case CCValAssign::AExt:
328 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
331 llvm_unreachable("Unknown loc info!");
334 // The custom bit on an i32 return value indicates that it should be passed
335 // in the high bits of the register.
336 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
337 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
338 DAG.getConstant(32, DL, MVT::i32));
340 // The next value may go in the low bits of the same register.
341 // Handle both at once.
342 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
343 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
344 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
345 // Skip the next value, it's already done.
350 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
352 // Guarantee that all emitted copies are stuck together with flags.
353 Flag = Chain.getValue(1);
354 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
357 RetOps[0] = Chain; // Update chain.
359 // Add the flag if we have it.
361 RetOps.push_back(Flag);
363 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
366 SDValue SparcTargetLowering::
367 LowerFormalArguments(SDValue Chain,
368 CallingConv::ID CallConv,
370 const SmallVectorImpl<ISD::InputArg> &Ins,
373 SmallVectorImpl<SDValue> &InVals) const {
374 if (Subtarget->is64Bit())
375 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
377 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
381 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
382 /// passed in either one or two GPRs, including FP values. TODO: we should
383 /// pass FP values in FP registers for fastcc functions.
384 SDValue SparcTargetLowering::
385 LowerFormalArguments_32(SDValue Chain,
386 CallingConv::ID CallConv,
388 const SmallVectorImpl<ISD::InputArg> &Ins,
391 SmallVectorImpl<SDValue> &InVals) const {
392 MachineFunction &MF = DAG.getMachineFunction();
393 MachineRegisterInfo &RegInfo = MF.getRegInfo();
394 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
396 // Assign locations to all of the incoming arguments.
397 SmallVector<CCValAssign, 16> ArgLocs;
398 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
400 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
402 const unsigned StackOffset = 92;
405 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
406 CCValAssign &VA = ArgLocs[i];
408 if (Ins[InIdx].Flags.isSRet()) {
410 report_fatal_error("sparc only supports sret on the first parameter");
411 // Get SRet from [%fp+64].
412 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
413 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
414 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
415 MachinePointerInfo(),
416 false, false, false, 0);
417 InVals.push_back(Arg);
422 if (VA.needsCustom()) {
423 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
425 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
426 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
427 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
430 CCValAssign &NextVA = ArgLocs[++i];
433 if (NextVA.isMemLoc()) {
434 int FrameIdx = MF.getFrameInfo()->
435 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
436 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
437 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
438 MachinePointerInfo(),
439 false, false, false, 0);
441 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
442 &SP::IntRegsRegClass);
443 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
446 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
447 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
448 InVals.push_back(WholeValue);
451 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
452 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
453 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
454 if (VA.getLocVT() == MVT::f32)
455 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
456 else if (VA.getLocVT() != MVT::i32) {
457 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
458 DAG.getValueType(VA.getLocVT()));
459 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
461 InVals.push_back(Arg);
465 assert(VA.isMemLoc());
467 unsigned Offset = VA.getLocMemOffset()+StackOffset;
468 auto PtrVT = getPointerTy(DAG.getDataLayout());
470 if (VA.needsCustom()) {
471 assert(VA.getValVT() == MVT::f64 || MVT::v2i32);
472 // If it is double-word aligned, just load.
473 if (Offset % 8 == 0) {
474 int FI = MF.getFrameInfo()->CreateFixedObject(8,
477 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
478 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
479 MachinePointerInfo(),
480 false,false, false, 0);
481 InVals.push_back(Load);
485 int FI = MF.getFrameInfo()->CreateFixedObject(4,
488 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
489 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
490 MachinePointerInfo(),
491 false, false, false, 0);
492 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
495 SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
497 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
498 MachinePointerInfo(),
499 false, false, false, 0);
502 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
503 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
504 InVals.push_back(WholeValue);
508 int FI = MF.getFrameInfo()->CreateFixedObject(4,
511 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
513 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
514 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
515 MachinePointerInfo(),
516 false, false, false, 0);
518 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
519 // Sparc is big endian, so add an offset based on the ObjectVT.
520 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
521 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
522 DAG.getConstant(Offset, dl, MVT::i32));
523 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
524 MachinePointerInfo(),
525 VA.getValVT(), false, false, false,0);
526 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
528 InVals.push_back(Load);
531 if (MF.getFunction()->hasStructRetAttr()) {
532 // Copy the SRet Argument to SRetReturnReg.
533 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
534 unsigned Reg = SFI->getSRetReturnReg();
536 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
537 SFI->setSRetReturnReg(Reg);
539 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
540 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
543 // Store remaining ArgRegs to the stack if this is a varargs function.
545 static const MCPhysReg ArgRegs[] = {
546 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
548 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
549 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
550 unsigned ArgOffset = CCInfo.getNextStackOffset();
551 if (NumAllocated == 6)
552 ArgOffset += StackOffset;
555 ArgOffset = 68+4*NumAllocated;
558 // Remember the vararg offset for the va_start implementation.
559 FuncInfo->setVarArgsFrameOffset(ArgOffset);
561 std::vector<SDValue> OutChains;
563 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
564 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
565 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
566 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
568 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
570 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
572 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
573 MachinePointerInfo(),
578 if (!OutChains.empty()) {
579 OutChains.push_back(Chain);
580 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
587 // Lower formal arguments for the 64 bit ABI.
588 SDValue SparcTargetLowering::
589 LowerFormalArguments_64(SDValue Chain,
590 CallingConv::ID CallConv,
592 const SmallVectorImpl<ISD::InputArg> &Ins,
595 SmallVectorImpl<SDValue> &InVals) const {
596 MachineFunction &MF = DAG.getMachineFunction();
598 // Analyze arguments according to CC_Sparc64.
599 SmallVector<CCValAssign, 16> ArgLocs;
600 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
602 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
604 // The argument array begins at %fp+BIAS+128, after the register save area.
605 const unsigned ArgArea = 128;
607 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
608 CCValAssign &VA = ArgLocs[i];
610 // This argument is passed in a register.
611 // All integer register arguments are promoted by the caller to i64.
613 // Create a virtual register for the promoted live-in value.
614 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
615 getRegClassFor(VA.getLocVT()));
616 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
618 // Get the high bits for i32 struct elements.
619 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
620 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
621 DAG.getConstant(32, DL, MVT::i32));
623 // The caller promoted the argument, so insert an Assert?ext SDNode so we
624 // won't promote the value again in this function.
625 switch (VA.getLocInfo()) {
626 case CCValAssign::SExt:
627 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
628 DAG.getValueType(VA.getValVT()));
630 case CCValAssign::ZExt:
631 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
632 DAG.getValueType(VA.getValVT()));
638 // Truncate the register down to the argument type.
640 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
642 InVals.push_back(Arg);
646 // The registers are exhausted. This argument was passed on the stack.
647 assert(VA.isMemLoc());
648 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
649 // beginning of the arguments area at %fp+BIAS+128.
650 unsigned Offset = VA.getLocMemOffset() + ArgArea;
651 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
652 // Adjust offset for extended arguments, SPARC is big-endian.
653 // The caller will have written the full slot with extended bytes, but we
654 // prefer our own extending loads.
656 Offset += 8 - ValSize;
657 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
658 InVals.push_back(DAG.getLoad(
659 VA.getValVT(), DL, Chain,
660 DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),
661 MachinePointerInfo::getFixedStack(MF, FI), false, false, false, 0));
667 // This function takes variable arguments, some of which may have been passed
668 // in registers %i0-%i5. Variable floating point arguments are never passed
669 // in floating point registers. They go on %i0-%i5 or on the stack like
670 // integer arguments.
672 // The va_start intrinsic needs to know the offset to the first variable
674 unsigned ArgOffset = CCInfo.getNextStackOffset();
675 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
676 // Skip the 128 bytes of register save area.
677 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
678 Subtarget->getStackPointerBias());
680 // Save the variable arguments that were passed in registers.
681 // The caller is required to reserve stack space for 6 arguments regardless
682 // of how many arguments were actually passed.
683 SmallVector<SDValue, 8> OutChains;
684 for (; ArgOffset < 6*8; ArgOffset += 8) {
685 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
686 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
687 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
688 auto PtrVT = getPointerTy(MF.getDataLayout());
689 OutChains.push_back(DAG.getStore(
690 Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
691 MachinePointerInfo::getFixedStack(MF, FI), false, false, 0));
694 if (!OutChains.empty())
695 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
701 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
702 SmallVectorImpl<SDValue> &InVals) const {
703 if (Subtarget->is64Bit())
704 return LowerCall_64(CLI, InVals);
705 return LowerCall_32(CLI, InVals);
708 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
709 ImmutableCallSite *CS) {
711 return CS->hasFnAttr(Attribute::ReturnsTwice);
713 const Function *CalleeFn = nullptr;
714 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
715 CalleeFn = dyn_cast<Function>(G->getGlobal());
716 } else if (ExternalSymbolSDNode *E =
717 dyn_cast<ExternalSymbolSDNode>(Callee)) {
718 const Function *Fn = DAG.getMachineFunction().getFunction();
719 const Module *M = Fn->getParent();
720 const char *CalleeName = E->getSymbol();
721 CalleeFn = M->getFunction(CalleeName);
726 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
729 // Lower a call for the 32-bit ABI.
731 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
732 SmallVectorImpl<SDValue> &InVals) const {
733 SelectionDAG &DAG = CLI.DAG;
735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
738 SDValue Chain = CLI.Chain;
739 SDValue Callee = CLI.Callee;
740 bool &isTailCall = CLI.IsTailCall;
741 CallingConv::ID CallConv = CLI.CallConv;
742 bool isVarArg = CLI.IsVarArg;
744 // Sparc target does not yet support tail call optimization.
747 // Analyze operands of the call, assigning locations to each operand.
748 SmallVector<CCValAssign, 16> ArgLocs;
749 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
751 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
753 // Get the size of the outgoing arguments stack space requirement.
754 unsigned ArgsSize = CCInfo.getNextStackOffset();
756 // Keep stack frames 8-byte aligned.
757 ArgsSize = (ArgsSize+7) & ~7;
759 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
761 // Create local copies for byval args.
762 SmallVector<SDValue, 8> ByValArgs;
763 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
764 ISD::ArgFlagsTy Flags = Outs[i].Flags;
765 if (!Flags.isByVal())
768 SDValue Arg = OutVals[i];
769 unsigned Size = Flags.getByValSize();
770 unsigned Align = Flags.getByValAlign();
772 int FI = MFI->CreateStackObject(Size, Align, false);
773 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
774 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
776 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
777 false, // isVolatile,
778 (Size <= 32), // AlwaysInline if size <= 32,
780 MachinePointerInfo(), MachinePointerInfo());
781 ByValArgs.push_back(FIPtr);
784 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
787 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
788 SmallVector<SDValue, 8> MemOpChains;
790 const unsigned StackOffset = 92;
791 bool hasStructRetAttr = false;
792 // Walk the register/memloc assignments, inserting copies/loads.
793 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
796 CCValAssign &VA = ArgLocs[i];
797 SDValue Arg = OutVals[realArgIdx];
799 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
801 // Use local copy if it is a byval arg.
803 Arg = ByValArgs[byvalArgIdx++];
805 // Promote the value if needed.
806 switch (VA.getLocInfo()) {
807 default: llvm_unreachable("Unknown loc info!");
808 case CCValAssign::Full: break;
809 case CCValAssign::SExt:
810 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
812 case CCValAssign::ZExt:
813 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
815 case CCValAssign::AExt:
816 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
818 case CCValAssign::BCvt:
819 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
823 if (Flags.isSRet()) {
824 assert(VA.needsCustom());
825 // store SRet argument in %sp+64
826 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
827 SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
828 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
829 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
830 MachinePointerInfo(),
832 hasStructRetAttr = true;
836 if (VA.needsCustom()) {
837 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
840 unsigned Offset = VA.getLocMemOffset() + StackOffset;
841 // if it is double-word aligned, just store.
842 if (Offset % 8 == 0) {
843 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
844 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
845 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
846 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
847 MachinePointerInfo(),
853 if (VA.getLocVT() == MVT::f64) {
854 // Move from the float value from float registers into the
855 // integer registers.
857 // TODO: this conversion is done in two steps, because
858 // f64->i64 conversion is done efficiently, and i64->v2i32 is
859 // basically a no-op. But f64->v2i32 is NOT done efficiently
861 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
862 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
865 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
867 DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
868 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
870 DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
873 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
875 CCValAssign &NextVA = ArgLocs[++i];
876 if (NextVA.isRegLoc()) {
877 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
879 // Store the second part in stack.
880 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
881 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
882 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
883 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
884 MemOpChains.push_back(DAG.getStore(Chain, dl, Part1, PtrOff,
885 MachinePointerInfo(),
889 unsigned Offset = VA.getLocMemOffset() + StackOffset;
890 // Store the first part.
891 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
892 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
893 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
894 MemOpChains.push_back(DAG.getStore(Chain, dl, Part0, PtrOff,
895 MachinePointerInfo(),
897 // Store the second part.
898 PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
899 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
900 MemOpChains.push_back(DAG.getStore(Chain, dl, Part1, PtrOff,
901 MachinePointerInfo(),
907 // Arguments that can be passed on register must be kept at
910 if (VA.getLocVT() != MVT::f32) {
911 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
914 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
915 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
919 assert(VA.isMemLoc());
921 // Create a store off the stack pointer for this argument.
922 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
923 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
925 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
926 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
927 MachinePointerInfo(),
932 // Emit all stores, make sure the occur before any copies into physregs.
933 if (!MemOpChains.empty())
934 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
936 // Build a sequence of copy-to-reg nodes chained together with token
937 // chain and flag operands which copy the outgoing args into registers.
938 // The InFlag in necessary since all emitted instructions must be
941 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
942 unsigned Reg = toCallerWindow(RegsToPass[i].first);
943 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
944 InFlag = Chain.getValue(1);
947 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
948 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
950 // If the callee is a GlobalAddress node (quite common, every direct call is)
951 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
952 // Likewise ExternalSymbol -> TargetExternalSymbol.
953 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
954 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
955 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
956 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
957 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
958 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
960 // Returns a chain & a flag for retval copy to use
961 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
962 SmallVector<SDValue, 8> Ops;
963 Ops.push_back(Chain);
964 Ops.push_back(Callee);
965 if (hasStructRetAttr)
966 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
967 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
968 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
969 RegsToPass[i].second.getValueType()));
971 // Add a register mask operand representing the call-preserved registers.
972 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
973 const uint32_t *Mask =
975 ? TRI->getRTCallPreservedMask(CallConv)
976 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
977 assert(Mask && "Missing call preserved mask for calling convention");
978 Ops.push_back(DAG.getRegisterMask(Mask));
980 if (InFlag.getNode())
981 Ops.push_back(InFlag);
983 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
984 InFlag = Chain.getValue(1);
986 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
987 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
988 InFlag = Chain.getValue(1);
990 // Assign locations to each value returned by this call.
991 SmallVector<CCValAssign, 16> RVLocs;
992 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
995 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
997 // Copy all of the result registers out of their specified physreg.
998 for (unsigned i = 0; i != RVLocs.size(); ++i) {
999 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1000 RVLocs[i].getValVT(), InFlag).getValue(1);
1001 InFlag = Chain.getValue(2);
1002 InVals.push_back(Chain.getValue(0));
1008 // This functions returns true if CalleeName is a ABI function that returns
1009 // a long double (fp128).
1010 static bool isFP128ABICall(const char *CalleeName)
1012 static const char *const ABICalls[] =
1013 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
1014 "_Q_sqrt", "_Q_neg",
1015 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
1016 "_Q_lltoq", "_Q_ulltoq",
1019 for (const char * const *I = ABICalls; *I != nullptr; ++I)
1020 if (strcmp(CalleeName, *I) == 0)
1026 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
1028 const Function *CalleeFn = nullptr;
1029 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1030 CalleeFn = dyn_cast<Function>(G->getGlobal());
1031 } else if (ExternalSymbolSDNode *E =
1032 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1033 const Function *Fn = DAG.getMachineFunction().getFunction();
1034 const Module *M = Fn->getParent();
1035 const char *CalleeName = E->getSymbol();
1036 CalleeFn = M->getFunction(CalleeName);
1037 if (!CalleeFn && isFP128ABICall(CalleeName))
1038 return 16; // Return sizeof(fp128)
1044 assert(CalleeFn->hasStructRetAttr() &&
1045 "Callee does not have the StructRet attribute.");
1047 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
1048 Type *ElementTy = Ty->getElementType();
1049 return DAG.getDataLayout().getTypeAllocSize(ElementTy);
1053 // Fixup floating point arguments in the ... part of a varargs call.
1055 // The SPARC v9 ABI requires that floating point arguments are treated the same
1056 // as integers when calling a varargs function. This does not apply to the
1057 // fixed arguments that are part of the function's prototype.
1059 // This function post-processes a CCValAssign array created by
1060 // AnalyzeCallOperands().
1061 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1062 ArrayRef<ISD::OutputArg> Outs) {
1063 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1064 const CCValAssign &VA = ArgLocs[i];
1065 MVT ValTy = VA.getLocVT();
1066 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1067 // varargs functions.
1068 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1070 // The fixed arguments to a varargs function still go in FP registers.
1071 if (Outs[VA.getValNo()].IsFixed)
1074 // This floating point argument should be reassigned.
1077 // Determine the offset into the argument array.
1078 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1079 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1080 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1081 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1084 // This argument should go in %i0-%i5.
1085 unsigned IReg = SP::I0 + Offset/8;
1086 if (ValTy == MVT::f64)
1087 // Full register, just bitconvert into i64.
1088 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1089 IReg, MVT::i64, CCValAssign::BCvt);
1091 assert(ValTy == MVT::f128 && "Unexpected type!");
1092 // Full register, just bitconvert into i128 -- We will lower this into
1093 // two i64s in LowerCall_64.
1094 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1095 IReg, MVT::i128, CCValAssign::BCvt);
1098 // This needs to go to memory, we're out of integer registers.
1099 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1100 Offset, VA.getLocVT(), VA.getLocInfo());
1106 // Lower a call for the 64-bit ABI.
1108 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1109 SmallVectorImpl<SDValue> &InVals) const {
1110 SelectionDAG &DAG = CLI.DAG;
1112 SDValue Chain = CLI.Chain;
1113 auto PtrVT = getPointerTy(DAG.getDataLayout());
1115 // Sparc target does not yet support tail call optimization.
1116 CLI.IsTailCall = false;
1118 // Analyze operands of the call, assigning locations to each operand.
1119 SmallVector<CCValAssign, 16> ArgLocs;
1120 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1122 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1124 // Get the size of the outgoing arguments stack space requirement.
1125 // The stack offset computed by CC_Sparc64 includes all arguments.
1126 // Called functions expect 6 argument words to exist in the stack frame, used
1128 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1130 // Keep stack frames 16-byte aligned.
1131 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1133 // Varargs calls require special treatment.
1135 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1137 // Adjust the stack pointer to make room for the arguments.
1138 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1139 // with more than 6 arguments.
1140 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1143 // Collect the set of registers to pass to the function and their values.
1144 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1146 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1148 // Collect chains from all the memory opeations that copy arguments to the
1149 // stack. They must follow the stack pointer adjustment above and precede the
1150 // call instruction itself.
1151 SmallVector<SDValue, 8> MemOpChains;
1153 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1154 const CCValAssign &VA = ArgLocs[i];
1155 SDValue Arg = CLI.OutVals[i];
1157 // Promote the value if needed.
1158 switch (VA.getLocInfo()) {
1160 llvm_unreachable("Unknown location info!");
1161 case CCValAssign::Full:
1163 case CCValAssign::SExt:
1164 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1166 case CCValAssign::ZExt:
1167 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1169 case CCValAssign::AExt:
1170 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1172 case CCValAssign::BCvt:
1173 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1174 // SPARC does not support i128 natively. Lower it into two i64, see below.
1175 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1176 || VA.getLocVT() != MVT::i128)
1177 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1181 if (VA.isRegLoc()) {
1182 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1183 && VA.getLocVT() == MVT::i128) {
1184 // Store and reload into the interger register reg and reg+1.
1185 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1186 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1187 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1188 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1189 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1190 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1191 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1193 // Store to %sp+BIAS+128+Offset
1194 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1195 MachinePointerInfo(),
1197 // Load into Reg and Reg+1
1198 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1199 MachinePointerInfo(),
1200 false, false, false, 0);
1201 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1202 MachinePointerInfo(),
1203 false, false, false, 0);
1204 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1206 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1211 // The custom bit on an i32 return value indicates that it should be
1212 // passed in the high bits of the register.
1213 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1214 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1215 DAG.getConstant(32, DL, MVT::i32));
1217 // The next value may go in the low bits of the same register.
1218 // Handle both at once.
1219 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1220 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1221 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1223 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1224 // Skip the next value, it's already done.
1228 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1232 assert(VA.isMemLoc());
1234 // Create a store off the stack pointer for this argument.
1235 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1236 // The argument area starts at %fp+BIAS+128 in the callee frame,
1237 // %sp+BIAS+128 in ours.
1238 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1239 Subtarget->getStackPointerBias() +
1241 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1242 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1243 MachinePointerInfo(),
1247 // Emit all stores, make sure they occur before the call.
1248 if (!MemOpChains.empty())
1249 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1251 // Build a sequence of CopyToReg nodes glued together with token chain and
1252 // glue operands which copy the outgoing args into registers. The InGlue is
1253 // necessary since all emitted instructions must be stuck together in order
1254 // to pass the live physical registers.
1256 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1257 Chain = DAG.getCopyToReg(Chain, DL,
1258 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1259 InGlue = Chain.getValue(1);
1262 // If the callee is a GlobalAddress node (quite common, every direct call is)
1263 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1264 // Likewise ExternalSymbol -> TargetExternalSymbol.
1265 SDValue Callee = CLI.Callee;
1266 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1267 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1268 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
1269 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1270 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1271 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1272 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1274 // Build the operands for the call instruction itself.
1275 SmallVector<SDValue, 8> Ops;
1276 Ops.push_back(Chain);
1277 Ops.push_back(Callee);
1278 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1279 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1280 RegsToPass[i].second.getValueType()));
1282 // Add a register mask operand representing the call-preserved registers.
1283 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1284 const uint32_t *Mask =
1285 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1286 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1288 assert(Mask && "Missing call preserved mask for calling convention");
1289 Ops.push_back(DAG.getRegisterMask(Mask));
1291 // Make sure the CopyToReg nodes are glued to the call instruction which
1292 // consumes the registers.
1293 if (InGlue.getNode())
1294 Ops.push_back(InGlue);
1296 // Now the call itself.
1297 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1298 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1299 InGlue = Chain.getValue(1);
1301 // Revert the stack pointer immediately after the call.
1302 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1303 DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
1304 InGlue = Chain.getValue(1);
1306 // Now extract the return values. This is more or less the same as
1307 // LowerFormalArguments_64.
1309 // Assign locations to each value returned by this call.
1310 SmallVector<CCValAssign, 16> RVLocs;
1311 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1314 // Set inreg flag manually for codegen generated library calls that
1316 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1317 CLI.Ins[0].Flags.setInReg();
1319 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1321 // Copy all of the result registers out of their specified physreg.
1322 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1323 CCValAssign &VA = RVLocs[i];
1324 unsigned Reg = toCallerWindow(VA.getLocReg());
1326 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1327 // reside in the same register in the high and low bits. Reuse the
1328 // CopyFromReg previous node to avoid duplicate copies.
1330 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1331 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1332 RV = Chain.getValue(0);
1334 // But usually we'll create a new CopyFromReg for a different register.
1335 if (!RV.getNode()) {
1336 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1337 Chain = RV.getValue(1);
1338 InGlue = Chain.getValue(2);
1341 // Get the high bits for i32 struct elements.
1342 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1343 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1344 DAG.getConstant(32, DL, MVT::i32));
1346 // The callee promoted the return value, so insert an Assert?ext SDNode so
1347 // we won't promote the value again in this function.
1348 switch (VA.getLocInfo()) {
1349 case CCValAssign::SExt:
1350 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1351 DAG.getValueType(VA.getValVT()));
1353 case CCValAssign::ZExt:
1354 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1355 DAG.getValueType(VA.getValVT()));
1361 // Truncate the register down to the return value type.
1362 if (VA.isExtInLoc())
1363 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1365 InVals.push_back(RV);
1371 //===----------------------------------------------------------------------===//
1372 // TargetLowering Implementation
1373 //===----------------------------------------------------------------------===//
1375 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1377 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1379 default: llvm_unreachable("Unknown integer condition code!");
1380 case ISD::SETEQ: return SPCC::ICC_E;
1381 case ISD::SETNE: return SPCC::ICC_NE;
1382 case ISD::SETLT: return SPCC::ICC_L;
1383 case ISD::SETGT: return SPCC::ICC_G;
1384 case ISD::SETLE: return SPCC::ICC_LE;
1385 case ISD::SETGE: return SPCC::ICC_GE;
1386 case ISD::SETULT: return SPCC::ICC_CS;
1387 case ISD::SETULE: return SPCC::ICC_LEU;
1388 case ISD::SETUGT: return SPCC::ICC_GU;
1389 case ISD::SETUGE: return SPCC::ICC_CC;
1393 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1395 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1397 default: llvm_unreachable("Unknown fp condition code!");
1399 case ISD::SETOEQ: return SPCC::FCC_E;
1401 case ISD::SETUNE: return SPCC::FCC_NE;
1403 case ISD::SETOLT: return SPCC::FCC_L;
1405 case ISD::SETOGT: return SPCC::FCC_G;
1407 case ISD::SETOLE: return SPCC::FCC_LE;
1409 case ISD::SETOGE: return SPCC::FCC_GE;
1410 case ISD::SETULT: return SPCC::FCC_UL;
1411 case ISD::SETULE: return SPCC::FCC_ULE;
1412 case ISD::SETUGT: return SPCC::FCC_UG;
1413 case ISD::SETUGE: return SPCC::FCC_UGE;
1414 case ISD::SETUO: return SPCC::FCC_U;
1415 case ISD::SETO: return SPCC::FCC_O;
1416 case ISD::SETONE: return SPCC::FCC_LG;
1417 case ISD::SETUEQ: return SPCC::FCC_UE;
1421 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
1422 const SparcSubtarget &STI)
1423 : TargetLowering(TM), Subtarget(&STI) {
1424 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
1426 // Instructions which use registers as conditionals examine all the
1427 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1428 // matters much whether it's ZeroOrOneBooleanContent, or
1429 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1431 setBooleanContents(ZeroOrOneBooleanContent);
1432 setBooleanVectorContents(ZeroOrOneBooleanContent);
1434 // Set up the register classes.
1435 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1436 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1437 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1438 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1439 if (Subtarget->is64Bit()) {
1440 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1442 // On 32bit sparc, we define a double-register 32bit register
1443 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1444 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1446 // ...but almost all operations must be expanded, so set that as
1448 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1449 setOperationAction(Op, MVT::v2i32, Expand);
1451 // Truncating/extending stores/loads are also not supported.
1452 for (MVT VT : MVT::integer_vector_valuetypes()) {
1453 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1454 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1455 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1457 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1458 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
1459 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1461 setTruncStoreAction(VT, MVT::v2i32, Expand);
1462 setTruncStoreAction(MVT::v2i32, VT, Expand);
1464 // However, load and store *are* legal.
1465 setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1466 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
1468 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
1470 // And we need to promote i64 loads/stores into vector load/store
1471 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1472 setOperationAction(ISD::STORE, MVT::i64, Custom);
1474 // Sadly, this doesn't work:
1475 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1476 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1479 // Turn FP extload into load/fextend
1480 for (MVT VT : MVT::fp_valuetypes()) {
1481 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1482 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1485 // Sparc doesn't have i1 sign extending load
1486 for (MVT VT : MVT::integer_valuetypes())
1487 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1489 // Turn FP truncstore into trunc + store.
1490 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1491 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1492 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1494 // Custom legalize GlobalAddress nodes into LO/HI parts.
1495 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
1496 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
1497 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
1498 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
1500 // Sparc doesn't have sext_inreg, replace them with shl/sra
1501 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1502 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1503 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1505 // Sparc has no REM or DIVREM operations.
1506 setOperationAction(ISD::UREM, MVT::i32, Expand);
1507 setOperationAction(ISD::SREM, MVT::i32, Expand);
1508 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1509 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1511 // ... nor does SparcV9.
1512 if (Subtarget->is64Bit()) {
1513 setOperationAction(ISD::UREM, MVT::i64, Expand);
1514 setOperationAction(ISD::SREM, MVT::i64, Expand);
1515 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1516 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1519 // Custom expand fp<->sint
1520 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1521 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1522 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1523 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1525 // Custom Expand fp<->uint
1526 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1527 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1528 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1529 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1531 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1532 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1534 // Sparc has no select or setcc: expand to SELECT_CC.
1535 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1536 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1537 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1538 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1540 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1541 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1542 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1543 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1545 // Sparc doesn't have BRCOND either, it has BR_CC.
1546 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1547 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1548 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1549 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1550 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1551 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1552 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1554 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1555 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1556 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1557 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1559 if (Subtarget->is64Bit()) {
1560 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1561 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1562 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1563 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1564 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1565 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1566 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1567 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1568 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1569 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1571 setOperationAction(ISD::CTPOP, MVT::i64,
1572 Subtarget->usePopc() ? Legal : Expand);
1573 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1574 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1575 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1576 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1577 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1578 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1579 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1580 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1584 // FIXME: We insert fences for each atomics and generate sub-optimal code
1585 // for PSO/TSO. Also, implement other atomicrmw operations.
1587 setInsertFencesForAtomic(true);
1589 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1590 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
1591 (Subtarget->isV9() ? Legal: Expand));
1594 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1596 // Custom Lower Atomic LOAD/STORE
1597 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1598 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1600 if (Subtarget->is64Bit()) {
1601 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1602 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1603 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1604 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1607 if (!Subtarget->isV9()) {
1608 // SparcV8 does not have FNEGD and FABSD.
1609 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1610 setOperationAction(ISD::FABS, MVT::f64, Custom);
1613 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1614 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1615 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1616 setOperationAction(ISD::FREM , MVT::f128, Expand);
1617 setOperationAction(ISD::FMA , MVT::f128, Expand);
1618 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1619 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1620 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1621 setOperationAction(ISD::FREM , MVT::f64, Expand);
1622 setOperationAction(ISD::FMA , MVT::f64, Expand);
1623 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1624 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1625 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1626 setOperationAction(ISD::FREM , MVT::f32, Expand);
1627 setOperationAction(ISD::FMA , MVT::f32, Expand);
1628 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1629 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1630 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1631 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1632 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1633 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1634 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1635 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1638 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1639 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1640 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1642 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1643 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1644 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1646 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1647 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1648 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1650 if (Subtarget->is64Bit()) {
1651 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1652 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1653 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1654 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1656 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1657 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1659 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1660 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1661 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1664 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1665 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1666 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1667 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1669 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1671 // Use the default implementation.
1672 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1673 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1674 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1675 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1676 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1678 setExceptionPointerRegister(SP::I0);
1679 setExceptionSelectorRegister(SP::I1);
1681 setStackPointerRegisterToSaveRestore(SP::O6);
1683 setOperationAction(ISD::CTPOP, MVT::i32,
1684 Subtarget->usePopc() ? Legal : Expand);
1686 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1687 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1688 setOperationAction(ISD::STORE, MVT::f128, Legal);
1690 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1691 setOperationAction(ISD::STORE, MVT::f128, Custom);
1694 if (Subtarget->hasHardQuad()) {
1695 setOperationAction(ISD::FADD, MVT::f128, Legal);
1696 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1697 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1698 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1699 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1700 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1701 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1702 if (Subtarget->isV9()) {
1703 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1704 setOperationAction(ISD::FABS, MVT::f128, Legal);
1706 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1707 setOperationAction(ISD::FABS, MVT::f128, Custom);
1710 if (!Subtarget->is64Bit()) {
1711 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1712 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1713 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1714 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1718 // Custom legalize f128 operations.
1720 setOperationAction(ISD::FADD, MVT::f128, Custom);
1721 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1722 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1723 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1724 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1725 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1726 setOperationAction(ISD::FABS, MVT::f128, Custom);
1728 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1729 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1730 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1732 // Setup Runtime library names.
1733 if (Subtarget->is64Bit()) {
1734 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1735 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1736 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1737 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1738 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1739 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1740 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1741 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1742 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1743 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1744 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1745 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1746 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1747 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1748 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1749 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1750 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1752 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1753 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1754 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1755 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1756 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1757 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1758 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1759 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1760 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1761 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1762 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1763 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1764 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1765 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1766 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1767 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1768 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1772 setMinFunctionAlignment(2);
1774 computeRegisterProperties(Subtarget->getRegisterInfo());
1777 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1778 switch ((SPISD::NodeType)Opcode) {
1779 case SPISD::FIRST_NUMBER: break;
1780 case SPISD::CMPICC: return "SPISD::CMPICC";
1781 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1782 case SPISD::BRICC: return "SPISD::BRICC";
1783 case SPISD::BRXCC: return "SPISD::BRXCC";
1784 case SPISD::BRFCC: return "SPISD::BRFCC";
1785 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1786 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1787 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1788 case SPISD::Hi: return "SPISD::Hi";
1789 case SPISD::Lo: return "SPISD::Lo";
1790 case SPISD::FTOI: return "SPISD::FTOI";
1791 case SPISD::ITOF: return "SPISD::ITOF";
1792 case SPISD::FTOX: return "SPISD::FTOX";
1793 case SPISD::XTOF: return "SPISD::XTOF";
1794 case SPISD::CALL: return "SPISD::CALL";
1795 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1796 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1797 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1798 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1799 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1800 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1805 EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
1809 return VT.changeVectorElementTypeToInteger();
1812 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1813 /// be zero. Op is expected to be a target specific node. Used by DAG
1815 void SparcTargetLowering::computeKnownBitsForTargetNode
1819 const SelectionDAG &DAG,
1820 unsigned Depth) const {
1821 APInt KnownZero2, KnownOne2;
1822 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1824 switch (Op.getOpcode()) {
1826 case SPISD::SELECT_ICC:
1827 case SPISD::SELECT_XCC:
1828 case SPISD::SELECT_FCC:
1829 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1830 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1832 // Only known if known in both the LHS and RHS.
1833 KnownOne &= KnownOne2;
1834 KnownZero &= KnownZero2;
1839 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1840 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1841 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1842 ISD::CondCode CC, unsigned &SPCC) {
1843 if (isa<ConstantSDNode>(RHS) &&
1844 cast<ConstantSDNode>(RHS)->isNullValue() &&
1846 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1847 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1848 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1849 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1850 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1851 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1852 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1853 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1854 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1855 SDValue CMPCC = LHS.getOperand(3);
1856 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1857 LHS = CMPCC.getOperand(0);
1858 RHS = CMPCC.getOperand(1);
1862 // Convert to a target node and set target flags.
1863 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1864 SelectionDAG &DAG) const {
1865 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1866 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1868 GA->getValueType(0),
1869 GA->getOffset(), TF);
1871 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1872 return DAG.getTargetConstantPool(CP->getConstVal(),
1873 CP->getValueType(0),
1875 CP->getOffset(), TF);
1877 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1878 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1883 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1884 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1885 ES->getValueType(0), TF);
1887 llvm_unreachable("Unhandled address SDNode");
1890 // Split Op into high and low parts according to HiTF and LoTF.
1891 // Return an ADD node combining the parts.
1892 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1893 unsigned HiTF, unsigned LoTF,
1894 SelectionDAG &DAG) const {
1896 EVT VT = Op.getValueType();
1897 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1898 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1899 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1902 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1903 // or ExternalSymbol SDNode.
1904 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1906 EVT VT = getPointerTy(DAG.getDataLayout());
1908 // Handle PIC mode first.
1909 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1910 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1911 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1912 SparcMCExpr::VK_Sparc_GOT10, DAG);
1913 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1914 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1915 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1916 // function has calls.
1917 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1918 MFI->setHasCalls(true);
1919 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1920 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
1921 false, false, false, 0);
1924 // This is one of the absolute code models.
1925 switch(getTargetMachine().getCodeModel()) {
1927 llvm_unreachable("Unsupported absolute code model");
1928 case CodeModel::Small:
1930 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1931 SparcMCExpr::VK_Sparc_LO, DAG);
1932 case CodeModel::Medium: {
1934 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1935 SparcMCExpr::VK_Sparc_M44, DAG);
1936 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
1937 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1938 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1939 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1941 case CodeModel::Large: {
1943 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1944 SparcMCExpr::VK_Sparc_HM, DAG);
1945 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
1946 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1947 SparcMCExpr::VK_Sparc_LO, DAG);
1948 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1953 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1954 SelectionDAG &DAG) const {
1955 return makeAddress(Op, DAG);
1958 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1959 SelectionDAG &DAG) const {
1960 return makeAddress(Op, DAG);
1963 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1964 SelectionDAG &DAG) const {
1965 return makeAddress(Op, DAG);
1968 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1969 SelectionDAG &DAG) const {
1971 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1972 if (DAG.getTarget().Options.EmulatedTLS)
1973 return LowerToTLSEmulatedModel(GA, DAG);
1976 const GlobalValue *GV = GA->getGlobal();
1977 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1979 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1981 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1982 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1983 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
1984 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
1985 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1986 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
1987 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
1988 unsigned addTF = ((model == TLSModel::GeneralDynamic)
1989 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
1990 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
1991 unsigned callTF = ((model == TLSModel::GeneralDynamic)
1992 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
1993 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
1995 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1996 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1997 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1998 withTargetFlags(Op, addTF, DAG));
2000 SDValue Chain = DAG.getEntryNode();
2003 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
2004 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2005 InFlag = Chain.getValue(1);
2006 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2007 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2009 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2010 SmallVector<SDValue, 4> Ops;
2011 Ops.push_back(Chain);
2012 Ops.push_back(Callee);
2013 Ops.push_back(Symbol);
2014 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
2015 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2016 DAG.getMachineFunction(), CallingConv::C);
2017 assert(Mask && "Missing call preserved mask for calling convention");
2018 Ops.push_back(DAG.getRegisterMask(Mask));
2019 Ops.push_back(InFlag);
2020 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2021 InFlag = Chain.getValue(1);
2022 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
2023 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2024 InFlag = Chain.getValue(1);
2025 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
2027 if (model != TLSModel::LocalDynamic)
2030 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2031 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
2032 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2033 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
2034 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2035 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2036 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
2039 if (model == TLSModel::InitialExec) {
2040 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
2041 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
2043 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2045 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2046 // function has calls.
2047 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2048 MFI->setHasCalls(true);
2050 SDValue TGA = makeHiLoPair(Op,
2051 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
2052 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
2053 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2054 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
2056 withTargetFlags(Op, ldTF, DAG));
2057 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2058 DAG.getRegister(SP::G7, PtrVT), Offset,
2060 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
2063 assert(model == TLSModel::LocalExec);
2064 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2065 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
2066 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2067 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
2068 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2070 return DAG.getNode(ISD::ADD, DL, PtrVT,
2071 DAG.getRegister(SP::G7, PtrVT), Offset);
2075 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
2076 SDValue Arg, SDLoc DL,
2077 SelectionDAG &DAG) const {
2078 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2079 EVT ArgVT = Arg.getValueType();
2080 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2086 if (ArgTy->isFP128Ty()) {
2087 // Create a stack object and pass the pointer to the library function.
2088 int FI = MFI->CreateStackObject(16, 8, false);
2089 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2090 Chain = DAG.getStore(Chain,
2094 MachinePointerInfo(),
2100 Entry.Ty = PointerType::getUnqual(ArgTy);
2102 Args.push_back(Entry);
2107 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2108 const char *LibFuncName,
2109 unsigned numArgs) const {
2113 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2114 auto PtrVT = getPointerTy(DAG.getDataLayout());
2116 SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2117 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2118 Type *RetTyABI = RetTy;
2119 SDValue Chain = DAG.getEntryNode();
2122 if (RetTy->isFP128Ty()) {
2123 // Create a Stack Object to receive the return value of type f128.
2125 int RetFI = MFI->CreateStackObject(16, 8, false);
2126 RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2127 Entry.Node = RetPtr;
2128 Entry.Ty = PointerType::getUnqual(RetTy);
2129 if (!Subtarget->is64Bit())
2130 Entry.isSRet = true;
2131 Entry.isReturned = false;
2132 Args.push_back(Entry);
2133 RetTyABI = Type::getVoidTy(*DAG.getContext());
2136 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2137 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2138 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2140 TargetLowering::CallLoweringInfo CLI(DAG);
2141 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2142 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0);
2144 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2146 // chain is in second result.
2147 if (RetTyABI == RetTy)
2148 return CallInfo.first;
2150 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2152 Chain = CallInfo.second;
2154 // Load RetPtr to get the return value.
2155 return DAG.getLoad(Op.getValueType(),
2159 MachinePointerInfo(),
2160 false, false, false, 8);
2164 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2167 SelectionDAG &DAG) const {
2169 const char *LibCall = nullptr;
2170 bool is64Bit = Subtarget->is64Bit();
2172 default: llvm_unreachable("Unhandled conditional code!");
2173 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2174 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2175 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2176 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2177 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2178 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2186 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2189 auto PtrVT = getPointerTy(DAG.getDataLayout());
2190 SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2191 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2193 SDValue Chain = DAG.getEntryNode();
2194 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2195 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2197 TargetLowering::CallLoweringInfo CLI(DAG);
2198 CLI.setDebugLoc(DL).setChain(Chain)
2199 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
2201 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2203 // result is in first, and chain is in second result.
2204 SDValue Result = CallInfo.first;
2208 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2209 SPCC = SPCC::ICC_NE;
2210 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2212 case SPCC::FCC_UL : {
2213 SDValue Mask = DAG.getTargetConstant(1, DL, Result.getValueType());
2214 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2215 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2216 SPCC = SPCC::ICC_NE;
2217 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2219 case SPCC::FCC_ULE: {
2220 SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
2221 SPCC = SPCC::ICC_NE;
2222 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2224 case SPCC::FCC_UG : {
2225 SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2227 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2229 case SPCC::FCC_UGE: {
2230 SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2231 SPCC = SPCC::ICC_NE;
2232 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2235 case SPCC::FCC_U : {
2236 SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2238 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2240 case SPCC::FCC_O : {
2241 SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2242 SPCC = SPCC::ICC_NE;
2243 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2245 case SPCC::FCC_LG : {
2246 SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
2247 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2248 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2249 SPCC = SPCC::ICC_NE;
2250 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2252 case SPCC::FCC_UE : {
2253 SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
2254 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2255 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2257 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2263 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2264 const SparcTargetLowering &TLI) {
2266 if (Op.getOperand(0).getValueType() == MVT::f64)
2267 return TLI.LowerF128Op(Op, DAG,
2268 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2270 if (Op.getOperand(0).getValueType() == MVT::f32)
2271 return TLI.LowerF128Op(Op, DAG,
2272 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2274 llvm_unreachable("fpextend with non-float operand!");
2279 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2280 const SparcTargetLowering &TLI) {
2281 // FP_ROUND on f64 and f32 are legal.
2282 if (Op.getOperand(0).getValueType() != MVT::f128)
2285 if (Op.getValueType() == MVT::f64)
2286 return TLI.LowerF128Op(Op, DAG,
2287 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2288 if (Op.getValueType() == MVT::f32)
2289 return TLI.LowerF128Op(Op, DAG,
2290 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2292 llvm_unreachable("fpround to non-float!");
2296 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2297 const SparcTargetLowering &TLI,
2300 EVT VT = Op.getValueType();
2301 assert(VT == MVT::i32 || VT == MVT::i64);
2303 // Expand f128 operations to fp128 abi calls.
2304 if (Op.getOperand(0).getValueType() == MVT::f128
2305 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2306 const char *libName = TLI.getLibcallName(VT == MVT::i32
2307 ? RTLIB::FPTOSINT_F128_I32
2308 : RTLIB::FPTOSINT_F128_I64);
2309 return TLI.LowerF128Op(Op, DAG, libName, 1);
2312 // Expand if the resulting type is illegal.
2313 if (!TLI.isTypeLegal(VT))
2316 // Otherwise, Convert the fp value to integer in an FP register.
2318 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2320 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2322 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2325 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2326 const SparcTargetLowering &TLI,
2329 EVT OpVT = Op.getOperand(0).getValueType();
2330 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2332 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2334 // Expand f128 operations to fp128 ABI calls.
2335 if (Op.getValueType() == MVT::f128
2336 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2337 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2338 ? RTLIB::SINTTOFP_I32_F128
2339 : RTLIB::SINTTOFP_I64_F128);
2340 return TLI.LowerF128Op(Op, DAG, libName, 1);
2343 // Expand if the operand type is illegal.
2344 if (!TLI.isTypeLegal(OpVT))
2347 // Otherwise, Convert the int value to FP in an FP register.
2348 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2349 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2350 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2353 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2354 const SparcTargetLowering &TLI,
2357 EVT VT = Op.getValueType();
2359 // Expand if it does not involve f128 or the target has support for
2360 // quad floating point instructions and the resulting type is legal.
2361 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2362 (hasHardQuad && TLI.isTypeLegal(VT)))
2365 assert(VT == MVT::i32 || VT == MVT::i64);
2367 return TLI.LowerF128Op(Op, DAG,
2368 TLI.getLibcallName(VT == MVT::i32
2369 ? RTLIB::FPTOUINT_F128_I32
2370 : RTLIB::FPTOUINT_F128_I64),
2374 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2375 const SparcTargetLowering &TLI,
2378 EVT OpVT = Op.getOperand(0).getValueType();
2379 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2381 // Expand if it does not involve f128 or the target has support for
2382 // quad floating point instructions and the operand type is legal.
2383 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2386 return TLI.LowerF128Op(Op, DAG,
2387 TLI.getLibcallName(OpVT == MVT::i32
2388 ? RTLIB::UINTTOFP_I32_F128
2389 : RTLIB::UINTTOFP_I64_F128),
2393 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2394 const SparcTargetLowering &TLI,
2396 SDValue Chain = Op.getOperand(0);
2397 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2398 SDValue LHS = Op.getOperand(2);
2399 SDValue RHS = Op.getOperand(3);
2400 SDValue Dest = Op.getOperand(4);
2402 unsigned Opc, SPCC = ~0U;
2404 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2405 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2406 LookThroughSetCC(LHS, RHS, CC, SPCC);
2408 // Get the condition flag.
2409 SDValue CompareFlag;
2410 if (LHS.getValueType().isInteger()) {
2411 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2412 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2413 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2414 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2416 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2417 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2418 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2421 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2422 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2426 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2427 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2430 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2431 const SparcTargetLowering &TLI,
2433 SDValue LHS = Op.getOperand(0);
2434 SDValue RHS = Op.getOperand(1);
2435 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2436 SDValue TrueVal = Op.getOperand(2);
2437 SDValue FalseVal = Op.getOperand(3);
2439 unsigned Opc, SPCC = ~0U;
2441 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2442 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2443 LookThroughSetCC(LHS, RHS, CC, SPCC);
2445 SDValue CompareFlag;
2446 if (LHS.getValueType().isInteger()) {
2447 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2448 Opc = LHS.getValueType() == MVT::i32 ?
2449 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2450 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2452 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2453 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2454 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2455 Opc = SPISD::SELECT_ICC;
2457 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2458 Opc = SPISD::SELECT_FCC;
2459 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2462 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2463 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2466 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2467 const SparcTargetLowering &TLI) {
2468 MachineFunction &MF = DAG.getMachineFunction();
2469 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2470 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2472 // Need frame address to find the address of VarArgsFrameIndex.
2473 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2475 // vastart just stores the address of the VarArgsFrameIndex slot into the
2476 // memory location argument.
2479 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2480 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2481 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2482 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2483 MachinePointerInfo(SV), false, false, 0);
2486 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2487 SDNode *Node = Op.getNode();
2488 EVT VT = Node->getValueType(0);
2489 SDValue InChain = Node->getOperand(0);
2490 SDValue VAListPtr = Node->getOperand(1);
2491 EVT PtrVT = VAListPtr.getValueType();
2492 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2494 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2495 MachinePointerInfo(SV), false, false, false, 0);
2496 // Increment the pointer, VAList, to the next vaarg.
2497 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2498 DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2500 // Store the incremented VAList to the legalized pointer.
2501 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2502 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2503 // Load the actual argument out of the pointer VAList.
2504 // We can't count on greater alignment than the word size.
2505 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2506 false, false, false,
2507 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2510 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2511 const SparcSubtarget *Subtarget) {
2512 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2513 SDValue Size = Op.getOperand(1); // Legalize the size.
2514 EVT VT = Size->getValueType(0);
2517 unsigned SPReg = SP::O6;
2518 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2519 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2520 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2522 // The resultant pointer is actually 16 words from the bottom of the stack,
2523 // to provide a register spill area.
2524 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2525 regSpillArea += Subtarget->getStackPointerBias();
2527 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2528 DAG.getConstant(regSpillArea, dl, VT));
2529 SDValue Ops[2] = { NewVal, Chain };
2530 return DAG.getMergeValues(Ops, dl);
2534 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2536 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2537 dl, MVT::Other, DAG.getEntryNode());
2541 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2542 const SparcSubtarget *Subtarget) {
2543 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2544 MFI->setFrameAddressIsTaken(true);
2546 EVT VT = Op.getValueType();
2548 unsigned FrameReg = SP::I6;
2549 unsigned stackBias = Subtarget->getStackPointerBias();
2554 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2555 if (Subtarget->is64Bit())
2556 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2557 DAG.getIntPtrConstant(stackBias, dl));
2561 // flush first to make sure the windowed registers' values are in stack
2562 SDValue Chain = getFLUSHW(Op, DAG);
2563 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2565 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2568 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2569 DAG.getIntPtrConstant(Offset, dl));
2570 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2571 false, false, false, 0);
2573 if (Subtarget->is64Bit())
2574 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2575 DAG.getIntPtrConstant(stackBias, dl));
2580 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2581 const SparcSubtarget *Subtarget) {
2583 uint64_t depth = Op.getConstantOperandVal(0);
2585 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2589 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2590 const SparcTargetLowering &TLI,
2591 const SparcSubtarget *Subtarget) {
2592 MachineFunction &MF = DAG.getMachineFunction();
2593 MachineFrameInfo *MFI = MF.getFrameInfo();
2594 MFI->setReturnAddressIsTaken(true);
2596 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2599 EVT VT = Op.getValueType();
2601 uint64_t depth = Op.getConstantOperandVal(0);
2605 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2606 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2607 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2611 // Need frame address to find return address of the caller.
2612 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2614 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2615 SDValue Ptr = DAG.getNode(ISD::ADD,
2618 DAG.getIntPtrConstant(Offset, dl));
2619 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2620 MachinePointerInfo(), false, false, false, 0);
2625 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2629 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2630 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2632 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2633 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2634 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2636 SDValue SrcReg64 = Op.getOperand(0);
2637 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2639 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2642 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2644 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2646 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2648 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2653 // Lower a f128 load into two f64 loads.
2654 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2657 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2658 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2659 && "Unexpected node type");
2661 unsigned alignment = LdNode->getAlignment();
2665 SDValue Hi64 = DAG.getLoad(MVT::f64,
2668 LdNode->getBasePtr(),
2669 LdNode->getPointerInfo(),
2670 false, false, false, alignment);
2671 EVT addrVT = LdNode->getBasePtr().getValueType();
2672 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2673 LdNode->getBasePtr(),
2674 DAG.getConstant(8, dl, addrVT));
2675 SDValue Lo64 = DAG.getLoad(MVT::f64,
2679 LdNode->getPointerInfo(),
2680 false, false, false, alignment);
2682 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2683 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2685 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2687 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2689 SDValue(InFP128, 0),
2692 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2694 SDValue(InFP128, 0),
2697 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2698 SDValue(Lo64.getNode(), 1) };
2699 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2700 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2701 return DAG.getMergeValues(Ops, dl);
2704 static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
2706 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2708 EVT MemVT = LdNode->getMemoryVT();
2709 if (MemVT == MVT::f128)
2710 return LowerF128Load(Op, DAG);
2715 // Lower a f128 store into two f64 stores.
2716 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2718 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2719 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2720 && "Unexpected node type");
2721 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2722 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2724 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2729 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2735 unsigned alignment = StNode->getAlignment();
2739 SDValue OutChains[2];
2740 OutChains[0] = DAG.getStore(StNode->getChain(),
2743 StNode->getBasePtr(),
2744 MachinePointerInfo(),
2745 false, false, alignment);
2746 EVT addrVT = StNode->getBasePtr().getValueType();
2747 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2748 StNode->getBasePtr(),
2749 DAG.getConstant(8, dl, addrVT));
2750 OutChains[1] = DAG.getStore(StNode->getChain(),
2754 MachinePointerInfo(),
2755 false, false, alignment);
2756 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2759 static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
2762 StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
2764 EVT MemVT = St->getMemoryVT();
2765 if (MemVT == MVT::f128)
2766 return LowerF128Store(Op, DAG);
2768 if (MemVT == MVT::i64) {
2769 // Custom handling for i64 stores: turn it into a bitcast and a
2771 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
2772 SDValue Chain = DAG.getStore(
2773 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
2774 St->isVolatile(), St->isNonTemporal(), St->getAlignment(),
2782 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2783 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2784 && "invalid opcode");
2786 if (Op.getValueType() == MVT::f64)
2787 return LowerF64Op(Op, DAG, Op.getOpcode());
2788 if (Op.getValueType() != MVT::f128)
2791 // Lower fabs/fneg on f128 to fabs/fneg on f64
2792 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2795 SDValue SrcReg128 = Op.getOperand(0);
2796 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2798 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2801 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2803 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
2805 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2807 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2809 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2814 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2816 if (Op.getValueType() != MVT::i64)
2820 SDValue Src1 = Op.getOperand(0);
2821 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2822 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2823 DAG.getConstant(32, dl, MVT::i64));
2824 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2826 SDValue Src2 = Op.getOperand(1);
2827 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2828 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2829 DAG.getConstant(32, dl, MVT::i64));
2830 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2833 bool hasChain = false;
2834 unsigned hiOpc = Op.getOpcode();
2835 switch (Op.getOpcode()) {
2836 default: llvm_unreachable("Invalid opcode");
2837 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2838 case ISD::ADDE: hasChain = true; break;
2839 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2840 case ISD::SUBE: hasChain = true; break;
2843 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2845 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2848 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2850 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2851 SDValue Carry = Hi.getValue(1);
2853 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2854 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2855 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2856 DAG.getConstant(32, dl, MVT::i64));
2858 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2859 SDValue Ops[2] = { Dst, Carry };
2860 return DAG.getMergeValues(Ops, dl);
2863 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2864 // in LegalizeDAG.cpp except the order of arguments to the library function.
2865 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2866 const SparcTargetLowering &TLI)
2868 unsigned opcode = Op.getOpcode();
2869 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2871 bool isSigned = (opcode == ISD::SMULO);
2873 EVT WideVT = MVT::i128;
2875 SDValue LHS = Op.getOperand(0);
2877 if (LHS.getValueType() != VT)
2880 SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2882 SDValue RHS = Op.getOperand(1);
2883 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2884 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2885 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2887 SDValue MulResult = TLI.makeLibCall(DAG,
2888 RTLIB::MUL_I128, WideVT,
2889 Args, 4, isSigned, dl).first;
2890 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2891 MulResult, DAG.getIntPtrConstant(0, dl));
2892 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2893 MulResult, DAG.getIntPtrConstant(1, dl));
2895 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2896 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2898 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
2901 // MulResult is a node with an illegal type. Because such things are not
2902 // generally permitted during this phase of legalization, ensure that
2903 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2905 assert(MulResult->use_empty() && "Illegally typed node still in use!");
2907 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2908 return DAG.getMergeValues(Ops, dl);
2911 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2912 // Monotonic load/stores are legal.
2913 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2916 // Otherwise, expand with a fence.
2920 SDValue SparcTargetLowering::
2921 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2923 bool hasHardQuad = Subtarget->hasHardQuad();
2924 bool isV9 = Subtarget->isV9();
2926 switch (Op.getOpcode()) {
2927 default: llvm_unreachable("Should not custom lower this!");
2929 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2931 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2933 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2934 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2935 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2936 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2937 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2939 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2941 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2943 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2945 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2947 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2949 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2950 case ISD::VAARG: return LowerVAARG(Op, DAG);
2951 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2954 case ISD::LOAD: return LowerLOAD(Op, DAG);
2955 case ISD::STORE: return LowerSTORE(Op, DAG);
2956 case ISD::FADD: return LowerF128Op(Op, DAG,
2957 getLibcallName(RTLIB::ADD_F128), 2);
2958 case ISD::FSUB: return LowerF128Op(Op, DAG,
2959 getLibcallName(RTLIB::SUB_F128), 2);
2960 case ISD::FMUL: return LowerF128Op(Op, DAG,
2961 getLibcallName(RTLIB::MUL_F128), 2);
2962 case ISD::FDIV: return LowerF128Op(Op, DAG,
2963 getLibcallName(RTLIB::DIV_F128), 2);
2964 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2965 getLibcallName(RTLIB::SQRT_F128),1);
2967 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
2968 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2969 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2973 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2975 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2976 case ISD::ATOMIC_LOAD:
2977 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2982 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2983 MachineBasicBlock *BB) const {
2984 switch (MI->getOpcode()) {
2985 default: llvm_unreachable("Unknown SELECT_CC!");
2986 case SP::SELECT_CC_Int_ICC:
2987 case SP::SELECT_CC_FP_ICC:
2988 case SP::SELECT_CC_DFP_ICC:
2989 case SP::SELECT_CC_QFP_ICC:
2990 return expandSelectCC(MI, BB, SP::BCOND);
2991 case SP::SELECT_CC_Int_FCC:
2992 case SP::SELECT_CC_FP_FCC:
2993 case SP::SELECT_CC_DFP_FCC:
2994 case SP::SELECT_CC_QFP_FCC:
2995 return expandSelectCC(MI, BB, SP::FBCOND);
2997 case SP::ATOMIC_LOAD_ADD_32:
2998 return expandAtomicRMW(MI, BB, SP::ADDrr);
2999 case SP::ATOMIC_LOAD_ADD_64:
3000 return expandAtomicRMW(MI, BB, SP::ADDXrr);
3001 case SP::ATOMIC_LOAD_SUB_32:
3002 return expandAtomicRMW(MI, BB, SP::SUBrr);
3003 case SP::ATOMIC_LOAD_SUB_64:
3004 return expandAtomicRMW(MI, BB, SP::SUBXrr);
3005 case SP::ATOMIC_LOAD_AND_32:
3006 return expandAtomicRMW(MI, BB, SP::ANDrr);
3007 case SP::ATOMIC_LOAD_AND_64:
3008 return expandAtomicRMW(MI, BB, SP::ANDXrr);
3009 case SP::ATOMIC_LOAD_OR_32:
3010 return expandAtomicRMW(MI, BB, SP::ORrr);
3011 case SP::ATOMIC_LOAD_OR_64:
3012 return expandAtomicRMW(MI, BB, SP::ORXrr);
3013 case SP::ATOMIC_LOAD_XOR_32:
3014 return expandAtomicRMW(MI, BB, SP::XORrr);
3015 case SP::ATOMIC_LOAD_XOR_64:
3016 return expandAtomicRMW(MI, BB, SP::XORXrr);
3017 case SP::ATOMIC_LOAD_NAND_32:
3018 return expandAtomicRMW(MI, BB, SP::ANDrr);
3019 case SP::ATOMIC_LOAD_NAND_64:
3020 return expandAtomicRMW(MI, BB, SP::ANDXrr);
3022 case SP::ATOMIC_SWAP_64:
3023 return expandAtomicRMW(MI, BB, 0);
3025 case SP::ATOMIC_LOAD_MAX_32:
3026 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
3027 case SP::ATOMIC_LOAD_MAX_64:
3028 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
3029 case SP::ATOMIC_LOAD_MIN_32:
3030 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
3031 case SP::ATOMIC_LOAD_MIN_64:
3032 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
3033 case SP::ATOMIC_LOAD_UMAX_32:
3034 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
3035 case SP::ATOMIC_LOAD_UMAX_64:
3036 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
3037 case SP::ATOMIC_LOAD_UMIN_32:
3038 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
3039 case SP::ATOMIC_LOAD_UMIN_64:
3040 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
3045 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
3046 MachineBasicBlock *BB,
3047 unsigned BROpcode) const {
3048 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3049 DebugLoc dl = MI->getDebugLoc();
3050 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
3052 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3053 // control-flow pattern. The incoming instruction knows the destination vreg
3054 // to set, the condition code register to branch on, the true/false values to
3055 // select between, and a branch opcode to use.
3056 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3057 MachineFunction::iterator It = BB;
3064 // fallthrough --> copy0MBB
3065 MachineBasicBlock *thisMBB = BB;
3066 MachineFunction *F = BB->getParent();
3067 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3068 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3069 F->insert(It, copy0MBB);
3070 F->insert(It, sinkMBB);
3072 // Transfer the remainder of BB and its successor edges to sinkMBB.
3073 sinkMBB->splice(sinkMBB->begin(), BB,
3074 std::next(MachineBasicBlock::iterator(MI)),
3076 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3078 // Add the true and fallthrough blocks as its successors.
3079 BB->addSuccessor(copy0MBB);
3080 BB->addSuccessor(sinkMBB);
3082 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
3085 // %FalseValue = ...
3086 // # fallthrough to sinkMBB
3089 // Update machine-CFG edges
3090 BB->addSuccessor(sinkMBB);
3093 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3096 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
3097 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
3098 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
3100 MI->eraseFromParent(); // The pseudo instruction is gone now.
3105 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
3106 MachineBasicBlock *MBB,
3108 unsigned CondCode) const {
3109 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3110 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
3111 DebugLoc DL = MI->getDebugLoc();
3113 // MI is an atomic read-modify-write instruction of the form:
3115 // rd = atomicrmw<op> addr, rs2
3117 // All three operands are registers.
3118 unsigned DestReg = MI->getOperand(0).getReg();
3119 unsigned AddrReg = MI->getOperand(1).getReg();
3120 unsigned Rs2Reg = MI->getOperand(2).getReg();
3122 // SelectionDAG has already inserted memory barriers before and after MI, so
3123 // we simply have to implement the operatiuon in terms of compare-and-swap.
3125 // %val0 = load %addr
3127 // %val = phi %val0, %dest
3128 // %upd = op %val, %rs2
3129 // %dest = cas %addr, %val, %upd
3134 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
3135 const TargetRegisterClass *ValueRC =
3136 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
3137 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
3139 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3140 .addReg(AddrReg).addImm(0);
3142 // Split the basic block MBB before MI and insert the loop block in the hole.
3143 MachineFunction::iterator MFI = MBB;
3144 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3145 MachineFunction *MF = MBB->getParent();
3146 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3147 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3149 MF->insert(MFI, LoopMBB);
3150 MF->insert(MFI, DoneMBB);
3152 // Move MI and following instructions to DoneMBB.
3153 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3154 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3156 // Connect the CFG again.
3157 MBB->addSuccessor(LoopMBB);
3158 LoopMBB->addSuccessor(LoopMBB);
3159 LoopMBB->addSuccessor(DoneMBB);
3161 // Build the loop block.
3162 unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3163 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3164 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3166 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3167 .addReg(Val0Reg).addMBB(MBB)
3168 .addReg(DestReg).addMBB(LoopMBB);
3171 // This is one of the min/max operations. We need a CMPrr followed by a
3173 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3174 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3175 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3176 } else if (Opcode) {
3177 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3178 .addReg(ValReg).addReg(Rs2Reg);
3181 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3182 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3183 unsigned TmpReg = UpdReg;
3184 UpdReg = MRI.createVirtualRegister(ValueRC);
3185 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3188 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3189 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3190 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3191 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3192 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3193 .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3195 MI->eraseFromParent();
3199 //===----------------------------------------------------------------------===//
3200 // Sparc Inline Assembly Support
3201 //===----------------------------------------------------------------------===//
3203 /// getConstraintType - Given a constraint letter, return the type of
3204 /// constraint it is for this target.
3205 SparcTargetLowering::ConstraintType
3206 SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3207 if (Constraint.size() == 1) {
3208 switch (Constraint[0]) {
3210 case 'r': return C_RegisterClass;
3216 return TargetLowering::getConstraintType(Constraint);
3219 TargetLowering::ConstraintWeight SparcTargetLowering::
3220 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3221 const char *constraint) const {
3222 ConstraintWeight weight = CW_Invalid;
3223 Value *CallOperandVal = info.CallOperandVal;
3224 // If we don't have a value, we can't do a match,
3225 // but allow it at the lowest weight.
3226 if (!CallOperandVal)
3229 // Look at the constraint type.
3230 switch (*constraint) {
3232 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3235 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3236 if (isInt<13>(C->getSExtValue()))
3237 weight = CW_Constant;
3244 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3245 /// vector. If it is invalid, don't add anything to Ops.
3246 void SparcTargetLowering::
3247 LowerAsmOperandForConstraint(SDValue Op,
3248 std::string &Constraint,
3249 std::vector<SDValue> &Ops,
3250 SelectionDAG &DAG) const {
3251 SDValue Result(nullptr, 0);
3253 // Only support length 1 constraints for now.
3254 if (Constraint.length() > 1)
3257 char ConstraintLetter = Constraint[0];
3258 switch (ConstraintLetter) {
3261 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3262 if (isInt<13>(C->getSExtValue())) {
3263 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3271 if (Result.getNode()) {
3272 Ops.push_back(Result);
3275 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3278 std::pair<unsigned, const TargetRegisterClass *>
3279 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3280 StringRef Constraint,
3282 if (Constraint.size() == 1) {
3283 switch (Constraint[0]) {
3285 if (VT == MVT::v2i32)
3286 return std::make_pair(0U, &SP::IntPairRegClass);
3288 return std::make_pair(0U, &SP::IntRegsRegClass);
3290 } else if (!Constraint.empty() && Constraint.size() <= 5
3291 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3292 // constraint = '{r<d>}'
3293 // Remove the braces from around the name.
3294 StringRef name(Constraint.data()+1, Constraint.size()-2);
3295 // Handle register aliases:
3300 uint64_t intVal = 0;
3301 if (name.substr(0, 1).equals("r")
3302 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3303 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3304 char regType = regTypes[intVal/8];
3305 char regIdx = '0' + (intVal % 8);
3306 char tmp[] = { '{', regType, regIdx, '}', 0 };
3307 std::string newConstraint = std::string(tmp);
3308 return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3313 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3317 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3318 // The Sparc target isn't yet aware of offsets.
3322 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3323 SmallVectorImpl<SDValue>& Results,
3324 SelectionDAG &DAG) const {
3328 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3330 switch (N->getOpcode()) {
3332 llvm_unreachable("Do not know how to custom type legalize this operation!");
3334 case ISD::FP_TO_SINT:
3335 case ISD::FP_TO_UINT:
3336 // Custom lower only if it involves f128 or i64.
3337 if (N->getOperand(0).getValueType() != MVT::f128
3338 || N->getValueType(0) != MVT::i64)
3340 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3341 ? RTLIB::FPTOSINT_F128_I64
3342 : RTLIB::FPTOUINT_F128_I64);
3344 Results.push_back(LowerF128Op(SDValue(N, 0),
3346 getLibcallName(libCall),
3350 case ISD::SINT_TO_FP:
3351 case ISD::UINT_TO_FP:
3352 // Custom lower only if it involves f128 or i64.
3353 if (N->getValueType(0) != MVT::f128
3354 || N->getOperand(0).getValueType() != MVT::i64)
3357 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3358 ? RTLIB::SINTTOFP_I64_F128
3359 : RTLIB::UINTTOFP_I64_F128);
3361 Results.push_back(LowerF128Op(SDValue(N, 0),
3363 getLibcallName(libCall),
3367 LoadSDNode *Ld = cast<LoadSDNode>(N);
3368 // Custom handling only for i64: turn i64 load into a v2i32 load,
3370 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3374 SDValue LoadRes = DAG.getExtLoad(
3375 Ld->getExtensionType(), dl, MVT::v2i32,
3376 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3377 MVT::v2i32, Ld->isVolatile(), Ld->isNonTemporal(),
3378 Ld->isInvariant(), Ld->getAlignment(), Ld->getAAInfo());
3380 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3381 Results.push_back(Res);
3382 Results.push_back(LoadRes.getValue(1));