1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcTargetMachine.h"
18 #include "MCTargetDesc/SparcBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/Support/ErrorHandling.h"
33 //===----------------------------------------------------------------------===//
34 // Calling Convention Implementation
35 //===----------------------------------------------------------------------===//
37 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
38 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
39 ISD::ArgFlagsTy &ArgFlags, CCState &State)
41 assert (ArgFlags.isSRet());
43 // Assign SRet argument.
44 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
50 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
51 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags, CCState &State)
54 static const uint16_t RegList[] = {
55 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
57 // Try to get first reg.
58 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
59 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
61 // Assign whole thing in stack.
62 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
63 State.AllocateStack(8,4),
68 // Try to get second reg.
69 if (unsigned Reg = State.AllocateReg(RegList, 6))
70 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
72 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
73 State.AllocateStack(4,4),
78 // Allocate a full-sized argument for the 64-bit ABI.
79 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
80 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
82 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
83 "Can't handle non-64 bits locations");
85 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
86 unsigned Offset = State.AllocateStack(8, 8);
89 if (LocVT == MVT::i64 && Offset < 6*8)
90 // Promote integers to %i0-%i5.
91 Reg = SP::I0 + Offset/8;
92 else if (LocVT == MVT::f64 && Offset < 16*8)
93 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
94 Reg = SP::D0 + Offset/8;
95 else if (LocVT == MVT::f32 && Offset < 16*8)
96 // Promote floats to %f1, %f3, ...
97 Reg = SP::F1 + Offset/4;
99 // Promote to register when possible, otherwise use the stack slot.
101 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
105 // This argument goes on the stack in an 8-byte slot.
106 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
107 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
108 if (LocVT == MVT::f32)
111 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
115 // Allocate a half-sized argument for the 64-bit ABI.
117 // This is used when passing { float, int } structs by value in registers.
118 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
119 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
120 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
121 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
122 unsigned Offset = State.AllocateStack(4, 4);
124 if (LocVT == MVT::f32 && Offset < 16*8) {
125 // Promote floats to %f0-%f31.
126 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
131 if (LocVT == MVT::i32 && Offset < 6*8) {
132 // Promote integers to %i0-%i5, using half the register.
133 unsigned Reg = SP::I0 + Offset/8;
135 LocInfo = CCValAssign::AExt;
137 // Set the Custom bit if this i32 goes in the high bits of a register.
139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
142 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
146 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
150 #include "SparcGenCallingConv.inc"
152 // The calling conventions in SparcCallingConv.td are described in terms of the
153 // callee's register window. This function translates registers to the
154 // corresponding caller window %o register.
155 static unsigned toCallerWindow(unsigned Reg) {
156 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
157 if (Reg >= SP::I0 && Reg <= SP::I7)
158 return Reg - SP::I0 + SP::O0;
163 SparcTargetLowering::LowerReturn(SDValue Chain,
164 CallingConv::ID CallConv, bool IsVarArg,
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
166 const SmallVectorImpl<SDValue> &OutVals,
167 SDLoc DL, SelectionDAG &DAG) const {
168 if (Subtarget->is64Bit())
169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
174 SparcTargetLowering::LowerReturn_32(SDValue Chain,
175 CallingConv::ID CallConv, bool IsVarArg,
176 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 const SmallVectorImpl<SDValue> &OutVals,
178 SDLoc DL, SelectionDAG &DAG) const {
179 MachineFunction &MF = DAG.getMachineFunction();
181 // CCValAssign - represent the assignment of the return value to locations.
182 SmallVector<CCValAssign, 16> RVLocs;
184 // CCState - Info about the registers and stack slot.
185 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
186 DAG.getTarget(), RVLocs, *DAG.getContext());
188 // Analyze return values.
189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
192 SmallVector<SDValue, 4> RetOps(1, Chain);
193 // Make room for the return address offset.
194 RetOps.push_back(SDValue());
196 // Copy the result values into the output registers.
197 for (unsigned i = 0; i != RVLocs.size(); ++i) {
198 CCValAssign &VA = RVLocs[i];
199 assert(VA.isRegLoc() && "Can only return in registers!");
201 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
204 // Guarantee that all emitted copies are stuck together with flags.
205 Flag = Chain.getValue(1);
206 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
209 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
210 // If the function returns a struct, copy the SRetReturnReg to I0
211 if (MF.getFunction()->hasStructRetAttr()) {
212 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
213 unsigned Reg = SFI->getSRetReturnReg();
215 llvm_unreachable("sret virtual register not created in the entry block");
216 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
217 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
218 Flag = Chain.getValue(1);
219 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
220 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
223 RetOps[0] = Chain; // Update chain.
224 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
226 // Add the flag if we have it.
228 RetOps.push_back(Flag);
230 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
231 &RetOps[0], RetOps.size());
234 // Lower return values for the 64-bit ABI.
235 // Return values are passed the exactly the same way as function arguments.
237 SparcTargetLowering::LowerReturn_64(SDValue Chain,
238 CallingConv::ID CallConv, bool IsVarArg,
239 const SmallVectorImpl<ISD::OutputArg> &Outs,
240 const SmallVectorImpl<SDValue> &OutVals,
241 SDLoc DL, SelectionDAG &DAG) const {
242 // CCValAssign - represent the assignment of the return value to locations.
243 SmallVector<CCValAssign, 16> RVLocs;
245 // CCState - Info about the registers and stack slot.
246 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
247 DAG.getTarget(), RVLocs, *DAG.getContext());
249 // Analyze return values.
250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
253 SmallVector<SDValue, 4> RetOps(1, Chain);
255 // The second operand on the return instruction is the return address offset.
256 // The return address is always %i7+8 with the 64-bit ABI.
257 RetOps.push_back(DAG.getConstant(8, MVT::i32));
259 // Copy the result values into the output registers.
260 for (unsigned i = 0; i != RVLocs.size(); ++i) {
261 CCValAssign &VA = RVLocs[i];
262 assert(VA.isRegLoc() && "Can only return in registers!");
263 SDValue OutVal = OutVals[i];
265 // Integer return values must be sign or zero extended by the callee.
266 switch (VA.getLocInfo()) {
267 case CCValAssign::SExt:
268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
270 case CCValAssign::ZExt:
271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
273 case CCValAssign::AExt:
274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
279 // The custom bit on an i32 return value indicates that it should be passed
280 // in the high bits of the register.
281 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
282 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
283 DAG.getConstant(32, MVT::i32));
285 // The next value may go in the low bits of the same register.
286 // Handle both at once.
287 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
288 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
289 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
290 // Skip the next value, it's already done.
295 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
297 // Guarantee that all emitted copies are stuck together with flags.
298 Flag = Chain.getValue(1);
299 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
302 RetOps[0] = Chain; // Update chain.
304 // Add the flag if we have it.
306 RetOps.push_back(Flag);
308 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
309 &RetOps[0], RetOps.size());
312 SDValue SparcTargetLowering::
313 LowerFormalArguments(SDValue Chain,
314 CallingConv::ID CallConv,
316 const SmallVectorImpl<ISD::InputArg> &Ins,
319 SmallVectorImpl<SDValue> &InVals) const {
320 if (Subtarget->is64Bit())
321 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
323 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
327 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
328 /// passed in either one or two GPRs, including FP values. TODO: we should
329 /// pass FP values in FP registers for fastcc functions.
330 SDValue SparcTargetLowering::
331 LowerFormalArguments_32(SDValue Chain,
332 CallingConv::ID CallConv,
334 const SmallVectorImpl<ISD::InputArg> &Ins,
337 SmallVectorImpl<SDValue> &InVals) const {
338 MachineFunction &MF = DAG.getMachineFunction();
339 MachineRegisterInfo &RegInfo = MF.getRegInfo();
340 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
342 // Assign locations to all of the incoming arguments.
343 SmallVector<CCValAssign, 16> ArgLocs;
344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
345 getTargetMachine(), ArgLocs, *DAG.getContext());
346 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
348 const unsigned StackOffset = 92;
350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
351 CCValAssign &VA = ArgLocs[i];
353 if (i == 0 && Ins[i].Flags.isSRet()) {
354 // Get SRet from [%fp+64].
355 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
356 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
357 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
358 MachinePointerInfo(),
359 false, false, false, 0);
360 InVals.push_back(Arg);
365 if (VA.needsCustom()) {
366 assert(VA.getLocVT() == MVT::f64);
367 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
368 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
369 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
372 CCValAssign &NextVA = ArgLocs[++i];
375 if (NextVA.isMemLoc()) {
376 int FrameIdx = MF.getFrameInfo()->
377 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
378 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
379 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
380 MachinePointerInfo(),
381 false, false, false, 0);
383 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
384 &SP::IntRegsRegClass);
385 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
388 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
389 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
390 InVals.push_back(WholeValue);
393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
395 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
396 if (VA.getLocVT() == MVT::f32)
397 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
398 else if (VA.getLocVT() != MVT::i32) {
399 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
400 DAG.getValueType(VA.getLocVT()));
401 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
403 InVals.push_back(Arg);
407 assert(VA.isMemLoc());
409 unsigned Offset = VA.getLocMemOffset()+StackOffset;
411 if (VA.needsCustom()) {
412 assert(VA.getValVT() == MVT::f64);
413 // If it is double-word aligned, just load.
414 if (Offset % 8 == 0) {
415 int FI = MF.getFrameInfo()->CreateFixedObject(8,
418 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
419 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
420 MachinePointerInfo(),
421 false,false, false, 0);
422 InVals.push_back(Load);
426 int FI = MF.getFrameInfo()->CreateFixedObject(4,
429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
430 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
431 MachinePointerInfo(),
432 false, false, false, 0);
433 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
436 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
438 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
439 MachinePointerInfo(),
440 false, false, false, 0);
443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
444 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
445 InVals.push_back(WholeValue);
449 int FI = MF.getFrameInfo()->CreateFixedObject(4,
452 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
454 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
455 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
456 MachinePointerInfo(),
457 false, false, false, 0);
459 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
460 // Sparc is big endian, so add an offset based on the ObjectVT.
461 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
462 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
463 DAG.getConstant(Offset, MVT::i32));
464 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
465 MachinePointerInfo(),
466 VA.getValVT(), false, false,0);
467 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
469 InVals.push_back(Load);
472 if (MF.getFunction()->hasStructRetAttr()) {
473 // Copy the SRet Argument to SRetReturnReg.
474 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
475 unsigned Reg = SFI->getSRetReturnReg();
477 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
478 SFI->setSRetReturnReg(Reg);
480 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
481 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
484 // Store remaining ArgRegs to the stack if this is a varargs function.
486 static const uint16_t ArgRegs[] = {
487 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
489 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
490 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
491 unsigned ArgOffset = CCInfo.getNextStackOffset();
492 if (NumAllocated == 6)
493 ArgOffset += StackOffset;
496 ArgOffset = 68+4*NumAllocated;
499 // Remember the vararg offset for the va_start implementation.
500 FuncInfo->setVarArgsFrameOffset(ArgOffset);
502 std::vector<SDValue> OutChains;
504 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
507 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
509 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
511 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
513 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
514 MachinePointerInfo(),
519 if (!OutChains.empty()) {
520 OutChains.push_back(Chain);
521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
522 &OutChains[0], OutChains.size());
529 // Lower formal arguments for the 64 bit ABI.
530 SDValue SparcTargetLowering::
531 LowerFormalArguments_64(SDValue Chain,
532 CallingConv::ID CallConv,
534 const SmallVectorImpl<ISD::InputArg> &Ins,
537 SmallVectorImpl<SDValue> &InVals) const {
538 MachineFunction &MF = DAG.getMachineFunction();
540 // Analyze arguments according to CC_Sparc64.
541 SmallVector<CCValAssign, 16> ArgLocs;
542 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
543 getTargetMachine(), ArgLocs, *DAG.getContext());
544 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
546 // The argument array begins at %fp+BIAS+128, after the register save area.
547 const unsigned ArgArea = 128;
549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
550 CCValAssign &VA = ArgLocs[i];
552 // This argument is passed in a register.
553 // All integer register arguments are promoted by the caller to i64.
555 // Create a virtual register for the promoted live-in value.
556 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
557 getRegClassFor(VA.getLocVT()));
558 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
560 // Get the high bits for i32 struct elements.
561 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
562 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
563 DAG.getConstant(32, MVT::i32));
565 // The caller promoted the argument, so insert an Assert?ext SDNode so we
566 // won't promote the value again in this function.
567 switch (VA.getLocInfo()) {
568 case CCValAssign::SExt:
569 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
570 DAG.getValueType(VA.getValVT()));
572 case CCValAssign::ZExt:
573 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
574 DAG.getValueType(VA.getValVT()));
580 // Truncate the register down to the argument type.
582 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
584 InVals.push_back(Arg);
588 // The registers are exhausted. This argument was passed on the stack.
589 assert(VA.isMemLoc());
590 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
591 // beginning of the arguments area at %fp+BIAS+128.
592 unsigned Offset = VA.getLocMemOffset() + ArgArea;
593 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
594 // Adjust offset for extended arguments, SPARC is big-endian.
595 // The caller will have written the full slot with extended bytes, but we
596 // prefer our own extending loads.
598 Offset += 8 - ValSize;
599 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
600 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
601 DAG.getFrameIndex(FI, getPointerTy()),
602 MachinePointerInfo::getFixedStack(FI),
603 false, false, false, 0));
609 // This function takes variable arguments, some of which may have been passed
610 // in registers %i0-%i5. Variable floating point arguments are never passed
611 // in floating point registers. They go on %i0-%i5 or on the stack like
612 // integer arguments.
614 // The va_start intrinsic needs to know the offset to the first variable
616 unsigned ArgOffset = CCInfo.getNextStackOffset();
617 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
618 // Skip the 128 bytes of register save area.
619 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
620 Subtarget->getStackPointerBias());
622 // Save the variable arguments that were passed in registers.
623 // The caller is required to reserve stack space for 6 arguments regardless
624 // of how many arguments were actually passed.
625 SmallVector<SDValue, 8> OutChains;
626 for (; ArgOffset < 6*8; ArgOffset += 8) {
627 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
628 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
629 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
630 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
631 DAG.getFrameIndex(FI, getPointerTy()),
632 MachinePointerInfo::getFixedStack(FI),
636 if (!OutChains.empty())
637 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
638 &OutChains[0], OutChains.size());
644 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
645 SmallVectorImpl<SDValue> &InVals) const {
646 if (Subtarget->is64Bit())
647 return LowerCall_64(CLI, InVals);
648 return LowerCall_32(CLI, InVals);
651 // Lower a call for the 32-bit ABI.
653 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
654 SmallVectorImpl<SDValue> &InVals) const {
655 SelectionDAG &DAG = CLI.DAG;
657 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
658 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
659 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
660 SDValue Chain = CLI.Chain;
661 SDValue Callee = CLI.Callee;
662 bool &isTailCall = CLI.IsTailCall;
663 CallingConv::ID CallConv = CLI.CallConv;
664 bool isVarArg = CLI.IsVarArg;
666 // Sparc target does not yet support tail call optimization.
669 // Analyze operands of the call, assigning locations to each operand.
670 SmallVector<CCValAssign, 16> ArgLocs;
671 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
672 DAG.getTarget(), ArgLocs, *DAG.getContext());
673 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
675 // Get the size of the outgoing arguments stack space requirement.
676 unsigned ArgsSize = CCInfo.getNextStackOffset();
678 // Keep stack frames 8-byte aligned.
679 ArgsSize = (ArgsSize+7) & ~7;
681 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
683 // Create local copies for byval args.
684 SmallVector<SDValue, 8> ByValArgs;
685 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
686 ISD::ArgFlagsTy Flags = Outs[i].Flags;
687 if (!Flags.isByVal())
690 SDValue Arg = OutVals[i];
691 unsigned Size = Flags.getByValSize();
692 unsigned Align = Flags.getByValAlign();
694 int FI = MFI->CreateStackObject(Size, Align, false);
695 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
696 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
698 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
699 false, // isVolatile,
700 (Size <= 32), // AlwaysInline if size <= 32
701 MachinePointerInfo(), MachinePointerInfo());
702 ByValArgs.push_back(FIPtr);
705 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
708 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
709 SmallVector<SDValue, 8> MemOpChains;
711 const unsigned StackOffset = 92;
712 bool hasStructRetAttr = false;
713 // Walk the register/memloc assignments, inserting copies/loads.
714 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
717 CCValAssign &VA = ArgLocs[i];
718 SDValue Arg = OutVals[realArgIdx];
720 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
722 // Use local copy if it is a byval arg.
724 Arg = ByValArgs[byvalArgIdx++];
726 // Promote the value if needed.
727 switch (VA.getLocInfo()) {
728 default: llvm_unreachable("Unknown loc info!");
729 case CCValAssign::Full: break;
730 case CCValAssign::SExt:
731 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
733 case CCValAssign::ZExt:
734 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
736 case CCValAssign::AExt:
737 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
739 case CCValAssign::BCvt:
740 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
744 if (Flags.isSRet()) {
745 assert(VA.needsCustom());
746 // store SRet argument in %sp+64
747 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
748 SDValue PtrOff = DAG.getIntPtrConstant(64);
749 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
750 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
751 MachinePointerInfo(),
753 hasStructRetAttr = true;
757 if (VA.needsCustom()) {
758 assert(VA.getLocVT() == MVT::f64);
761 unsigned Offset = VA.getLocMemOffset() + StackOffset;
762 // if it is double-word aligned, just store.
763 if (Offset % 8 == 0) {
764 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
765 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
766 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
767 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
768 MachinePointerInfo(),
774 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
775 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
776 Arg, StackPtr, MachinePointerInfo(),
778 // Sparc is big-endian, so the high part comes first.
779 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
780 MachinePointerInfo(), false, false, false, 0);
781 // Increment the pointer to the other half.
782 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
783 DAG.getIntPtrConstant(4));
784 // Load the low part.
785 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
786 MachinePointerInfo(), false, false, false, 0);
789 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
791 CCValAssign &NextVA = ArgLocs[++i];
792 if (NextVA.isRegLoc()) {
793 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
795 // Store the low part in stack.
796 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
797 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
798 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
799 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
800 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
801 MachinePointerInfo(),
805 unsigned Offset = VA.getLocMemOffset() + StackOffset;
806 // Store the high part.
807 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
808 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
809 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
810 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
811 MachinePointerInfo(),
813 // Store the low part.
814 PtrOff = DAG.getIntPtrConstant(Offset+4);
815 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
816 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
817 MachinePointerInfo(),
823 // Arguments that can be passed on register must be kept at
826 if (VA.getLocVT() != MVT::f32) {
827 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
830 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
831 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
835 assert(VA.isMemLoc());
837 // Create a store off the stack pointer for this argument.
838 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
839 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
840 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
841 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
842 MachinePointerInfo(),
847 // Emit all stores, make sure the occur before any copies into physregs.
848 if (!MemOpChains.empty())
849 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
850 &MemOpChains[0], MemOpChains.size());
852 // Build a sequence of copy-to-reg nodes chained together with token
853 // chain and flag operands which copy the outgoing args into registers.
854 // The InFlag in necessary since all emitted instructions must be
857 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
858 unsigned Reg = toCallerWindow(RegsToPass[i].first);
859 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
860 InFlag = Chain.getValue(1);
863 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
865 // If the callee is a GlobalAddress node (quite common, every direct call is)
866 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
867 // Likewise ExternalSymbol -> TargetExternalSymbol.
868 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
869 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
870 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
871 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
873 // Returns a chain & a flag for retval copy to use
874 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
875 SmallVector<SDValue, 8> Ops;
876 Ops.push_back(Chain);
877 Ops.push_back(Callee);
878 if (hasStructRetAttr)
879 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
880 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
881 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
882 RegsToPass[i].second.getValueType()));
884 // Add a register mask operand representing the call-preserved registers.
885 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
886 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
887 assert(Mask && "Missing call preserved mask for calling convention");
888 Ops.push_back(DAG.getRegisterMask(Mask));
890 if (InFlag.getNode())
891 Ops.push_back(InFlag);
893 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
894 InFlag = Chain.getValue(1);
896 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
897 DAG.getIntPtrConstant(0, true), InFlag, dl);
898 InFlag = Chain.getValue(1);
900 // Assign locations to each value returned by this call.
901 SmallVector<CCValAssign, 16> RVLocs;
902 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
903 DAG.getTarget(), RVLocs, *DAG.getContext());
905 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
907 // Copy all of the result registers out of their specified physreg.
908 for (unsigned i = 0; i != RVLocs.size(); ++i) {
909 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
910 RVLocs[i].getValVT(), InFlag).getValue(1);
911 InFlag = Chain.getValue(2);
912 InVals.push_back(Chain.getValue(0));
919 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
921 const Function *CalleeFn = 0;
922 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
923 CalleeFn = dyn_cast<Function>(G->getGlobal());
924 } else if (ExternalSymbolSDNode *E =
925 dyn_cast<ExternalSymbolSDNode>(Callee)) {
926 const Function *Fn = DAG.getMachineFunction().getFunction();
927 const Module *M = Fn->getParent();
928 CalleeFn = M->getFunction(E->getSymbol());
934 assert(CalleeFn->hasStructRetAttr() &&
935 "Callee does not have the StructRet attribute.");
937 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
938 Type *ElementTy = Ty->getElementType();
939 return getDataLayout()->getTypeAllocSize(ElementTy);
943 // Fixup floating point arguments in the ... part of a varargs call.
945 // The SPARC v9 ABI requires that floating point arguments are treated the same
946 // as integers when calling a varargs function. This does not apply to the
947 // fixed arguments that are part of the function's prototype.
949 // This function post-processes a CCValAssign array created by
950 // AnalyzeCallOperands().
951 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
952 ArrayRef<ISD::OutputArg> Outs) {
953 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
954 const CCValAssign &VA = ArgLocs[i];
955 // FIXME: What about f32 arguments? C promotes them to f64 when calling
956 // varargs functions.
957 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64)
959 // The fixed arguments to a varargs function still go in FP registers.
960 if (Outs[VA.getValNo()].IsFixed)
963 // This floating point argument should be reassigned.
966 // Determine the offset into the argument array.
967 unsigned Offset = 8 * (VA.getLocReg() - SP::D0);
968 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
971 // This argument should go in %i0-%i5.
972 unsigned IReg = SP::I0 + Offset/8;
973 // Full register, just bitconvert into i64.
974 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
975 IReg, MVT::i64, CCValAssign::BCvt);
977 // This needs to go to memory, we're out of integer registers.
978 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
979 Offset, VA.getLocVT(), VA.getLocInfo());
985 // Lower a call for the 64-bit ABI.
987 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
988 SmallVectorImpl<SDValue> &InVals) const {
989 SelectionDAG &DAG = CLI.DAG;
991 SDValue Chain = CLI.Chain;
993 // Analyze operands of the call, assigning locations to each operand.
994 SmallVector<CCValAssign, 16> ArgLocs;
995 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
996 DAG.getTarget(), ArgLocs, *DAG.getContext());
997 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
999 // Get the size of the outgoing arguments stack space requirement.
1000 // The stack offset computed by CC_Sparc64 includes all arguments.
1001 // Called functions expect 6 argument words to exist in the stack frame, used
1003 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1005 // Keep stack frames 16-byte aligned.
1006 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1008 // Varargs calls require special treatment.
1010 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1012 // Adjust the stack pointer to make room for the arguments.
1013 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1014 // with more than 6 arguments.
1015 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1018 // Collect the set of registers to pass to the function and their values.
1019 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1021 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1023 // Collect chains from all the memory opeations that copy arguments to the
1024 // stack. They must follow the stack pointer adjustment above and precede the
1025 // call instruction itself.
1026 SmallVector<SDValue, 8> MemOpChains;
1028 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1029 const CCValAssign &VA = ArgLocs[i];
1030 SDValue Arg = CLI.OutVals[i];
1032 // Promote the value if needed.
1033 switch (VA.getLocInfo()) {
1035 llvm_unreachable("Unknown location info!");
1036 case CCValAssign::Full:
1038 case CCValAssign::SExt:
1039 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1041 case CCValAssign::ZExt:
1042 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1044 case CCValAssign::AExt:
1045 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1047 case CCValAssign::BCvt:
1048 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1052 if (VA.isRegLoc()) {
1053 // The custom bit on an i32 return value indicates that it should be
1054 // passed in the high bits of the register.
1055 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1056 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1057 DAG.getConstant(32, MVT::i32));
1059 // The next value may go in the low bits of the same register.
1060 // Handle both at once.
1061 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1062 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1063 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1065 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1066 // Skip the next value, it's already done.
1070 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1074 assert(VA.isMemLoc());
1076 // Create a store off the stack pointer for this argument.
1077 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1078 // The argument area starts at %fp+BIAS+128 in the callee frame,
1079 // %sp+BIAS+128 in ours.
1080 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1081 Subtarget->getStackPointerBias() +
1083 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1084 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1085 MachinePointerInfo(),
1089 // Emit all stores, make sure they occur before the call.
1090 if (!MemOpChains.empty())
1091 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1092 &MemOpChains[0], MemOpChains.size());
1094 // Build a sequence of CopyToReg nodes glued together with token chain and
1095 // glue operands which copy the outgoing args into registers. The InGlue is
1096 // necessary since all emitted instructions must be stuck together in order
1097 // to pass the live physical registers.
1099 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1100 Chain = DAG.getCopyToReg(Chain, DL,
1101 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1102 InGlue = Chain.getValue(1);
1105 // If the callee is a GlobalAddress node (quite common, every direct call is)
1106 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1107 // Likewise ExternalSymbol -> TargetExternalSymbol.
1108 SDValue Callee = CLI.Callee;
1109 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1110 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy());
1111 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1112 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
1114 // Build the operands for the call instruction itself.
1115 SmallVector<SDValue, 8> Ops;
1116 Ops.push_back(Chain);
1117 Ops.push_back(Callee);
1118 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1119 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1120 RegsToPass[i].second.getValueType()));
1122 // Add a register mask operand representing the call-preserved registers.
1123 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1124 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
1125 assert(Mask && "Missing call preserved mask for calling convention");
1126 Ops.push_back(DAG.getRegisterMask(Mask));
1128 // Make sure the CopyToReg nodes are glued to the call instruction which
1129 // consumes the registers.
1130 if (InGlue.getNode())
1131 Ops.push_back(InGlue);
1133 // Now the call itself.
1134 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1135 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
1136 InGlue = Chain.getValue(1);
1138 // Revert the stack pointer immediately after the call.
1139 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1140 DAG.getIntPtrConstant(0, true), InGlue, DL);
1141 InGlue = Chain.getValue(1);
1143 // Now extract the return values. This is more or less the same as
1144 // LowerFormalArguments_64.
1146 // Assign locations to each value returned by this call.
1147 SmallVector<CCValAssign, 16> RVLocs;
1148 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1149 DAG.getTarget(), RVLocs, *DAG.getContext());
1150 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
1152 // Copy all of the result registers out of their specified physreg.
1153 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1154 CCValAssign &VA = RVLocs[i];
1155 unsigned Reg = toCallerWindow(VA.getLocReg());
1157 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1158 // reside in the same register in the high and low bits. Reuse the
1159 // CopyFromReg previous node to avoid duplicate copies.
1161 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1162 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1163 RV = Chain.getValue(0);
1165 // But usually we'll create a new CopyFromReg for a different register.
1166 if (!RV.getNode()) {
1167 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1168 Chain = RV.getValue(1);
1169 InGlue = Chain.getValue(2);
1172 // Get the high bits for i32 struct elements.
1173 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1174 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1175 DAG.getConstant(32, MVT::i32));
1177 // The callee promoted the return value, so insert an Assert?ext SDNode so
1178 // we won't promote the value again in this function.
1179 switch (VA.getLocInfo()) {
1180 case CCValAssign::SExt:
1181 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1182 DAG.getValueType(VA.getValVT()));
1184 case CCValAssign::ZExt:
1185 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1186 DAG.getValueType(VA.getValVT()));
1192 // Truncate the register down to the return value type.
1193 if (VA.isExtInLoc())
1194 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1196 InVals.push_back(RV);
1202 //===----------------------------------------------------------------------===//
1203 // TargetLowering Implementation
1204 //===----------------------------------------------------------------------===//
1206 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1208 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1210 default: llvm_unreachable("Unknown integer condition code!");
1211 case ISD::SETEQ: return SPCC::ICC_E;
1212 case ISD::SETNE: return SPCC::ICC_NE;
1213 case ISD::SETLT: return SPCC::ICC_L;
1214 case ISD::SETGT: return SPCC::ICC_G;
1215 case ISD::SETLE: return SPCC::ICC_LE;
1216 case ISD::SETGE: return SPCC::ICC_GE;
1217 case ISD::SETULT: return SPCC::ICC_CS;
1218 case ISD::SETULE: return SPCC::ICC_LEU;
1219 case ISD::SETUGT: return SPCC::ICC_GU;
1220 case ISD::SETUGE: return SPCC::ICC_CC;
1224 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1226 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1228 default: llvm_unreachable("Unknown fp condition code!");
1230 case ISD::SETOEQ: return SPCC::FCC_E;
1232 case ISD::SETUNE: return SPCC::FCC_NE;
1234 case ISD::SETOLT: return SPCC::FCC_L;
1236 case ISD::SETOGT: return SPCC::FCC_G;
1238 case ISD::SETOLE: return SPCC::FCC_LE;
1240 case ISD::SETOGE: return SPCC::FCC_GE;
1241 case ISD::SETULT: return SPCC::FCC_UL;
1242 case ISD::SETULE: return SPCC::FCC_ULE;
1243 case ISD::SETUGT: return SPCC::FCC_UG;
1244 case ISD::SETUGE: return SPCC::FCC_UGE;
1245 case ISD::SETUO: return SPCC::FCC_U;
1246 case ISD::SETO: return SPCC::FCC_O;
1247 case ISD::SETONE: return SPCC::FCC_LG;
1248 case ISD::SETUEQ: return SPCC::FCC_UE;
1252 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1253 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
1254 Subtarget = &TM.getSubtarget<SparcSubtarget>();
1256 // Set up the register classes.
1257 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1258 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1259 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1260 if (Subtarget->is64Bit())
1261 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1263 // Turn FP extload into load/fextend
1264 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1265 // Sparc doesn't have i1 sign extending load
1266 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1267 // Turn FP truncstore into trunc + store.
1268 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1270 // Custom legalize GlobalAddress nodes into LO/HI parts.
1271 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1272 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1273 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1274 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1276 // Sparc doesn't have sext_inreg, replace them with shl/sra
1277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1279 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1281 // Sparc has no REM or DIVREM operations.
1282 setOperationAction(ISD::UREM, MVT::i32, Expand);
1283 setOperationAction(ISD::SREM, MVT::i32, Expand);
1284 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1285 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1287 // Custom expand fp<->sint
1288 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1289 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1292 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1293 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1295 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1296 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1298 // Sparc has no select or setcc: expand to SELECT_CC.
1299 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1300 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1301 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1302 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1303 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1304 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1306 // Sparc doesn't have BRCOND either, it has BR_CC.
1307 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1308 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1309 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1310 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1311 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1312 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1314 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1315 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1316 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1318 if (Subtarget->is64Bit()) {
1319 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1320 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1321 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1322 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1323 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1327 // FIXME: There are instructions available for ATOMIC_FENCE
1328 // on SparcV8 and later.
1329 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
1331 if (!Subtarget->isV9()) {
1332 // SparcV8 does not have FNEGD and FABSD.
1333 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1334 setOperationAction(ISD::FABS, MVT::f64, Custom);
1337 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1338 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1339 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1340 setOperationAction(ISD::FREM , MVT::f64, Expand);
1341 setOperationAction(ISD::FMA , MVT::f64, Expand);
1342 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1343 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1344 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1345 setOperationAction(ISD::FREM , MVT::f32, Expand);
1346 setOperationAction(ISD::FMA , MVT::f32, Expand);
1347 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1348 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1349 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1350 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1352 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1353 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1354 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1355 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1357 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1358 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1360 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1361 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1362 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1364 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1365 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1366 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1368 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
1370 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1371 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1372 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1373 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1375 // Use the default implementation.
1376 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1377 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1378 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1379 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1382 // No debug info support yet.
1383 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
1385 setStackPointerRegisterToSaveRestore(SP::O6);
1387 if (Subtarget->isV9())
1388 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1390 setMinFunctionAlignment(2);
1392 computeRegisterProperties();
1395 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1398 case SPISD::CMPICC: return "SPISD::CMPICC";
1399 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1400 case SPISD::BRICC: return "SPISD::BRICC";
1401 case SPISD::BRXCC: return "SPISD::BRXCC";
1402 case SPISD::BRFCC: return "SPISD::BRFCC";
1403 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1404 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1405 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1406 case SPISD::Hi: return "SPISD::Hi";
1407 case SPISD::Lo: return "SPISD::Lo";
1408 case SPISD::FTOI: return "SPISD::FTOI";
1409 case SPISD::ITOF: return "SPISD::ITOF";
1410 case SPISD::CALL: return "SPISD::CALL";
1411 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1412 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1413 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1417 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1418 /// be zero. Op is expected to be a target specific node. Used by DAG
1420 void SparcTargetLowering::computeMaskedBitsForTargetNode
1424 const SelectionDAG &DAG,
1425 unsigned Depth) const {
1426 APInt KnownZero2, KnownOne2;
1427 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1429 switch (Op.getOpcode()) {
1431 case SPISD::SELECT_ICC:
1432 case SPISD::SELECT_XCC:
1433 case SPISD::SELECT_FCC:
1434 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1435 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1436 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1437 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1439 // Only known if known in both the LHS and RHS.
1440 KnownOne &= KnownOne2;
1441 KnownZero &= KnownZero2;
1446 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1447 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1448 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1449 ISD::CondCode CC, unsigned &SPCC) {
1450 if (isa<ConstantSDNode>(RHS) &&
1451 cast<ConstantSDNode>(RHS)->isNullValue() &&
1453 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1454 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1455 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1456 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1457 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1458 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1459 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1460 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1461 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1462 SDValue CMPCC = LHS.getOperand(3);
1463 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1464 LHS = CMPCC.getOperand(0);
1465 RHS = CMPCC.getOperand(1);
1469 // Convert to a target node and set target flags.
1470 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1471 SelectionDAG &DAG) const {
1472 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1473 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1475 GA->getValueType(0),
1476 GA->getOffset(), TF);
1478 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1479 return DAG.getTargetConstantPool(CP->getConstVal(),
1480 CP->getValueType(0),
1482 CP->getOffset(), TF);
1484 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1485 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1490 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1491 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1492 ES->getValueType(0), TF);
1494 llvm_unreachable("Unhandled address SDNode");
1497 // Split Op into high and low parts according to HiTF and LoTF.
1498 // Return an ADD node combining the parts.
1499 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1500 unsigned HiTF, unsigned LoTF,
1501 SelectionDAG &DAG) const {
1503 EVT VT = Op.getValueType();
1504 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1505 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1506 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1509 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1510 // or ExternalSymbol SDNode.
1511 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1513 EVT VT = getPointerTy();
1515 // Handle PIC mode first.
1516 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1517 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1518 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1519 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1520 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1521 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1522 MachinePointerInfo::getGOT(), false, false, false, 0);
1525 // This is one of the absolute code models.
1526 switch(getTargetMachine().getCodeModel()) {
1528 llvm_unreachable("Unsupported absolute code model");
1529 case CodeModel::Small:
1531 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1532 case CodeModel::Medium: {
1534 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
1535 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1536 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
1537 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1538 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1540 case CodeModel::Large: {
1542 SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
1543 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1544 SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1545 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1550 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1551 SelectionDAG &DAG) const {
1552 return makeAddress(Op, DAG);
1555 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1556 SelectionDAG &DAG) const {
1557 return makeAddress(Op, DAG);
1560 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1561 SelectionDAG &DAG) const {
1562 return makeAddress(Op, DAG);
1565 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1567 // Convert the fp value to integer in an FP register.
1568 assert(Op.getValueType() == MVT::i32);
1569 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
1570 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
1573 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1575 assert(Op.getOperand(0).getValueType() == MVT::i32);
1576 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
1577 // Convert the int value to FP in an FP register.
1578 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
1581 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1582 SDValue Chain = Op.getOperand(0);
1583 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1584 SDValue LHS = Op.getOperand(2);
1585 SDValue RHS = Op.getOperand(3);
1586 SDValue Dest = Op.getOperand(4);
1588 unsigned Opc, SPCC = ~0U;
1590 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1591 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1592 LookThroughSetCC(LHS, RHS, CC, SPCC);
1594 // Get the condition flag.
1595 SDValue CompareFlag;
1596 if (LHS.getValueType().isInteger()) {
1597 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
1598 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1599 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
1600 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
1602 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1603 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1606 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
1607 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1610 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1611 SDValue LHS = Op.getOperand(0);
1612 SDValue RHS = Op.getOperand(1);
1613 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1614 SDValue TrueVal = Op.getOperand(2);
1615 SDValue FalseVal = Op.getOperand(3);
1617 unsigned Opc, SPCC = ~0U;
1619 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1620 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1621 LookThroughSetCC(LHS, RHS, CC, SPCC);
1623 SDValue CompareFlag;
1624 if (LHS.getValueType().isInteger()) {
1625 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
1626 Opc = LHS.getValueType() == MVT::i32 ?
1627 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
1628 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1630 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1631 Opc = SPISD::SELECT_FCC;
1632 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1634 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
1635 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1638 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1639 const SparcTargetLowering &TLI) {
1640 MachineFunction &MF = DAG.getMachineFunction();
1641 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1643 // Need frame address to find the address of VarArgsFrameIndex.
1644 MF.getFrameInfo()->setFrameAddressIsTaken(true);
1646 // vastart just stores the address of the VarArgsFrameIndex slot into the
1647 // memory location argument.
1650 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
1651 DAG.getRegister(SP::I6, TLI.getPointerTy()),
1652 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
1653 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1654 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
1655 MachinePointerInfo(SV), false, false, 0);
1658 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
1659 SDNode *Node = Op.getNode();
1660 EVT VT = Node->getValueType(0);
1661 SDValue InChain = Node->getOperand(0);
1662 SDValue VAListPtr = Node->getOperand(1);
1663 EVT PtrVT = VAListPtr.getValueType();
1664 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1666 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
1667 MachinePointerInfo(SV), false, false, false, 0);
1668 // Increment the pointer, VAList, to the next vaarg.
1669 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
1670 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
1671 // Store the incremented VAList to the legalized pointer.
1672 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
1673 VAListPtr, MachinePointerInfo(SV), false, false, 0);
1674 // Load the actual argument out of the pointer VAList.
1675 // We can't count on greater alignment than the word size.
1676 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
1677 false, false, false,
1678 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
1681 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1682 SDValue Chain = Op.getOperand(0); // Legalize the chain.
1683 SDValue Size = Op.getOperand(1); // Legalize the size.
1686 unsigned SPReg = SP::O6;
1687 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
1688 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
1689 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
1691 // The resultant pointer is actually 16 words from the bottom of the stack,
1692 // to provide a register spill area.
1693 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
1694 DAG.getConstant(96, MVT::i32));
1695 SDValue Ops[2] = { NewVal, Chain };
1696 return DAG.getMergeValues(Ops, 2, dl);
1700 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
1702 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
1703 dl, MVT::Other, DAG.getEntryNode());
1707 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1708 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1709 MFI->setFrameAddressIsTaken(true);
1711 EVT VT = Op.getValueType();
1713 unsigned FrameReg = SP::I6;
1715 uint64_t depth = Op.getConstantOperandVal(0);
1719 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1721 // flush first to make sure the windowed registers' values are in stack
1722 SDValue Chain = getFLUSHW(Op, DAG);
1723 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
1725 for (uint64_t i = 0; i != depth; ++i) {
1726 SDValue Ptr = DAG.getNode(ISD::ADD,
1728 FrameAddr, DAG.getIntPtrConstant(56));
1729 FrameAddr = DAG.getLoad(MVT::i32, dl,
1732 MachinePointerInfo(), false, false, false, 0);
1738 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
1739 const SparcTargetLowering &TLI) {
1740 MachineFunction &MF = DAG.getMachineFunction();
1741 MachineFrameInfo *MFI = MF.getFrameInfo();
1742 MFI->setReturnAddressIsTaken(true);
1744 EVT VT = Op.getValueType();
1746 uint64_t depth = Op.getConstantOperandVal(0);
1750 unsigned RetReg = MF.addLiveIn(SP::I7,
1751 TLI.getRegClassFor(TLI.getPointerTy()));
1752 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
1754 // Need frame address to find return address of the caller.
1755 MFI->setFrameAddressIsTaken(true);
1757 // flush first to make sure the windowed registers' values are in stack
1758 SDValue Chain = getFLUSHW(Op, DAG);
1759 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
1761 for (uint64_t i = 0; i != depth; ++i) {
1762 SDValue Ptr = DAG.getNode(ISD::ADD,
1765 DAG.getIntPtrConstant((i == depth-1)?60:56));
1766 RetAddr = DAG.getLoad(MVT::i32, dl,
1769 MachinePointerInfo(), false, false, false, 0);
1775 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG)
1779 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
1780 assert(Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS);
1782 // Lower fneg/fabs on f64 to fneg/fabs on f32.
1783 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
1784 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
1786 SDValue SrcReg64 = Op.getOperand(0);
1787 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
1789 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
1792 Hi32 = DAG.getNode(Op.getOpcode(), dl, MVT::f32, Hi32);
1794 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
1796 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
1798 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
1803 SDValue SparcTargetLowering::
1804 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1805 switch (Op.getOpcode()) {
1806 default: llvm_unreachable("Should not custom lower this!");
1809 case ISD::FABS: return LowerF64Op(Op, DAG);
1811 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this);
1812 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1813 case ISD::GlobalTLSAddress:
1814 llvm_unreachable("TLS not implemented for Sparc.");
1815 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1816 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1817 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1818 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1819 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1820 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1821 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1822 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
1823 case ISD::VAARG: return LowerVAARG(Op, DAG);
1824 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1829 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1830 MachineBasicBlock *BB) const {
1831 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1834 DebugLoc dl = MI->getDebugLoc();
1835 // Figure out the conditional branch opcode to use for this select_cc.
1836 switch (MI->getOpcode()) {
1837 default: llvm_unreachable("Unknown SELECT_CC!");
1838 case SP::SELECT_CC_Int_ICC:
1839 case SP::SELECT_CC_FP_ICC:
1840 case SP::SELECT_CC_DFP_ICC:
1841 BROpcode = SP::BCOND;
1843 case SP::SELECT_CC_Int_FCC:
1844 case SP::SELECT_CC_FP_FCC:
1845 case SP::SELECT_CC_DFP_FCC:
1846 BROpcode = SP::FBCOND;
1850 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
1852 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1853 // control-flow pattern. The incoming instruction knows the destination vreg
1854 // to set, the condition code register to branch on, the true/false values to
1855 // select between, and a branch opcode to use.
1856 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1857 MachineFunction::iterator It = BB;
1864 // fallthrough --> copy0MBB
1865 MachineBasicBlock *thisMBB = BB;
1866 MachineFunction *F = BB->getParent();
1867 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1868 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1869 F->insert(It, copy0MBB);
1870 F->insert(It, sinkMBB);
1872 // Transfer the remainder of BB and its successor edges to sinkMBB.
1873 sinkMBB->splice(sinkMBB->begin(), BB,
1874 llvm::next(MachineBasicBlock::iterator(MI)),
1876 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1878 // Add the true and fallthrough blocks as its successors.
1879 BB->addSuccessor(copy0MBB);
1880 BB->addSuccessor(sinkMBB);
1882 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1885 // %FalseValue = ...
1886 // # fallthrough to sinkMBB
1889 // Update machine-CFG edges
1890 BB->addSuccessor(sinkMBB);
1893 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1896 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1897 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1898 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1900 MI->eraseFromParent(); // The pseudo instruction is gone now.
1904 //===----------------------------------------------------------------------===//
1905 // Sparc Inline Assembly Support
1906 //===----------------------------------------------------------------------===//
1908 /// getConstraintType - Given a constraint letter, return the type of
1909 /// constraint it is for this target.
1910 SparcTargetLowering::ConstraintType
1911 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1912 if (Constraint.size() == 1) {
1913 switch (Constraint[0]) {
1915 case 'r': return C_RegisterClass;
1919 return TargetLowering::getConstraintType(Constraint);
1922 std::pair<unsigned, const TargetRegisterClass*>
1923 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1925 if (Constraint.size() == 1) {
1926 switch (Constraint[0]) {
1928 return std::make_pair(0U, &SP::IntRegsRegClass);
1932 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1936 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1937 // The Sparc target isn't yet aware of offsets.