1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcTargetMachine.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Support/ErrorHandling.h"
31 //===----------------------------------------------------------------------===//
32 // Calling Convention Implementation
33 //===----------------------------------------------------------------------===//
35 #include "SparcGenCallingConv.inc"
38 SparcTargetLowering::LowerReturn(SDValue Chain,
39 CallingConv::ID CallConv, bool isVarArg,
40 const SmallVectorImpl<ISD::OutputArg> &Outs,
41 DebugLoc dl, SelectionDAG &DAG) const {
43 // CCValAssign - represent the assignment of the return value to locations.
44 SmallVector<CCValAssign, 16> RVLocs;
46 // CCState - Info about the registers and stack slot.
47 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
48 RVLocs, *DAG.getContext());
50 // Analize return values.
51 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
53 // If this is the first return lowered for this function, add the regs to the
54 // liveout set for the function.
55 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
56 for (unsigned i = 0; i != RVLocs.size(); ++i)
57 if (RVLocs[i].isRegLoc())
58 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
63 // Copy the result values into the output registers.
64 for (unsigned i = 0; i != RVLocs.size(); ++i) {
65 CCValAssign &VA = RVLocs[i];
66 assert(VA.isRegLoc() && "Can only return in registers!");
68 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
71 // Guarantee that all emitted copies are stuck together with flags.
72 Flag = Chain.getValue(1);
76 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
77 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
80 /// LowerFormalArguments - V8 uses a very simple ABI, where all values are
81 /// passed in either one or two GPRs, including FP values. TODO: we should
82 /// pass FP values in FP registers for fastcc functions.
84 SparcTargetLowering::LowerFormalArguments(SDValue Chain,
85 CallingConv::ID CallConv, bool isVarArg,
86 const SmallVectorImpl<ISD::InputArg>
88 DebugLoc dl, SelectionDAG &DAG,
89 SmallVectorImpl<SDValue> &InVals)
92 MachineFunction &MF = DAG.getMachineFunction();
93 MachineRegisterInfo &RegInfo = MF.getRegInfo();
94 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
96 // Assign locations to all of the incoming arguments.
97 SmallVector<CCValAssign, 16> ArgLocs;
98 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
99 ArgLocs, *DAG.getContext());
100 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
102 static const unsigned ArgRegs[] = {
103 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
105 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
106 unsigned ArgOffset = 68;
108 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
110 CCValAssign &VA = ArgLocs[i];
111 // FIXME: We ignore the register assignments of AnalyzeFormalArguments
112 // because it doesn't know how to split a double into two i32 registers.
113 EVT ObjectVT = VA.getValVT();
114 switch (ObjectVT.getSimpleVT().SimpleTy) {
115 default: llvm_unreachable("Unhandled argument type!");
120 if (!Ins[i].Used) { // Argument is dead.
121 if (CurArgReg < ArgRegEnd) ++CurArgReg;
122 InVals.push_back(DAG.getUNDEF(ObjectVT));
123 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
124 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
125 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
126 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
127 if (ObjectVT != MVT::i32) {
128 unsigned AssertOp = ISD::AssertSext;
129 Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
130 DAG.getValueType(ObjectVT));
131 Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
133 InVals.push_back(Arg);
135 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
137 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
139 if (ObjectVT == MVT::i32) {
140 Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
143 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
145 // Sparc is big endian, so add an offset based on the ObjectVT.
146 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
147 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
148 DAG.getConstant(Offset, MVT::i32));
149 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
150 NULL, 0, ObjectVT, false, false, 0);
151 Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
153 InVals.push_back(Load);
159 if (!Ins[i].Used) { // Argument is dead.
160 if (CurArgReg < ArgRegEnd) ++CurArgReg;
161 InVals.push_back(DAG.getUNDEF(ObjectVT));
162 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
163 // FP value is passed in an integer register.
164 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
165 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
166 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
168 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
169 InVals.push_back(Arg);
171 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
173 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
174 SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0,
176 InVals.push_back(Load);
183 if (!Ins[i].Used) { // Argument is dead.
184 if (CurArgReg < ArgRegEnd) ++CurArgReg;
185 if (CurArgReg < ArgRegEnd) ++CurArgReg;
186 InVals.push_back(DAG.getUNDEF(ObjectVT));
189 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
190 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
191 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
192 HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
194 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
196 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
197 HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
202 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
203 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
204 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
205 LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
207 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4,
209 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
210 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
214 // Compose the two halves together into an i64 unit.
216 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
218 // If we want a double, do a bit convert.
219 if (ObjectVT == MVT::f64)
220 WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
222 InVals.push_back(WholeValue);
229 // Store remaining ArgRegs to the stack if this is a varargs function.
231 // Remember the vararg offset for the va_start implementation.
232 FuncInfo->setVarArgsFrameOffset(ArgOffset);
234 std::vector<SDValue> OutChains;
236 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
237 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
238 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
239 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
241 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
243 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
245 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0,
250 if (!OutChains.empty()) {
251 OutChains.push_back(Chain);
252 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
253 &OutChains[0], OutChains.size());
261 SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
262 CallingConv::ID CallConv, bool isVarArg,
264 const SmallVectorImpl<ISD::OutputArg> &Outs,
265 const SmallVectorImpl<ISD::InputArg> &Ins,
266 DebugLoc dl, SelectionDAG &DAG,
267 SmallVectorImpl<SDValue> &InVals) const {
268 // Sparc target does not yet support tail call optimization.
272 // Analyze operands of the call, assigning locations to each operand.
273 SmallVector<CCValAssign, 16> ArgLocs;
274 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs);
275 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
277 // Get the size of the outgoing arguments stack space requirement.
278 unsigned ArgsSize = CCInfo.getNextStackOffset();
279 // FIXME: We can't use this until f64 is known to take two GPRs.
283 // Count the size of the outgoing arguments.
284 unsigned ArgsSize = 0;
285 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
286 switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
287 default: llvm_unreachable("Unknown value type!");
302 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
307 // Keep stack frames 8-byte aligned.
308 ArgsSize = (ArgsSize+7) & ~7;
310 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
312 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
313 SmallVector<SDValue, 8> MemOpChains;
316 // Walk the register/memloc assignments, inserting copies/loads.
317 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
318 CCValAssign &VA = ArgLocs[i];
319 SDValue Arg = Outs[i].Val;
321 // Promote the value if needed.
322 switch (VA.getLocInfo()) {
323 default: llvm_unreachable("Unknown loc info!");
324 case CCValAssign::Full: break;
325 case CCValAssign::SExt:
326 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
328 case CCValAssign::ZExt:
329 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
331 case CCValAssign::AExt:
332 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
336 // Arguments that can be passed on register must be kept at
339 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
343 assert(VA.isMemLoc());
345 // Create a store off the stack pointer for this argument.
346 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
347 // FIXME: VERIFY THAT 68 IS RIGHT.
348 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
349 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
350 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0,
355 static const unsigned ArgRegs[] = {
356 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
358 unsigned ArgOffset = 68;
360 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
361 SDValue Val = Outs[i].Val;
362 EVT ObjectVT = Val.getValueType();
363 SDValue ValToStore(0, 0);
365 switch (ObjectVT.getSimpleVT().SimpleTy) {
366 default: llvm_unreachable("Unhandled argument type!");
370 if (RegsToPass.size() >= 6) {
373 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
378 if (RegsToPass.size() >= 6) {
381 // Convert this to a FP value in an int reg.
382 Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
383 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
388 if (RegsToPass.size() >= 6) {
389 ValToStore = Val; // Whole thing is passed in memory.
393 // Break into top and bottom parts by storing to the stack and loading
394 // out the parts as integers. Top part goes in a reg.
395 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
396 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
397 Val, StackPtr, NULL, 0,
399 // Sparc is big-endian, so the high part comes first.
400 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0,
402 // Increment the pointer to the other half.
403 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
404 DAG.getIntPtrConstant(4));
405 // Load the low part.
406 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0,
409 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
411 if (RegsToPass.size() >= 6) {
416 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
422 if (RegsToPass.size() >= 6) {
423 ValToStore = Val; // Whole thing is passed in memory.
427 // Split the value into top and bottom part. Top part goes in a reg.
428 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
429 DAG.getConstant(1, MVT::i32));
430 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
431 DAG.getConstant(0, MVT::i32));
432 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
434 if (RegsToPass.size() >= 6) {
439 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
445 if (ValToStore.getNode()) {
446 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
447 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
448 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
449 MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
453 ArgOffset += ObjSize;
457 // Emit all stores, make sure the occur before any copies into physregs.
458 if (!MemOpChains.empty())
459 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
460 &MemOpChains[0], MemOpChains.size());
462 // Build a sequence of copy-to-reg nodes chained together with token
463 // chain and flag operands which copy the outgoing args into registers.
464 // The InFlag in necessary since all emited instructions must be
467 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
468 unsigned Reg = RegsToPass[i].first;
469 // Remap I0->I7 -> O0->O7.
470 if (Reg >= SP::I0 && Reg <= SP::I7)
471 Reg = Reg-SP::I0+SP::O0;
473 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
474 InFlag = Chain.getValue(1);
477 // If the callee is a GlobalAddress node (quite common, every direct call is)
478 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
479 // Likewise ExternalSymbol -> TargetExternalSymbol.
480 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
481 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
482 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
483 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
485 std::vector<EVT> NodeTys;
486 NodeTys.push_back(MVT::Other); // Returns a chain
487 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
488 SDValue Ops[] = { Chain, Callee, InFlag };
489 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
490 InFlag = Chain.getValue(1);
492 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
493 DAG.getIntPtrConstant(0, true), InFlag);
494 InFlag = Chain.getValue(1);
496 // Assign locations to each value returned by this call.
497 SmallVector<CCValAssign, 16> RVLocs;
498 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(),
499 RVLocs, *DAG.getContext());
501 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
503 // Copy all of the result registers out of their specified physreg.
504 for (unsigned i = 0; i != RVLocs.size(); ++i) {
505 unsigned Reg = RVLocs[i].getLocReg();
507 // Remap I0->I7 -> O0->O7.
508 if (Reg >= SP::I0 && Reg <= SP::I7)
509 Reg = Reg-SP::I0+SP::O0;
511 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
512 RVLocs[i].getValVT(), InFlag).getValue(1);
513 InFlag = Chain.getValue(2);
514 InVals.push_back(Chain.getValue(0));
522 //===----------------------------------------------------------------------===//
523 // TargetLowering Implementation
524 //===----------------------------------------------------------------------===//
526 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
528 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
530 default: llvm_unreachable("Unknown integer condition code!");
531 case ISD::SETEQ: return SPCC::ICC_E;
532 case ISD::SETNE: return SPCC::ICC_NE;
533 case ISD::SETLT: return SPCC::ICC_L;
534 case ISD::SETGT: return SPCC::ICC_G;
535 case ISD::SETLE: return SPCC::ICC_LE;
536 case ISD::SETGE: return SPCC::ICC_GE;
537 case ISD::SETULT: return SPCC::ICC_CS;
538 case ISD::SETULE: return SPCC::ICC_LEU;
539 case ISD::SETUGT: return SPCC::ICC_GU;
540 case ISD::SETUGE: return SPCC::ICC_CC;
544 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
546 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
548 default: llvm_unreachable("Unknown fp condition code!");
550 case ISD::SETOEQ: return SPCC::FCC_E;
552 case ISD::SETUNE: return SPCC::FCC_NE;
554 case ISD::SETOLT: return SPCC::FCC_L;
556 case ISD::SETOGT: return SPCC::FCC_G;
558 case ISD::SETOLE: return SPCC::FCC_LE;
560 case ISD::SETOGE: return SPCC::FCC_GE;
561 case ISD::SETULT: return SPCC::FCC_UL;
562 case ISD::SETULE: return SPCC::FCC_ULE;
563 case ISD::SETUGT: return SPCC::FCC_UG;
564 case ISD::SETUGE: return SPCC::FCC_UGE;
565 case ISD::SETUO: return SPCC::FCC_U;
566 case ISD::SETO: return SPCC::FCC_O;
567 case ISD::SETONE: return SPCC::FCC_LG;
568 case ISD::SETUEQ: return SPCC::FCC_UE;
572 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
573 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
575 // Set up the register classes.
576 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
577 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
578 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
580 // Turn FP extload into load/fextend
581 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
582 // Sparc doesn't have i1 sign extending load
583 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
584 // Turn FP truncstore into trunc + store.
585 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
587 // Custom legalize GlobalAddress nodes into LO/HI parts.
588 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
590 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
592 // Sparc doesn't have sext_inreg, replace them with shl/sra
593 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
594 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
595 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
597 // Sparc has no REM or DIVREM operations.
598 setOperationAction(ISD::UREM, MVT::i32, Expand);
599 setOperationAction(ISD::SREM, MVT::i32, Expand);
600 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
601 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
603 // Custom expand fp<->sint
604 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
605 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
608 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
609 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
611 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
612 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
614 // Sparc has no select or setcc: expand to SELECT_CC.
615 setOperationAction(ISD::SELECT, MVT::i32, Expand);
616 setOperationAction(ISD::SELECT, MVT::f32, Expand);
617 setOperationAction(ISD::SELECT, MVT::f64, Expand);
618 setOperationAction(ISD::SETCC, MVT::i32, Expand);
619 setOperationAction(ISD::SETCC, MVT::f32, Expand);
620 setOperationAction(ISD::SETCC, MVT::f64, Expand);
622 // Sparc doesn't have BRCOND either, it has BR_CC.
623 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
624 setOperationAction(ISD::BRIND, MVT::Other, Expand);
625 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
626 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
627 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
628 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
634 // SPARC has no intrinsics for these particular operations.
635 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
637 setOperationAction(ISD::FSIN , MVT::f64, Expand);
638 setOperationAction(ISD::FCOS , MVT::f64, Expand);
639 setOperationAction(ISD::FREM , MVT::f64, Expand);
640 setOperationAction(ISD::FSIN , MVT::f32, Expand);
641 setOperationAction(ISD::FCOS , MVT::f32, Expand);
642 setOperationAction(ISD::FREM , MVT::f32, Expand);
643 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
644 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
645 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
646 setOperationAction(ISD::ROTL , MVT::i32, Expand);
647 setOperationAction(ISD::ROTR , MVT::i32, Expand);
648 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
650 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
651 setOperationAction(ISD::FPOW , MVT::f64, Expand);
652 setOperationAction(ISD::FPOW , MVT::f32, Expand);
654 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
655 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
656 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
658 // FIXME: Sparc provides these multiplies, but we don't have them yet.
659 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
660 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
662 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
664 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
665 setOperationAction(ISD::VASTART , MVT::Other, Custom);
666 // VAARG needs to be lowered to not do unaligned accesses for doubles.
667 setOperationAction(ISD::VAARG , MVT::Other, Custom);
669 // Use the default implementation.
670 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
671 setOperationAction(ISD::VAEND , MVT::Other, Expand);
672 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
673 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
674 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
676 // No debug info support yet.
677 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
679 setStackPointerRegisterToSaveRestore(SP::O6);
681 if (TM.getSubtarget<SparcSubtarget>().isV9())
682 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
684 computeRegisterProperties();
687 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
690 case SPISD::CMPICC: return "SPISD::CMPICC";
691 case SPISD::CMPFCC: return "SPISD::CMPFCC";
692 case SPISD::BRICC: return "SPISD::BRICC";
693 case SPISD::BRFCC: return "SPISD::BRFCC";
694 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
695 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
696 case SPISD::Hi: return "SPISD::Hi";
697 case SPISD::Lo: return "SPISD::Lo";
698 case SPISD::FTOI: return "SPISD::FTOI";
699 case SPISD::ITOF: return "SPISD::ITOF";
700 case SPISD::CALL: return "SPISD::CALL";
701 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
705 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
706 /// be zero. Op is expected to be a target specific node. Used by DAG
708 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
712 const SelectionDAG &DAG,
713 unsigned Depth) const {
714 APInt KnownZero2, KnownOne2;
715 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
717 switch (Op.getOpcode()) {
719 case SPISD::SELECT_ICC:
720 case SPISD::SELECT_FCC:
721 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
723 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
725 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
728 // Only known if known in both the LHS and RHS.
729 KnownOne &= KnownOne2;
730 KnownZero &= KnownZero2;
735 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
736 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
737 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
738 ISD::CondCode CC, unsigned &SPCC) {
739 if (isa<ConstantSDNode>(RHS) &&
740 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
742 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
743 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
744 (LHS.getOpcode() == SPISD::SELECT_FCC &&
745 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
746 isa<ConstantSDNode>(LHS.getOperand(0)) &&
747 isa<ConstantSDNode>(LHS.getOperand(1)) &&
748 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
749 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
750 SDValue CMPCC = LHS.getOperand(3);
751 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
752 LHS = CMPCC.getOperand(0);
753 RHS = CMPCC.getOperand(1);
757 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
758 SelectionDAG &DAG) const {
759 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
760 // FIXME there isn't really any debug info here
761 DebugLoc dl = Op.getDebugLoc();
762 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
763 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
764 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
766 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
767 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
769 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
771 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
772 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
773 GlobalBase, RelAddr);
774 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
775 AbsAddr, NULL, 0, false, false, 0);
778 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
779 SelectionDAG &DAG) const {
780 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
781 // FIXME there isn't really any debug info here
782 DebugLoc dl = Op.getDebugLoc();
783 const Constant *C = N->getConstVal();
784 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
785 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
786 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
787 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
788 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
790 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
792 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
793 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
794 GlobalBase, RelAddr);
795 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
796 AbsAddr, NULL, 0, false, false, 0);
799 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
800 DebugLoc dl = Op.getDebugLoc();
801 // Convert the fp value to integer in an FP register.
802 assert(Op.getValueType() == MVT::i32);
803 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
804 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
807 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
808 DebugLoc dl = Op.getDebugLoc();
809 assert(Op.getOperand(0).getValueType() == MVT::i32);
810 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
811 // Convert the int value to FP in an FP register.
812 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
815 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
816 SDValue Chain = Op.getOperand(0);
817 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
818 SDValue LHS = Op.getOperand(2);
819 SDValue RHS = Op.getOperand(3);
820 SDValue Dest = Op.getOperand(4);
821 DebugLoc dl = Op.getDebugLoc();
822 unsigned Opc, SPCC = ~0U;
824 // If this is a br_cc of a "setcc", and if the setcc got lowered into
825 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
826 LookThroughSetCC(LHS, RHS, CC, SPCC);
828 // Get the condition flag.
830 if (LHS.getValueType() == MVT::i32) {
831 std::vector<EVT> VTs;
832 VTs.push_back(MVT::i32);
833 VTs.push_back(MVT::Flag);
834 SDValue Ops[2] = { LHS, RHS };
835 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
836 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
839 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
840 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
843 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
844 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
847 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
848 SDValue LHS = Op.getOperand(0);
849 SDValue RHS = Op.getOperand(1);
850 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
851 SDValue TrueVal = Op.getOperand(2);
852 SDValue FalseVal = Op.getOperand(3);
853 DebugLoc dl = Op.getDebugLoc();
854 unsigned Opc, SPCC = ~0U;
856 // If this is a select_cc of a "setcc", and if the setcc got lowered into
857 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
858 LookThroughSetCC(LHS, RHS, CC, SPCC);
861 if (LHS.getValueType() == MVT::i32) {
862 std::vector<EVT> VTs;
863 VTs.push_back(LHS.getValueType()); // subcc returns a value
864 VTs.push_back(MVT::Flag);
865 SDValue Ops[2] = { LHS, RHS };
866 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
867 Opc = SPISD::SELECT_ICC;
868 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
870 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
871 Opc = SPISD::SELECT_FCC;
872 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
874 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
875 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
878 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
879 const SparcTargetLowering &TLI) {
880 MachineFunction &MF = DAG.getMachineFunction();
881 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
883 // vastart just stores the address of the VarArgsFrameIndex slot into the
884 // memory location argument.
885 DebugLoc dl = Op.getDebugLoc();
887 DAG.getNode(ISD::ADD, dl, MVT::i32,
888 DAG.getRegister(SP::I6, MVT::i32),
889 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
891 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
892 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0,
896 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
897 SDNode *Node = Op.getNode();
898 EVT VT = Node->getValueType(0);
899 SDValue InChain = Node->getOperand(0);
900 SDValue VAListPtr = Node->getOperand(1);
901 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
902 DebugLoc dl = Node->getDebugLoc();
903 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0,
905 // Increment the pointer, VAList, to the next vaarg
906 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
907 DAG.getConstant(VT.getSizeInBits()/8,
909 // Store the incremented VAList to the legalized pointer
910 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
911 VAListPtr, SV, 0, false, false, 0);
912 // Load the actual argument out of the pointer VAList, unless this is an
915 return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0, false, false, 0);
917 // Otherwise, load it as i64, then do a bitconvert.
918 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0,
921 // Bit-Convert the value to f64.
923 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
926 return DAG.getMergeValues(Ops, 2, dl);
929 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
930 SDValue Chain = Op.getOperand(0); // Legalize the chain.
931 SDValue Size = Op.getOperand(1); // Legalize the size.
932 DebugLoc dl = Op.getDebugLoc();
934 unsigned SPReg = SP::O6;
935 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
936 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
937 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
939 // The resultant pointer is actually 16 words from the bottom of the stack,
940 // to provide a register spill area.
941 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
942 DAG.getConstant(96, MVT::i32));
943 SDValue Ops[2] = { NewVal, Chain };
944 return DAG.getMergeValues(Ops, 2, dl);
948 SDValue SparcTargetLowering::
949 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
950 switch (Op.getOpcode()) {
951 default: llvm_unreachable("Should not custom lower this!");
952 // Frame & Return address. Currently unimplemented
953 case ISD::RETURNADDR: return SDValue();
954 case ISD::FRAMEADDR: return SDValue();
955 case ISD::GlobalTLSAddress:
956 llvm_unreachable("TLS not implemented for Sparc.");
957 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
958 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
959 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
960 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
961 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
962 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
963 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
964 case ISD::VAARG: return LowerVAARG(Op, DAG);
965 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
970 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
971 MachineBasicBlock *BB) const {
972 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
975 DebugLoc dl = MI->getDebugLoc();
976 // Figure out the conditional branch opcode to use for this select_cc.
977 switch (MI->getOpcode()) {
978 default: llvm_unreachable("Unknown SELECT_CC!");
979 case SP::SELECT_CC_Int_ICC:
980 case SP::SELECT_CC_FP_ICC:
981 case SP::SELECT_CC_DFP_ICC:
982 BROpcode = SP::BCOND;
984 case SP::SELECT_CC_Int_FCC:
985 case SP::SELECT_CC_FP_FCC:
986 case SP::SELECT_CC_DFP_FCC:
987 BROpcode = SP::FBCOND;
991 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
993 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
994 // control-flow pattern. The incoming instruction knows the destination vreg
995 // to set, the condition code register to branch on, the true/false values to
996 // select between, and a branch opcode to use.
997 const BasicBlock *LLVM_BB = BB->getBasicBlock();
998 MachineFunction::iterator It = BB;
1005 // fallthrough --> copy0MBB
1006 MachineBasicBlock *thisMBB = BB;
1007 MachineFunction *F = BB->getParent();
1008 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1009 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1010 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1011 F->insert(It, copy0MBB);
1012 F->insert(It, sinkMBB);
1013 // Update machine-CFG edges by first adding all successors of the current
1014 // block to the new block which will contain the Phi node for the select.
1015 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
1016 E = BB->succ_end(); I != E; ++I)
1017 sinkMBB->addSuccessor(*I);
1018 // Next, remove all successors of the current block, and add the true
1019 // and fallthrough blocks as its successors.
1020 while (!BB->succ_empty())
1021 BB->removeSuccessor(BB->succ_begin());
1022 // Next, add the true and fallthrough blocks as its successors.
1023 BB->addSuccessor(copy0MBB);
1024 BB->addSuccessor(sinkMBB);
1027 // %FalseValue = ...
1028 // # fallthrough to sinkMBB
1031 // Update machine-CFG edges
1032 BB->addSuccessor(sinkMBB);
1035 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1038 BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1039 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1040 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1042 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1046 //===----------------------------------------------------------------------===//
1047 // Sparc Inline Assembly Support
1048 //===----------------------------------------------------------------------===//
1050 /// getConstraintType - Given a constraint letter, return the type of
1051 /// constraint it is for this target.
1052 SparcTargetLowering::ConstraintType
1053 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1054 if (Constraint.size() == 1) {
1055 switch (Constraint[0]) {
1057 case 'r': return C_RegisterClass;
1061 return TargetLowering::getConstraintType(Constraint);
1064 std::pair<unsigned, const TargetRegisterClass*>
1065 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1067 if (Constraint.size() == 1) {
1068 switch (Constraint[0]) {
1070 return std::make_pair(0U, SP::IntRegsRegisterClass);
1074 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1077 std::vector<unsigned> SparcTargetLowering::
1078 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1080 if (Constraint.size() != 1)
1081 return std::vector<unsigned>();
1083 switch (Constraint[0]) {
1086 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1087 SP::L4, SP::L5, SP::L6, SP::L7,
1088 SP::I0, SP::I1, SP::I2, SP::I3,
1090 SP::O0, SP::O1, SP::O2, SP::O3,
1091 SP::O4, SP::O5, SP::O7, 0);
1094 return std::vector<unsigned>();
1098 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1099 // The Sparc target isn't yet aware of offsets.
1103 /// getFunctionAlignment - Return the Log2 alignment of this function.
1104 unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const {