1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcTargetMachine.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Module.h"
28 #include "llvm/Support/ErrorHandling.h"
32 //===----------------------------------------------------------------------===//
33 // Calling Convention Implementation
34 //===----------------------------------------------------------------------===//
36 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
37 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
38 ISD::ArgFlagsTy &ArgFlags, CCState &State)
40 assert (ArgFlags.isSRet());
42 //Assign SRet argument
43 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
49 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
50 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags, CCState &State)
53 static const uint16_t RegList[] = {
54 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
56 //Try to get first reg
57 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
58 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
60 //Assign whole thing in stack
61 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
62 State.AllocateStack(8,4),
67 //Try to get second reg
68 if (unsigned Reg = State.AllocateReg(RegList, 6))
69 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
71 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
72 State.AllocateStack(4,4),
77 // Allocate a full-sized argument for the 64-bit ABI.
78 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
79 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
80 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
81 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
82 "Can't handle non-64 bits locations");
84 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
85 unsigned Offset = State.AllocateStack(8, 8);
88 if (LocVT == MVT::i64 && Offset < 6*8)
89 // Promote integers to %i0-%i5.
90 Reg = SP::I0 + Offset/8;
91 else if (LocVT == MVT::f64 && Offset < 16*8)
92 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
93 Reg = SP::D0 + Offset/8;
94 else if (LocVT == MVT::f32 && Offset < 16*8)
95 // Promote floats to %f1, %f3, ...
96 Reg = SP::F1 + Offset/4;
98 // Promote to register when possible, otherwise use the stack slot.
100 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
104 // This argument goes on the stack in an 8-byte slot.
105 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
106 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
107 if (LocVT == MVT::f32)
110 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
114 // Allocate a half-sized argument for the 64-bit ABI.
116 // This is used when passing { float, int } structs by value in registers.
117 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
118 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
119 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
120 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
121 unsigned Offset = State.AllocateStack(4, 4);
123 if (LocVT == MVT::f32 && Offset < 16*8) {
124 // Promote floats to %f0-%f31.
125 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
130 if (LocVT == MVT::i32 && Offset < 6*8) {
131 // Promote integers to %i0-%i5, using half the register.
132 unsigned Reg = SP::I0 + Offset/8;
134 LocInfo = CCValAssign::AExt;
136 // Set the Custom bit if this i32 goes in the high bits of a register.
138 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
141 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
145 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
149 #include "SparcGenCallingConv.inc"
152 SparcTargetLowering::LowerReturn(SDValue Chain,
153 CallingConv::ID CallConv, bool isVarArg,
154 const SmallVectorImpl<ISD::OutputArg> &Outs,
155 const SmallVectorImpl<SDValue> &OutVals,
156 DebugLoc dl, SelectionDAG &DAG) const {
158 MachineFunction &MF = DAG.getMachineFunction();
160 // CCValAssign - represent the assignment of the return value to locations.
161 SmallVector<CCValAssign, 16> RVLocs;
163 // CCState - Info about the registers and stack slot.
164 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
165 DAG.getTarget(), RVLocs, *DAG.getContext());
167 // Analize return values.
168 CCInfo.AnalyzeReturn(Outs, Subtarget->is64Bit() ? CC_Sparc64 : RetCC_Sparc32);
171 SmallVector<SDValue, 4> RetOps(1, Chain);
172 // Make room for the return address offset.
173 RetOps.push_back(SDValue());
175 // Copy the result values into the output registers.
176 for (unsigned i = 0; i != RVLocs.size(); ++i) {
177 CCValAssign &VA = RVLocs[i];
178 assert(VA.isRegLoc() && "Can only return in registers!");
180 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
183 // Guarantee that all emitted copies are stuck together with flags.
184 Flag = Chain.getValue(1);
185 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
188 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot
189 // If the function returns a struct, copy the SRetReturnReg to I0
190 if (MF.getFunction()->hasStructRetAttr()) {
191 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
192 unsigned Reg = SFI->getSRetReturnReg();
194 llvm_unreachable("sret virtual register not created in the entry block");
195 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
196 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag);
197 Flag = Chain.getValue(1);
198 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
199 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
202 RetOps[0] = Chain; // Update chain.
203 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
205 // Add the flag if we have it.
207 RetOps.push_back(Flag);
209 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other,
210 &RetOps[0], RetOps.size());
213 SDValue SparcTargetLowering::
214 LowerFormalArguments(SDValue Chain,
215 CallingConv::ID CallConv,
217 const SmallVectorImpl<ISD::InputArg> &Ins,
220 SmallVectorImpl<SDValue> &InVals) const {
221 if (Subtarget->is64Bit())
222 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
224 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
228 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
229 /// passed in either one or two GPRs, including FP values. TODO: we should
230 /// pass FP values in FP registers for fastcc functions.
231 SDValue SparcTargetLowering::
232 LowerFormalArguments_32(SDValue Chain,
233 CallingConv::ID CallConv,
235 const SmallVectorImpl<ISD::InputArg> &Ins,
238 SmallVectorImpl<SDValue> &InVals) const {
239 MachineFunction &MF = DAG.getMachineFunction();
240 MachineRegisterInfo &RegInfo = MF.getRegInfo();
241 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
243 // Assign locations to all of the incoming arguments.
244 SmallVector<CCValAssign, 16> ArgLocs;
245 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
246 getTargetMachine(), ArgLocs, *DAG.getContext());
247 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
249 const unsigned StackOffset = 92;
251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
252 CCValAssign &VA = ArgLocs[i];
254 if (i == 0 && Ins[i].Flags.isSRet()) {
255 //Get SRet from [%fp+64]
256 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
257 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
258 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
259 MachinePointerInfo(),
260 false, false, false, 0);
261 InVals.push_back(Arg);
266 if (VA.needsCustom()) {
267 assert(VA.getLocVT() == MVT::f64);
268 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
269 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
270 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
273 CCValAssign &NextVA = ArgLocs[++i];
276 if (NextVA.isMemLoc()) {
277 int FrameIdx = MF.getFrameInfo()->
278 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
279 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
280 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
281 MachinePointerInfo(),
282 false, false, false, 0);
284 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
285 &SP::IntRegsRegClass);
286 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
289 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
290 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
291 InVals.push_back(WholeValue);
294 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
295 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
296 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
297 if (VA.getLocVT() == MVT::f32)
298 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
299 else if (VA.getLocVT() != MVT::i32) {
300 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
301 DAG.getValueType(VA.getLocVT()));
302 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
304 InVals.push_back(Arg);
308 assert(VA.isMemLoc());
310 unsigned Offset = VA.getLocMemOffset()+StackOffset;
312 if (VA.needsCustom()) {
313 assert(VA.getValVT() == MVT::f64);
314 //If it is double-word aligned, just load.
315 if (Offset % 8 == 0) {
316 int FI = MF.getFrameInfo()->CreateFixedObject(8,
319 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
320 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
321 MachinePointerInfo(),
322 false,false, false, 0);
323 InVals.push_back(Load);
327 int FI = MF.getFrameInfo()->CreateFixedObject(4,
330 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
331 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
332 MachinePointerInfo(),
333 false, false, false, 0);
334 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
337 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
339 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
340 MachinePointerInfo(),
341 false, false, false, 0);
344 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
345 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
346 InVals.push_back(WholeValue);
350 int FI = MF.getFrameInfo()->CreateFixedObject(4,
353 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
355 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
356 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
357 MachinePointerInfo(),
358 false, false, false, 0);
360 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
361 // Sparc is big endian, so add an offset based on the ObjectVT.
362 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
363 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
364 DAG.getConstant(Offset, MVT::i32));
365 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
366 MachinePointerInfo(),
367 VA.getValVT(), false, false,0);
368 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
370 InVals.push_back(Load);
373 if (MF.getFunction()->hasStructRetAttr()) {
374 //Copy the SRet Argument to SRetReturnReg
375 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
376 unsigned Reg = SFI->getSRetReturnReg();
378 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
379 SFI->setSRetReturnReg(Reg);
381 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
382 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
385 // Store remaining ArgRegs to the stack if this is a varargs function.
387 static const uint16_t ArgRegs[] = {
388 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
390 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
391 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
392 unsigned ArgOffset = CCInfo.getNextStackOffset();
393 if (NumAllocated == 6)
394 ArgOffset += StackOffset;
397 ArgOffset = 68+4*NumAllocated;
400 // Remember the vararg offset for the va_start implementation.
401 FuncInfo->setVarArgsFrameOffset(ArgOffset);
403 std::vector<SDValue> OutChains;
405 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
406 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
407 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
408 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
410 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
412 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
414 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
415 MachinePointerInfo(),
420 if (!OutChains.empty()) {
421 OutChains.push_back(Chain);
422 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
423 &OutChains[0], OutChains.size());
430 // Lower formal arguments for the 64 bit ABI.
431 SDValue SparcTargetLowering::
432 LowerFormalArguments_64(SDValue Chain,
433 CallingConv::ID CallConv,
435 const SmallVectorImpl<ISD::InputArg> &Ins,
438 SmallVectorImpl<SDValue> &InVals) const {
439 MachineFunction &MF = DAG.getMachineFunction();
441 // Analyze arguments according to CC_Sparc64.
442 SmallVector<CCValAssign, 16> ArgLocs;
443 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
444 getTargetMachine(), ArgLocs, *DAG.getContext());
445 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
448 CCValAssign &VA = ArgLocs[i];
450 // This argument is passed in a register.
451 // All integer register arguments are promoted by the caller to i64.
453 // Create a virtual register for the promoted live-in value.
454 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
455 getRegClassFor(VA.getLocVT()));
456 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
458 // Get the high bits for i32 struct elements.
459 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
460 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
461 DAG.getConstant(32, MVT::i32));
463 // The caller promoted the argument, so insert an Assert?ext SDNode so we
464 // won't promote the value again in this function.
465 switch (VA.getLocInfo()) {
466 case CCValAssign::SExt:
467 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
468 DAG.getValueType(VA.getValVT()));
470 case CCValAssign::ZExt:
471 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
472 DAG.getValueType(VA.getValVT()));
478 // Truncate the register down to the argument type.
480 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
482 InVals.push_back(Arg);
486 // The registers are exhausted. This argument was passed on the stack.
487 assert(VA.isMemLoc());
488 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
489 // beginning of the arguments area at %fp+BIAS+128.
490 unsigned Offset = VA.getLocMemOffset() + 128;
491 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
492 // Adjust offset for extended arguments, SPARC is big-endian.
493 // The caller will have written the full slot with extended bytes, but we
494 // prefer our own extending loads.
496 Offset += 8 - ValSize;
497 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
498 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
499 DAG.getFrameIndex(FI, getPointerTy()),
500 MachinePointerInfo::getFixedStack(FI),
501 false, false, false, 0));
507 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
508 SmallVectorImpl<SDValue> &InVals) const {
509 SelectionDAG &DAG = CLI.DAG;
510 DebugLoc &dl = CLI.DL;
511 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
512 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
513 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
514 SDValue Chain = CLI.Chain;
515 SDValue Callee = CLI.Callee;
516 bool &isTailCall = CLI.IsTailCall;
517 CallingConv::ID CallConv = CLI.CallConv;
518 bool isVarArg = CLI.IsVarArg;
520 // Sparc target does not yet support tail call optimization.
523 // Analyze operands of the call, assigning locations to each operand.
524 SmallVector<CCValAssign, 16> ArgLocs;
525 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
526 DAG.getTarget(), ArgLocs, *DAG.getContext());
527 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
529 // Get the size of the outgoing arguments stack space requirement.
530 unsigned ArgsSize = CCInfo.getNextStackOffset();
532 // Keep stack frames 8-byte aligned.
533 ArgsSize = (ArgsSize+7) & ~7;
535 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
537 //Create local copies for byval args.
538 SmallVector<SDValue, 8> ByValArgs;
539 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
540 ISD::ArgFlagsTy Flags = Outs[i].Flags;
541 if (!Flags.isByVal())
544 SDValue Arg = OutVals[i];
545 unsigned Size = Flags.getByValSize();
546 unsigned Align = Flags.getByValAlign();
548 int FI = MFI->CreateStackObject(Size, Align, false);
549 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
550 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
552 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
554 (Size <= 32), //AlwaysInline if size <= 32
555 MachinePointerInfo(), MachinePointerInfo());
556 ByValArgs.push_back(FIPtr);
559 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
561 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
562 SmallVector<SDValue, 8> MemOpChains;
564 const unsigned StackOffset = 92;
565 bool hasStructRetAttr = false;
566 // Walk the register/memloc assignments, inserting copies/loads.
567 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
570 CCValAssign &VA = ArgLocs[i];
571 SDValue Arg = OutVals[realArgIdx];
573 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
575 //Use local copy if it is a byval arg.
577 Arg = ByValArgs[byvalArgIdx++];
579 // Promote the value if needed.
580 switch (VA.getLocInfo()) {
581 default: llvm_unreachable("Unknown loc info!");
582 case CCValAssign::Full: break;
583 case CCValAssign::SExt:
584 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
586 case CCValAssign::ZExt:
587 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
589 case CCValAssign::AExt:
590 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
592 case CCValAssign::BCvt:
593 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
597 if (Flags.isSRet()) {
598 assert(VA.needsCustom());
599 // store SRet argument in %sp+64
600 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
601 SDValue PtrOff = DAG.getIntPtrConstant(64);
602 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
603 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
604 MachinePointerInfo(),
606 hasStructRetAttr = true;
610 if (VA.needsCustom()) {
611 assert(VA.getLocVT() == MVT::f64);
614 unsigned Offset = VA.getLocMemOffset() + StackOffset;
615 //if it is double-word aligned, just store.
616 if (Offset % 8 == 0) {
617 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
618 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
619 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
620 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
621 MachinePointerInfo(),
627 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
628 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
629 Arg, StackPtr, MachinePointerInfo(),
631 // Sparc is big-endian, so the high part comes first.
632 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
633 MachinePointerInfo(), false, false, false, 0);
634 // Increment the pointer to the other half.
635 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
636 DAG.getIntPtrConstant(4));
637 // Load the low part.
638 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
639 MachinePointerInfo(), false, false, false, 0);
642 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
644 CCValAssign &NextVA = ArgLocs[++i];
645 if (NextVA.isRegLoc()) {
646 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
648 //Store the low part in stack.
649 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
650 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
651 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
652 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
653 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
654 MachinePointerInfo(),
658 unsigned Offset = VA.getLocMemOffset() + StackOffset;
659 // Store the high part.
660 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
661 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
662 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
663 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
664 MachinePointerInfo(),
666 // Store the low part.
667 PtrOff = DAG.getIntPtrConstant(Offset+4);
668 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
669 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
670 MachinePointerInfo(),
676 // Arguments that can be passed on register must be kept at
679 if (VA.getLocVT() != MVT::f32) {
680 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
683 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
684 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
688 assert(VA.isMemLoc());
690 // Create a store off the stack pointer for this argument.
691 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
692 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
693 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
694 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
695 MachinePointerInfo(),
700 // Emit all stores, make sure the occur before any copies into physregs.
701 if (!MemOpChains.empty())
702 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
703 &MemOpChains[0], MemOpChains.size());
705 // Build a sequence of copy-to-reg nodes chained together with token
706 // chain and flag operands which copy the outgoing args into registers.
707 // The InFlag in necessary since all emitted instructions must be
710 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
711 unsigned Reg = RegsToPass[i].first;
712 // Remap I0->I7 -> O0->O7.
713 if (Reg >= SP::I0 && Reg <= SP::I7)
714 Reg = Reg-SP::I0+SP::O0;
716 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
717 InFlag = Chain.getValue(1);
720 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
722 // If the callee is a GlobalAddress node (quite common, every direct call is)
723 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
724 // Likewise ExternalSymbol -> TargetExternalSymbol.
725 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
726 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
727 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
728 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
730 // Returns a chain & a flag for retval copy to use
731 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
732 SmallVector<SDValue, 8> Ops;
733 Ops.push_back(Chain);
734 Ops.push_back(Callee);
735 if (hasStructRetAttr)
736 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
738 unsigned Reg = RegsToPass[i].first;
739 if (Reg >= SP::I0 && Reg <= SP::I7)
740 Reg = Reg-SP::I0+SP::O0;
742 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
744 if (InFlag.getNode())
745 Ops.push_back(InFlag);
747 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
748 InFlag = Chain.getValue(1);
750 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
751 DAG.getIntPtrConstant(0, true), InFlag);
752 InFlag = Chain.getValue(1);
754 // Assign locations to each value returned by this call.
755 SmallVector<CCValAssign, 16> RVLocs;
756 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
757 DAG.getTarget(), RVLocs, *DAG.getContext());
759 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
761 // Copy all of the result registers out of their specified physreg.
762 for (unsigned i = 0; i != RVLocs.size(); ++i) {
763 unsigned Reg = RVLocs[i].getLocReg();
765 // Remap I0->I7 -> O0->O7.
766 if (Reg >= SP::I0 && Reg <= SP::I7)
767 Reg = Reg-SP::I0+SP::O0;
769 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
770 RVLocs[i].getValVT(), InFlag).getValue(1);
771 InFlag = Chain.getValue(2);
772 InVals.push_back(Chain.getValue(0));
779 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
781 const Function *CalleeFn = 0;
782 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
783 CalleeFn = dyn_cast<Function>(G->getGlobal());
784 } else if (ExternalSymbolSDNode *E =
785 dyn_cast<ExternalSymbolSDNode>(Callee)) {
786 const Function *Fn = DAG.getMachineFunction().getFunction();
787 const Module *M = Fn->getParent();
788 CalleeFn = M->getFunction(E->getSymbol());
794 assert(CalleeFn->hasStructRetAttr() &&
795 "Callee does not have the StructRet attribute.");
797 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
798 Type *ElementTy = Ty->getElementType();
799 return getDataLayout()->getTypeAllocSize(ElementTy);
802 //===----------------------------------------------------------------------===//
803 // TargetLowering Implementation
804 //===----------------------------------------------------------------------===//
806 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
808 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
810 default: llvm_unreachable("Unknown integer condition code!");
811 case ISD::SETEQ: return SPCC::ICC_E;
812 case ISD::SETNE: return SPCC::ICC_NE;
813 case ISD::SETLT: return SPCC::ICC_L;
814 case ISD::SETGT: return SPCC::ICC_G;
815 case ISD::SETLE: return SPCC::ICC_LE;
816 case ISD::SETGE: return SPCC::ICC_GE;
817 case ISD::SETULT: return SPCC::ICC_CS;
818 case ISD::SETULE: return SPCC::ICC_LEU;
819 case ISD::SETUGT: return SPCC::ICC_GU;
820 case ISD::SETUGE: return SPCC::ICC_CC;
824 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
826 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
828 default: llvm_unreachable("Unknown fp condition code!");
830 case ISD::SETOEQ: return SPCC::FCC_E;
832 case ISD::SETUNE: return SPCC::FCC_NE;
834 case ISD::SETOLT: return SPCC::FCC_L;
836 case ISD::SETOGT: return SPCC::FCC_G;
838 case ISD::SETOLE: return SPCC::FCC_LE;
840 case ISD::SETOGE: return SPCC::FCC_GE;
841 case ISD::SETULT: return SPCC::FCC_UL;
842 case ISD::SETULE: return SPCC::FCC_ULE;
843 case ISD::SETUGT: return SPCC::FCC_UG;
844 case ISD::SETUGE: return SPCC::FCC_UGE;
845 case ISD::SETUO: return SPCC::FCC_U;
846 case ISD::SETO: return SPCC::FCC_O;
847 case ISD::SETONE: return SPCC::FCC_LG;
848 case ISD::SETUEQ: return SPCC::FCC_UE;
852 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
853 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
854 Subtarget = &TM.getSubtarget<SparcSubtarget>();
856 // Set up the register classes.
857 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
858 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
859 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
860 if (Subtarget->is64Bit())
861 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
863 // Turn FP extload into load/fextend
864 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
865 // Sparc doesn't have i1 sign extending load
866 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
867 // Turn FP truncstore into trunc + store.
868 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
870 // Custom legalize GlobalAddress nodes into LO/HI parts.
871 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
872 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
873 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
875 // Sparc doesn't have sext_inreg, replace them with shl/sra
876 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
877 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
878 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
880 // Sparc has no REM or DIVREM operations.
881 setOperationAction(ISD::UREM, MVT::i32, Expand);
882 setOperationAction(ISD::SREM, MVT::i32, Expand);
883 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
884 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
886 // Custom expand fp<->sint
887 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
888 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
891 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
892 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
894 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
895 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
897 // Sparc has no select or setcc: expand to SELECT_CC.
898 setOperationAction(ISD::SELECT, MVT::i32, Expand);
899 setOperationAction(ISD::SELECT, MVT::f32, Expand);
900 setOperationAction(ISD::SELECT, MVT::f64, Expand);
901 setOperationAction(ISD::SETCC, MVT::i32, Expand);
902 setOperationAction(ISD::SETCC, MVT::f32, Expand);
903 setOperationAction(ISD::SETCC, MVT::f64, Expand);
905 // Sparc doesn't have BRCOND either, it has BR_CC.
906 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
907 setOperationAction(ISD::BRIND, MVT::Other, Expand);
908 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
909 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
910 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
911 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
913 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
914 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
915 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
917 if (Subtarget->is64Bit()) {
918 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
919 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
922 // FIXME: There are instructions available for ATOMIC_FENCE
923 // on SparcV8 and later.
924 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
925 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
927 setOperationAction(ISD::FSIN , MVT::f64, Expand);
928 setOperationAction(ISD::FCOS , MVT::f64, Expand);
929 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
930 setOperationAction(ISD::FREM , MVT::f64, Expand);
931 setOperationAction(ISD::FMA , MVT::f64, Expand);
932 setOperationAction(ISD::FSIN , MVT::f32, Expand);
933 setOperationAction(ISD::FCOS , MVT::f32, Expand);
934 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
935 setOperationAction(ISD::FREM , MVT::f32, Expand);
936 setOperationAction(ISD::FMA , MVT::f32, Expand);
937 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
938 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
939 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
940 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
941 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
942 setOperationAction(ISD::ROTL , MVT::i32, Expand);
943 setOperationAction(ISD::ROTR , MVT::i32, Expand);
944 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
945 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
946 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
947 setOperationAction(ISD::FPOW , MVT::f64, Expand);
948 setOperationAction(ISD::FPOW , MVT::f32, Expand);
950 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
951 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
952 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
954 // FIXME: Sparc provides these multiplies, but we don't have them yet.
955 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
956 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
958 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
960 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
961 setOperationAction(ISD::VASTART , MVT::Other, Custom);
962 // VAARG needs to be lowered to not do unaligned accesses for doubles.
963 setOperationAction(ISD::VAARG , MVT::Other, Custom);
965 // Use the default implementation.
966 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
967 setOperationAction(ISD::VAEND , MVT::Other, Expand);
968 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
969 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
970 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
972 // No debug info support yet.
973 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
975 setStackPointerRegisterToSaveRestore(SP::O6);
977 if (TM.getSubtarget<SparcSubtarget>().isV9())
978 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
980 setMinFunctionAlignment(2);
982 computeRegisterProperties();
985 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
988 case SPISD::CMPICC: return "SPISD::CMPICC";
989 case SPISD::CMPFCC: return "SPISD::CMPFCC";
990 case SPISD::BRICC: return "SPISD::BRICC";
991 case SPISD::BRXCC: return "SPISD::BRXCC";
992 case SPISD::BRFCC: return "SPISD::BRFCC";
993 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
994 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
995 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
996 case SPISD::Hi: return "SPISD::Hi";
997 case SPISD::Lo: return "SPISD::Lo";
998 case SPISD::FTOI: return "SPISD::FTOI";
999 case SPISD::ITOF: return "SPISD::ITOF";
1000 case SPISD::CALL: return "SPISD::CALL";
1001 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1002 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1003 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1007 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1008 /// be zero. Op is expected to be a target specific node. Used by DAG
1010 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1013 const SelectionDAG &DAG,
1014 unsigned Depth) const {
1015 APInt KnownZero2, KnownOne2;
1016 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1018 switch (Op.getOpcode()) {
1020 case SPISD::SELECT_ICC:
1021 case SPISD::SELECT_XCC:
1022 case SPISD::SELECT_FCC:
1023 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1024 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1025 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1026 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1028 // Only known if known in both the LHS and RHS.
1029 KnownOne &= KnownOne2;
1030 KnownZero &= KnownZero2;
1035 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1036 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1037 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1038 ISD::CondCode CC, unsigned &SPCC) {
1039 if (isa<ConstantSDNode>(RHS) &&
1040 cast<ConstantSDNode>(RHS)->isNullValue() &&
1042 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1043 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1044 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1045 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1046 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1047 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1048 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1049 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1050 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1051 SDValue CMPCC = LHS.getOperand(3);
1052 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1053 LHS = CMPCC.getOperand(0);
1054 RHS = CMPCC.getOperand(1);
1058 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1059 SelectionDAG &DAG) const {
1060 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1061 // FIXME there isn't really any debug info here
1062 DebugLoc dl = Op.getDebugLoc();
1063 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
1064 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
1065 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
1067 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1068 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
1070 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
1072 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
1073 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
1074 GlobalBase, RelAddr);
1075 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1076 AbsAddr, MachinePointerInfo(), false, false, false, 0);
1079 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1080 SelectionDAG &DAG) const {
1081 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1082 // FIXME there isn't really any debug info here
1083 DebugLoc dl = Op.getDebugLoc();
1084 const Constant *C = N->getConstVal();
1085 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
1086 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
1087 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
1088 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1089 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
1091 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
1093 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
1094 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
1095 GlobalBase, RelAddr);
1096 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1097 AbsAddr, MachinePointerInfo(), false, false, false, 0);
1100 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1101 DebugLoc dl = Op.getDebugLoc();
1102 // Convert the fp value to integer in an FP register.
1103 assert(Op.getValueType() == MVT::i32);
1104 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
1105 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
1108 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1109 DebugLoc dl = Op.getDebugLoc();
1110 assert(Op.getOperand(0).getValueType() == MVT::i32);
1111 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
1112 // Convert the int value to FP in an FP register.
1113 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
1116 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1117 SDValue Chain = Op.getOperand(0);
1118 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1119 SDValue LHS = Op.getOperand(2);
1120 SDValue RHS = Op.getOperand(3);
1121 SDValue Dest = Op.getOperand(4);
1122 DebugLoc dl = Op.getDebugLoc();
1123 unsigned Opc, SPCC = ~0U;
1125 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1126 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1127 LookThroughSetCC(LHS, RHS, CC, SPCC);
1129 // Get the condition flag.
1130 SDValue CompareFlag;
1131 if (LHS.getValueType().isInteger()) {
1132 EVT VTs[] = { LHS.getValueType(), MVT::Glue };
1133 SDValue Ops[2] = { LHS, RHS };
1134 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
1135 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1136 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
1137 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
1139 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1140 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1143 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
1144 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1147 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1148 SDValue LHS = Op.getOperand(0);
1149 SDValue RHS = Op.getOperand(1);
1150 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1151 SDValue TrueVal = Op.getOperand(2);
1152 SDValue FalseVal = Op.getOperand(3);
1153 DebugLoc dl = Op.getDebugLoc();
1154 unsigned Opc, SPCC = ~0U;
1156 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1157 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1158 LookThroughSetCC(LHS, RHS, CC, SPCC);
1160 SDValue CompareFlag;
1161 if (LHS.getValueType().isInteger()) {
1162 // subcc returns a value
1163 EVT VTs[] = { LHS.getValueType(), MVT::Glue };
1164 SDValue Ops[2] = { LHS, RHS };
1165 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
1166 Opc = LHS.getValueType() == MVT::i32 ?
1167 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
1168 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1170 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1171 Opc = SPISD::SELECT_FCC;
1172 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1174 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
1175 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1178 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1179 const SparcTargetLowering &TLI) {
1180 MachineFunction &MF = DAG.getMachineFunction();
1181 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1183 // vastart just stores the address of the VarArgsFrameIndex slot into the
1184 // memory location argument.
1185 DebugLoc dl = Op.getDebugLoc();
1187 DAG.getNode(ISD::ADD, dl, MVT::i32,
1188 DAG.getRegister(SP::I6, MVT::i32),
1189 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
1191 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1192 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
1193 MachinePointerInfo(SV), false, false, 0);
1196 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
1197 SDNode *Node = Op.getNode();
1198 EVT VT = Node->getValueType(0);
1199 SDValue InChain = Node->getOperand(0);
1200 SDValue VAListPtr = Node->getOperand(1);
1201 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1202 DebugLoc dl = Node->getDebugLoc();
1203 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
1204 MachinePointerInfo(SV), false, false, false, 0);
1205 // Increment the pointer, VAList, to the next vaarg
1206 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
1207 DAG.getConstant(VT.getSizeInBits()/8,
1209 // Store the incremented VAList to the legalized pointer
1210 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
1211 VAListPtr, MachinePointerInfo(SV), false, false, 0);
1212 // Load the actual argument out of the pointer VAList, unless this is an
1215 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
1216 false, false, false, 0);
1218 // Otherwise, load it as i64, then do a bitconvert.
1219 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
1220 false, false, false, 0);
1222 // Bit-Convert the value to f64.
1224 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
1227 return DAG.getMergeValues(Ops, 2, dl);
1230 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1231 SDValue Chain = Op.getOperand(0); // Legalize the chain.
1232 SDValue Size = Op.getOperand(1); // Legalize the size.
1233 DebugLoc dl = Op.getDebugLoc();
1235 unsigned SPReg = SP::O6;
1236 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
1237 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
1238 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
1240 // The resultant pointer is actually 16 words from the bottom of the stack,
1241 // to provide a register spill area.
1242 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
1243 DAG.getConstant(96, MVT::i32));
1244 SDValue Ops[2] = { NewVal, Chain };
1245 return DAG.getMergeValues(Ops, 2, dl);
1249 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
1250 DebugLoc dl = Op.getDebugLoc();
1251 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
1252 dl, MVT::Other, DAG.getEntryNode());
1256 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1257 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1258 MFI->setFrameAddressIsTaken(true);
1260 EVT VT = Op.getValueType();
1261 DebugLoc dl = Op.getDebugLoc();
1262 unsigned FrameReg = SP::I6;
1264 uint64_t depth = Op.getConstantOperandVal(0);
1268 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1270 // flush first to make sure the windowed registers' values are in stack
1271 SDValue Chain = getFLUSHW(Op, DAG);
1272 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
1274 for (uint64_t i = 0; i != depth; ++i) {
1275 SDValue Ptr = DAG.getNode(ISD::ADD,
1277 FrameAddr, DAG.getIntPtrConstant(56));
1278 FrameAddr = DAG.getLoad(MVT::i32, dl,
1281 MachinePointerInfo(), false, false, false, 0);
1287 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
1288 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1289 MFI->setReturnAddressIsTaken(true);
1291 EVT VT = Op.getValueType();
1292 DebugLoc dl = Op.getDebugLoc();
1293 unsigned RetReg = SP::I7;
1295 uint64_t depth = Op.getConstantOperandVal(0);
1299 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
1301 // flush first to make sure the windowed registers' values are in stack
1302 SDValue Chain = getFLUSHW(Op, DAG);
1303 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
1305 for (uint64_t i = 0; i != depth; ++i) {
1306 SDValue Ptr = DAG.getNode(ISD::ADD,
1309 DAG.getIntPtrConstant((i == depth-1)?60:56));
1310 RetAddr = DAG.getLoad(MVT::i32, dl,
1313 MachinePointerInfo(), false, false, false, 0);
1319 SDValue SparcTargetLowering::
1320 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1321 switch (Op.getOpcode()) {
1322 default: llvm_unreachable("Should not custom lower this!");
1323 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1324 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1325 case ISD::GlobalTLSAddress:
1326 llvm_unreachable("TLS not implemented for Sparc.");
1327 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1328 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1329 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1330 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1331 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1332 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1333 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
1334 case ISD::VAARG: return LowerVAARG(Op, DAG);
1335 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1340 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1341 MachineBasicBlock *BB) const {
1342 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1345 DebugLoc dl = MI->getDebugLoc();
1346 // Figure out the conditional branch opcode to use for this select_cc.
1347 switch (MI->getOpcode()) {
1348 default: llvm_unreachable("Unknown SELECT_CC!");
1349 case SP::SELECT_CC_Int_ICC:
1350 case SP::SELECT_CC_FP_ICC:
1351 case SP::SELECT_CC_DFP_ICC:
1352 BROpcode = SP::BCOND;
1354 case SP::SELECT_CC_Int_FCC:
1355 case SP::SELECT_CC_FP_FCC:
1356 case SP::SELECT_CC_DFP_FCC:
1357 BROpcode = SP::FBCOND;
1361 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
1363 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1364 // control-flow pattern. The incoming instruction knows the destination vreg
1365 // to set, the condition code register to branch on, the true/false values to
1366 // select between, and a branch opcode to use.
1367 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1368 MachineFunction::iterator It = BB;
1375 // fallthrough --> copy0MBB
1376 MachineBasicBlock *thisMBB = BB;
1377 MachineFunction *F = BB->getParent();
1378 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1379 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1380 F->insert(It, copy0MBB);
1381 F->insert(It, sinkMBB);
1383 // Transfer the remainder of BB and its successor edges to sinkMBB.
1384 sinkMBB->splice(sinkMBB->begin(), BB,
1385 llvm::next(MachineBasicBlock::iterator(MI)),
1387 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1389 // Add the true and fallthrough blocks as its successors.
1390 BB->addSuccessor(copy0MBB);
1391 BB->addSuccessor(sinkMBB);
1393 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1396 // %FalseValue = ...
1397 // # fallthrough to sinkMBB
1400 // Update machine-CFG edges
1401 BB->addSuccessor(sinkMBB);
1404 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1407 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1408 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1409 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1411 MI->eraseFromParent(); // The pseudo instruction is gone now.
1415 //===----------------------------------------------------------------------===//
1416 // Sparc Inline Assembly Support
1417 //===----------------------------------------------------------------------===//
1419 /// getConstraintType - Given a constraint letter, return the type of
1420 /// constraint it is for this target.
1421 SparcTargetLowering::ConstraintType
1422 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1423 if (Constraint.size() == 1) {
1424 switch (Constraint[0]) {
1426 case 'r': return C_RegisterClass;
1430 return TargetLowering::getConstraintType(Constraint);
1433 std::pair<unsigned, const TargetRegisterClass*>
1434 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1436 if (Constraint.size() == 1) {
1437 switch (Constraint[0]) {
1439 return std::make_pair(0U, &SP::IntRegsRegClass);
1443 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1447 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1448 // The Sparc target isn't yet aware of offsets.