1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcTargetMachine.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Module.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/Support/ErrorHandling.h"
32 //===----------------------------------------------------------------------===//
33 // Calling Convention Implementation
34 //===----------------------------------------------------------------------===//
36 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
37 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
38 ISD::ArgFlagsTy &ArgFlags, CCState &State)
40 assert (ArgFlags.isSRet());
42 //Assign SRet argument
43 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
49 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
50 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags, CCState &State)
53 static const unsigned RegList[] = {
54 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
56 //Try to get first reg
57 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
58 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
60 //Assign whole thing in stack
61 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
62 State.AllocateStack(8,4),
67 //Try to get second reg
68 if (unsigned Reg = State.AllocateReg(RegList, 6))
69 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
71 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
72 State.AllocateStack(4,4),
77 #include "SparcGenCallingConv.inc"
80 SparcTargetLowering::LowerReturn(SDValue Chain,
81 CallingConv::ID CallConv, bool isVarArg,
82 const SmallVectorImpl<ISD::OutputArg> &Outs,
83 const SmallVectorImpl<SDValue> &OutVals,
84 DebugLoc dl, SelectionDAG &DAG) const {
86 MachineFunction &MF = DAG.getMachineFunction();
88 // CCValAssign - represent the assignment of the return value to locations.
89 SmallVector<CCValAssign, 16> RVLocs;
91 // CCState - Info about the registers and stack slot.
92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
93 DAG.getTarget(), RVLocs, *DAG.getContext());
95 // Analize return values.
96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
98 // If this is the first return lowered for this function, add the regs to the
99 // liveout set for the function.
100 if (MF.getRegInfo().liveout_empty()) {
101 for (unsigned i = 0; i != RVLocs.size(); ++i)
102 if (RVLocs[i].isRegLoc())
103 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
108 // Copy the result values into the output registers.
109 for (unsigned i = 0; i != RVLocs.size(); ++i) {
110 CCValAssign &VA = RVLocs[i];
111 assert(VA.isRegLoc() && "Can only return in registers!");
113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
116 // Guarantee that all emitted copies are stuck together with flags.
117 Flag = Chain.getValue(1);
120 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot
121 // If the function returns a struct, copy the SRetReturnReg to I0
122 if (MF.getFunction()->hasStructRetAttr()) {
123 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
124 unsigned Reg = SFI->getSRetReturnReg();
126 llvm_unreachable("sret virtual register not created in the entry block");
127 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
128 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag);
129 Flag = Chain.getValue(1);
130 if (MF.getRegInfo().liveout_empty())
131 MF.getRegInfo().addLiveOut(SP::I0);
132 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
135 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32);
138 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
139 RetAddrOffsetNode, Flag);
140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
144 /// LowerFormalArguments - V8 uses a very simple ABI, where all values are
145 /// passed in either one or two GPRs, including FP values. TODO: we should
146 /// pass FP values in FP registers for fastcc functions.
148 SparcTargetLowering::LowerFormalArguments(SDValue Chain,
149 CallingConv::ID CallConv, bool isVarArg,
150 const SmallVectorImpl<ISD::InputArg>
152 DebugLoc dl, SelectionDAG &DAG,
153 SmallVectorImpl<SDValue> &InVals)
156 MachineFunction &MF = DAG.getMachineFunction();
157 MachineRegisterInfo &RegInfo = MF.getRegInfo();
158 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
160 // Assign locations to all of the incoming arguments.
161 SmallVector<CCValAssign, 16> ArgLocs;
162 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
163 getTargetMachine(), ArgLocs, *DAG.getContext());
164 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
166 const unsigned StackOffset = 92;
168 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
169 CCValAssign &VA = ArgLocs[i];
171 if (i == 0 && Ins[i].Flags.isSRet()) {
172 //Get SRet from [%fp+64]
173 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
175 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
176 MachinePointerInfo(),
177 false, false, false, 0);
178 InVals.push_back(Arg);
183 if (VA.needsCustom()) {
184 assert(VA.getLocVT() == MVT::f64);
185 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
186 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
187 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
190 CCValAssign &NextVA = ArgLocs[++i];
193 if (NextVA.isMemLoc()) {
194 int FrameIdx = MF.getFrameInfo()->
195 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
196 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
197 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
198 MachinePointerInfo(),
199 false, false, false, 0);
201 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
202 &SP::IntRegsRegClass);
203 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
206 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
207 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
208 InVals.push_back(WholeValue);
211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
213 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
214 if (VA.getLocVT() == MVT::f32)
215 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
216 else if (VA.getLocVT() != MVT::i32) {
217 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
218 DAG.getValueType(VA.getLocVT()));
219 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
221 InVals.push_back(Arg);
225 assert(VA.isMemLoc());
227 unsigned Offset = VA.getLocMemOffset()+StackOffset;
229 if (VA.needsCustom()) {
230 assert(VA.getValVT() == MVT::f64);
231 //If it is double-word aligned, just load.
232 if (Offset % 8 == 0) {
233 int FI = MF.getFrameInfo()->CreateFixedObject(8,
236 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
237 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
238 MachinePointerInfo(),
239 false,false, false, 0);
240 InVals.push_back(Load);
244 int FI = MF.getFrameInfo()->CreateFixedObject(4,
247 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
248 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
249 MachinePointerInfo(),
250 false, false, false, 0);
251 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
254 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
256 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
257 MachinePointerInfo(),
258 false, false, false, 0);
261 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
262 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
263 InVals.push_back(WholeValue);
267 int FI = MF.getFrameInfo()->CreateFixedObject(4,
270 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
272 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
273 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
274 MachinePointerInfo(),
275 false, false, false, 0);
277 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
278 // Sparc is big endian, so add an offset based on the ObjectVT.
279 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
280 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
281 DAG.getConstant(Offset, MVT::i32));
282 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
283 MachinePointerInfo(),
284 VA.getValVT(), false, false,0);
285 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
287 InVals.push_back(Load);
290 if (MF.getFunction()->hasStructRetAttr()) {
291 //Copy the SRet Argument to SRetReturnReg
292 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
293 unsigned Reg = SFI->getSRetReturnReg();
295 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
296 SFI->setSRetReturnReg(Reg);
298 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
299 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
302 // Store remaining ArgRegs to the stack if this is a varargs function.
304 static const unsigned ArgRegs[] = {
305 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
307 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
308 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
309 unsigned ArgOffset = CCInfo.getNextStackOffset();
310 if (NumAllocated == 6)
311 ArgOffset += StackOffset;
314 ArgOffset = 68+4*NumAllocated;
317 // Remember the vararg offset for the va_start implementation.
318 FuncInfo->setVarArgsFrameOffset(ArgOffset);
320 std::vector<SDValue> OutChains;
322 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
325 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
327 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
329 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
331 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
332 MachinePointerInfo(),
337 if (!OutChains.empty()) {
338 OutChains.push_back(Chain);
339 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
340 &OutChains[0], OutChains.size());
348 SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
349 CallingConv::ID CallConv, bool isVarArg,
350 bool doesNotRet, bool &isTailCall,
351 const SmallVectorImpl<ISD::OutputArg> &Outs,
352 const SmallVectorImpl<SDValue> &OutVals,
353 const SmallVectorImpl<ISD::InputArg> &Ins,
354 DebugLoc dl, SelectionDAG &DAG,
355 SmallVectorImpl<SDValue> &InVals) const {
356 // Sparc target does not yet support tail call optimization.
359 // Analyze operands of the call, assigning locations to each operand.
360 SmallVector<CCValAssign, 16> ArgLocs;
361 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
362 DAG.getTarget(), ArgLocs, *DAG.getContext());
363 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
365 // Get the size of the outgoing arguments stack space requirement.
366 unsigned ArgsSize = CCInfo.getNextStackOffset();
368 // Keep stack frames 8-byte aligned.
369 ArgsSize = (ArgsSize+7) & ~7;
371 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
373 //Create local copies for byval args.
374 SmallVector<SDValue, 8> ByValArgs;
375 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
376 ISD::ArgFlagsTy Flags = Outs[i].Flags;
377 if (!Flags.isByVal())
380 SDValue Arg = OutVals[i];
381 unsigned Size = Flags.getByValSize();
382 unsigned Align = Flags.getByValAlign();
384 int FI = MFI->CreateStackObject(Size, Align, false);
385 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
386 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
388 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
390 (Size <= 32), //AlwaysInline if size <= 32
391 MachinePointerInfo(), MachinePointerInfo());
392 ByValArgs.push_back(FIPtr);
395 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
397 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
398 SmallVector<SDValue, 8> MemOpChains;
400 const unsigned StackOffset = 92;
401 bool hasStructRetAttr = false;
402 // Walk the register/memloc assignments, inserting copies/loads.
403 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
406 CCValAssign &VA = ArgLocs[i];
407 SDValue Arg = OutVals[realArgIdx];
409 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
411 //Use local copy if it is a byval arg.
413 Arg = ByValArgs[byvalArgIdx++];
415 // Promote the value if needed.
416 switch (VA.getLocInfo()) {
417 default: llvm_unreachable("Unknown loc info!");
418 case CCValAssign::Full: break;
419 case CCValAssign::SExt:
420 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
422 case CCValAssign::ZExt:
423 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
425 case CCValAssign::AExt:
426 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
428 case CCValAssign::BCvt:
429 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
433 if (Flags.isSRet()) {
434 assert(VA.needsCustom());
435 // store SRet argument in %sp+64
436 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
437 SDValue PtrOff = DAG.getIntPtrConstant(64);
438 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
439 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
440 MachinePointerInfo(),
442 hasStructRetAttr = true;
446 if (VA.needsCustom()) {
447 assert(VA.getLocVT() == MVT::f64);
450 unsigned Offset = VA.getLocMemOffset() + StackOffset;
451 //if it is double-word aligned, just store.
452 if (Offset % 8 == 0) {
453 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
454 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
455 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
456 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
457 MachinePointerInfo(),
463 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
464 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
465 Arg, StackPtr, MachinePointerInfo(),
467 // Sparc is big-endian, so the high part comes first.
468 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
469 MachinePointerInfo(), false, false, false, 0);
470 // Increment the pointer to the other half.
471 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
472 DAG.getIntPtrConstant(4));
473 // Load the low part.
474 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
475 MachinePointerInfo(), false, false, false, 0);
478 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
480 CCValAssign &NextVA = ArgLocs[++i];
481 if (NextVA.isRegLoc()) {
482 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
484 //Store the low part in stack.
485 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
486 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
487 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
488 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
489 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
490 MachinePointerInfo(),
494 unsigned Offset = VA.getLocMemOffset() + StackOffset;
495 // Store the high part.
496 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
497 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
498 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
499 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
500 MachinePointerInfo(),
502 // Store the low part.
503 PtrOff = DAG.getIntPtrConstant(Offset+4);
504 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
505 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
506 MachinePointerInfo(),
512 // Arguments that can be passed on register must be kept at
515 if (VA.getLocVT() != MVT::f32) {
516 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
519 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
520 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
524 assert(VA.isMemLoc());
526 // Create a store off the stack pointer for this argument.
527 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
528 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
529 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
530 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
531 MachinePointerInfo(),
536 // Emit all stores, make sure the occur before any copies into physregs.
537 if (!MemOpChains.empty())
538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
539 &MemOpChains[0], MemOpChains.size());
541 // Build a sequence of copy-to-reg nodes chained together with token
542 // chain and flag operands which copy the outgoing args into registers.
543 // The InFlag in necessary since all emitted instructions must be
546 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
547 unsigned Reg = RegsToPass[i].first;
548 // Remap I0->I7 -> O0->O7.
549 if (Reg >= SP::I0 && Reg <= SP::I7)
550 Reg = Reg-SP::I0+SP::O0;
552 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
553 InFlag = Chain.getValue(1);
556 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
558 // If the callee is a GlobalAddress node (quite common, every direct call is)
559 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
560 // Likewise ExternalSymbol -> TargetExternalSymbol.
561 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
562 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
563 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
564 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
566 // Returns a chain & a flag for retval copy to use
567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
568 SmallVector<SDValue, 8> Ops;
569 Ops.push_back(Chain);
570 Ops.push_back(Callee);
571 if (hasStructRetAttr)
572 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
573 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
574 unsigned Reg = RegsToPass[i].first;
575 if (Reg >= SP::I0 && Reg <= SP::I7)
576 Reg = Reg-SP::I0+SP::O0;
578 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
580 if (InFlag.getNode())
581 Ops.push_back(InFlag);
583 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
584 InFlag = Chain.getValue(1);
586 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
587 DAG.getIntPtrConstant(0, true), InFlag);
588 InFlag = Chain.getValue(1);
590 // Assign locations to each value returned by this call.
591 SmallVector<CCValAssign, 16> RVLocs;
592 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
593 DAG.getTarget(), RVLocs, *DAG.getContext());
595 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
597 // Copy all of the result registers out of their specified physreg.
598 for (unsigned i = 0; i != RVLocs.size(); ++i) {
599 unsigned Reg = RVLocs[i].getLocReg();
601 // Remap I0->I7 -> O0->O7.
602 if (Reg >= SP::I0 && Reg <= SP::I7)
603 Reg = Reg-SP::I0+SP::O0;
605 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
606 RVLocs[i].getValVT(), InFlag).getValue(1);
607 InFlag = Chain.getValue(2);
608 InVals.push_back(Chain.getValue(0));
615 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
617 const Function *CalleeFn = 0;
618 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
619 CalleeFn = dyn_cast<Function>(G->getGlobal());
620 } else if (ExternalSymbolSDNode *E =
621 dyn_cast<ExternalSymbolSDNode>(Callee)) {
622 const Function *Fn = DAG.getMachineFunction().getFunction();
623 const Module *M = Fn->getParent();
624 CalleeFn = M->getFunction(E->getSymbol());
630 assert(CalleeFn->hasStructRetAttr() &&
631 "Callee does not have the StructRet attribute.");
633 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
634 Type *ElementTy = Ty->getElementType();
635 return getTargetData()->getTypeAllocSize(ElementTy);
638 //===----------------------------------------------------------------------===//
639 // TargetLowering Implementation
640 //===----------------------------------------------------------------------===//
642 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
644 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
646 default: llvm_unreachable("Unknown integer condition code!");
647 case ISD::SETEQ: return SPCC::ICC_E;
648 case ISD::SETNE: return SPCC::ICC_NE;
649 case ISD::SETLT: return SPCC::ICC_L;
650 case ISD::SETGT: return SPCC::ICC_G;
651 case ISD::SETLE: return SPCC::ICC_LE;
652 case ISD::SETGE: return SPCC::ICC_GE;
653 case ISD::SETULT: return SPCC::ICC_CS;
654 case ISD::SETULE: return SPCC::ICC_LEU;
655 case ISD::SETUGT: return SPCC::ICC_GU;
656 case ISD::SETUGE: return SPCC::ICC_CC;
660 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
662 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
664 default: llvm_unreachable("Unknown fp condition code!");
666 case ISD::SETOEQ: return SPCC::FCC_E;
668 case ISD::SETUNE: return SPCC::FCC_NE;
670 case ISD::SETOLT: return SPCC::FCC_L;
672 case ISD::SETOGT: return SPCC::FCC_G;
674 case ISD::SETOLE: return SPCC::FCC_LE;
676 case ISD::SETOGE: return SPCC::FCC_GE;
677 case ISD::SETULT: return SPCC::FCC_UL;
678 case ISD::SETULE: return SPCC::FCC_ULE;
679 case ISD::SETUGT: return SPCC::FCC_UG;
680 case ISD::SETUGE: return SPCC::FCC_UGE;
681 case ISD::SETUO: return SPCC::FCC_U;
682 case ISD::SETO: return SPCC::FCC_O;
683 case ISD::SETONE: return SPCC::FCC_LG;
684 case ISD::SETUEQ: return SPCC::FCC_UE;
688 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
689 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
691 // Set up the register classes.
692 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
693 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
694 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
696 // Turn FP extload into load/fextend
697 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
698 // Sparc doesn't have i1 sign extending load
699 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
700 // Turn FP truncstore into trunc + store.
701 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
703 // Custom legalize GlobalAddress nodes into LO/HI parts.
704 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
705 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
706 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
708 // Sparc doesn't have sext_inreg, replace them with shl/sra
709 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
713 // Sparc has no REM or DIVREM operations.
714 setOperationAction(ISD::UREM, MVT::i32, Expand);
715 setOperationAction(ISD::SREM, MVT::i32, Expand);
716 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
717 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
719 // Custom expand fp<->sint
720 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
721 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
724 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
725 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
727 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
728 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
730 // Sparc has no select or setcc: expand to SELECT_CC.
731 setOperationAction(ISD::SELECT, MVT::i32, Expand);
732 setOperationAction(ISD::SELECT, MVT::f32, Expand);
733 setOperationAction(ISD::SELECT, MVT::f64, Expand);
734 setOperationAction(ISD::SETCC, MVT::i32, Expand);
735 setOperationAction(ISD::SETCC, MVT::f32, Expand);
736 setOperationAction(ISD::SETCC, MVT::f64, Expand);
738 // Sparc doesn't have BRCOND either, it has BR_CC.
739 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
740 setOperationAction(ISD::BRIND, MVT::Other, Expand);
741 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
742 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
743 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
744 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
746 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
747 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
748 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
750 // FIXME: There are instructions available for ATOMIC_FENCE
751 // on SparcV8 and later.
752 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
753 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
755 setOperationAction(ISD::FSIN , MVT::f64, Expand);
756 setOperationAction(ISD::FCOS , MVT::f64, Expand);
757 setOperationAction(ISD::FREM , MVT::f64, Expand);
758 setOperationAction(ISD::FMA , MVT::f64, Expand);
759 setOperationAction(ISD::FSIN , MVT::f32, Expand);
760 setOperationAction(ISD::FCOS , MVT::f32, Expand);
761 setOperationAction(ISD::FREM , MVT::f32, Expand);
762 setOperationAction(ISD::FMA , MVT::f32, Expand);
763 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
764 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
765 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
766 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
767 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
768 setOperationAction(ISD::ROTL , MVT::i32, Expand);
769 setOperationAction(ISD::ROTR , MVT::i32, Expand);
770 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
772 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
773 setOperationAction(ISD::FPOW , MVT::f64, Expand);
774 setOperationAction(ISD::FPOW , MVT::f32, Expand);
776 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
777 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
778 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
780 // FIXME: Sparc provides these multiplies, but we don't have them yet.
781 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
782 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
784 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
786 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
787 setOperationAction(ISD::VASTART , MVT::Other, Custom);
788 // VAARG needs to be lowered to not do unaligned accesses for doubles.
789 setOperationAction(ISD::VAARG , MVT::Other, Custom);
791 // Use the default implementation.
792 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
793 setOperationAction(ISD::VAEND , MVT::Other, Expand);
794 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
795 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
796 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
798 // No debug info support yet.
799 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
801 setStackPointerRegisterToSaveRestore(SP::O6);
803 if (TM.getSubtarget<SparcSubtarget>().isV9())
804 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
806 setMinFunctionAlignment(2);
808 computeRegisterProperties();
811 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
814 case SPISD::CMPICC: return "SPISD::CMPICC";
815 case SPISD::CMPFCC: return "SPISD::CMPFCC";
816 case SPISD::BRICC: return "SPISD::BRICC";
817 case SPISD::BRFCC: return "SPISD::BRFCC";
818 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
819 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
820 case SPISD::Hi: return "SPISD::Hi";
821 case SPISD::Lo: return "SPISD::Lo";
822 case SPISD::FTOI: return "SPISD::FTOI";
823 case SPISD::ITOF: return "SPISD::ITOF";
824 case SPISD::CALL: return "SPISD::CALL";
825 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
826 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
827 case SPISD::FLUSHW: return "SPISD::FLUSHW";
831 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
832 /// be zero. Op is expected to be a target specific node. Used by DAG
834 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
838 const SelectionDAG &DAG,
839 unsigned Depth) const {
840 APInt KnownZero2, KnownOne2;
841 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
843 switch (Op.getOpcode()) {
845 case SPISD::SELECT_ICC:
846 case SPISD::SELECT_FCC:
847 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
849 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
851 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
852 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
854 // Only known if known in both the LHS and RHS.
855 KnownOne &= KnownOne2;
856 KnownZero &= KnownZero2;
861 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
862 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
863 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
864 ISD::CondCode CC, unsigned &SPCC) {
865 if (isa<ConstantSDNode>(RHS) &&
866 cast<ConstantSDNode>(RHS)->isNullValue() &&
868 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
869 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
870 (LHS.getOpcode() == SPISD::SELECT_FCC &&
871 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
872 isa<ConstantSDNode>(LHS.getOperand(0)) &&
873 isa<ConstantSDNode>(LHS.getOperand(1)) &&
874 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
875 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
876 SDValue CMPCC = LHS.getOperand(3);
877 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
878 LHS = CMPCC.getOperand(0);
879 RHS = CMPCC.getOperand(1);
883 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
884 SelectionDAG &DAG) const {
885 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
886 // FIXME there isn't really any debug info here
887 DebugLoc dl = Op.getDebugLoc();
888 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
889 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
890 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
892 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
893 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
895 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
897 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
898 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
899 GlobalBase, RelAddr);
900 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
901 AbsAddr, MachinePointerInfo(), false, false, false, 0);
904 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
905 SelectionDAG &DAG) const {
906 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
907 // FIXME there isn't really any debug info here
908 DebugLoc dl = Op.getDebugLoc();
909 const Constant *C = N->getConstVal();
910 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
911 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
912 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
913 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
914 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
916 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
918 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
919 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
920 GlobalBase, RelAddr);
921 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
922 AbsAddr, MachinePointerInfo(), false, false, false, 0);
925 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
926 DebugLoc dl = Op.getDebugLoc();
927 // Convert the fp value to integer in an FP register.
928 assert(Op.getValueType() == MVT::i32);
929 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
930 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
933 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
934 DebugLoc dl = Op.getDebugLoc();
935 assert(Op.getOperand(0).getValueType() == MVT::i32);
936 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
937 // Convert the int value to FP in an FP register.
938 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
941 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
942 SDValue Chain = Op.getOperand(0);
943 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
944 SDValue LHS = Op.getOperand(2);
945 SDValue RHS = Op.getOperand(3);
946 SDValue Dest = Op.getOperand(4);
947 DebugLoc dl = Op.getDebugLoc();
948 unsigned Opc, SPCC = ~0U;
950 // If this is a br_cc of a "setcc", and if the setcc got lowered into
951 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
952 LookThroughSetCC(LHS, RHS, CC, SPCC);
954 // Get the condition flag.
956 if (LHS.getValueType() == MVT::i32) {
957 std::vector<EVT> VTs;
958 VTs.push_back(MVT::i32);
959 VTs.push_back(MVT::Glue);
960 SDValue Ops[2] = { LHS, RHS };
961 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
962 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
965 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
966 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
969 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
970 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
973 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
974 SDValue LHS = Op.getOperand(0);
975 SDValue RHS = Op.getOperand(1);
976 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
977 SDValue TrueVal = Op.getOperand(2);
978 SDValue FalseVal = Op.getOperand(3);
979 DebugLoc dl = Op.getDebugLoc();
980 unsigned Opc, SPCC = ~0U;
982 // If this is a select_cc of a "setcc", and if the setcc got lowered into
983 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
984 LookThroughSetCC(LHS, RHS, CC, SPCC);
987 if (LHS.getValueType() == MVT::i32) {
988 std::vector<EVT> VTs;
989 VTs.push_back(LHS.getValueType()); // subcc returns a value
990 VTs.push_back(MVT::Glue);
991 SDValue Ops[2] = { LHS, RHS };
992 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
993 Opc = SPISD::SELECT_ICC;
994 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
996 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
997 Opc = SPISD::SELECT_FCC;
998 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1000 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
1001 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1004 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1005 const SparcTargetLowering &TLI) {
1006 MachineFunction &MF = DAG.getMachineFunction();
1007 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1009 // vastart just stores the address of the VarArgsFrameIndex slot into the
1010 // memory location argument.
1011 DebugLoc dl = Op.getDebugLoc();
1013 DAG.getNode(ISD::ADD, dl, MVT::i32,
1014 DAG.getRegister(SP::I6, MVT::i32),
1015 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
1017 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1018 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
1019 MachinePointerInfo(SV), false, false, 0);
1022 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
1023 SDNode *Node = Op.getNode();
1024 EVT VT = Node->getValueType(0);
1025 SDValue InChain = Node->getOperand(0);
1026 SDValue VAListPtr = Node->getOperand(1);
1027 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1028 DebugLoc dl = Node->getDebugLoc();
1029 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
1030 MachinePointerInfo(SV), false, false, false, 0);
1031 // Increment the pointer, VAList, to the next vaarg
1032 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
1033 DAG.getConstant(VT.getSizeInBits()/8,
1035 // Store the incremented VAList to the legalized pointer
1036 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
1037 VAListPtr, MachinePointerInfo(SV), false, false, 0);
1038 // Load the actual argument out of the pointer VAList, unless this is an
1041 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
1042 false, false, false, 0);
1044 // Otherwise, load it as i64, then do a bitconvert.
1045 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
1046 false, false, false, 0);
1048 // Bit-Convert the value to f64.
1050 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
1053 return DAG.getMergeValues(Ops, 2, dl);
1056 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1057 SDValue Chain = Op.getOperand(0); // Legalize the chain.
1058 SDValue Size = Op.getOperand(1); // Legalize the size.
1059 DebugLoc dl = Op.getDebugLoc();
1061 unsigned SPReg = SP::O6;
1062 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
1063 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
1064 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
1066 // The resultant pointer is actually 16 words from the bottom of the stack,
1067 // to provide a register spill area.
1068 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
1069 DAG.getConstant(96, MVT::i32));
1070 SDValue Ops[2] = { NewVal, Chain };
1071 return DAG.getMergeValues(Ops, 2, dl);
1075 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
1076 DebugLoc dl = Op.getDebugLoc();
1077 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
1078 dl, MVT::Other, DAG.getEntryNode());
1082 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1083 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1084 MFI->setFrameAddressIsTaken(true);
1086 EVT VT = Op.getValueType();
1087 DebugLoc dl = Op.getDebugLoc();
1088 unsigned FrameReg = SP::I6;
1090 uint64_t depth = Op.getConstantOperandVal(0);
1094 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1096 // flush first to make sure the windowed registers' values are in stack
1097 SDValue Chain = getFLUSHW(Op, DAG);
1098 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
1100 for (uint64_t i = 0; i != depth; ++i) {
1101 SDValue Ptr = DAG.getNode(ISD::ADD,
1103 FrameAddr, DAG.getIntPtrConstant(56));
1104 FrameAddr = DAG.getLoad(MVT::i32, dl,
1107 MachinePointerInfo(), false, false, false, 0);
1113 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
1114 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1115 MFI->setReturnAddressIsTaken(true);
1117 EVT VT = Op.getValueType();
1118 DebugLoc dl = Op.getDebugLoc();
1119 unsigned RetReg = SP::I7;
1121 uint64_t depth = Op.getConstantOperandVal(0);
1125 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
1127 // flush first to make sure the windowed registers' values are in stack
1128 SDValue Chain = getFLUSHW(Op, DAG);
1129 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
1131 for (uint64_t i = 0; i != depth; ++i) {
1132 SDValue Ptr = DAG.getNode(ISD::ADD,
1135 DAG.getIntPtrConstant((i == depth-1)?60:56));
1136 RetAddr = DAG.getLoad(MVT::i32, dl,
1139 MachinePointerInfo(), false, false, false, 0);
1145 SDValue SparcTargetLowering::
1146 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1147 switch (Op.getOpcode()) {
1148 default: llvm_unreachable("Should not custom lower this!");
1149 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1150 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1151 case ISD::GlobalTLSAddress:
1152 llvm_unreachable("TLS not implemented for Sparc.");
1153 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1154 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1155 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1156 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1157 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1158 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1159 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
1160 case ISD::VAARG: return LowerVAARG(Op, DAG);
1161 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1166 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1167 MachineBasicBlock *BB) const {
1168 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1171 DebugLoc dl = MI->getDebugLoc();
1172 // Figure out the conditional branch opcode to use for this select_cc.
1173 switch (MI->getOpcode()) {
1174 default: llvm_unreachable("Unknown SELECT_CC!");
1175 case SP::SELECT_CC_Int_ICC:
1176 case SP::SELECT_CC_FP_ICC:
1177 case SP::SELECT_CC_DFP_ICC:
1178 BROpcode = SP::BCOND;
1180 case SP::SELECT_CC_Int_FCC:
1181 case SP::SELECT_CC_FP_FCC:
1182 case SP::SELECT_CC_DFP_FCC:
1183 BROpcode = SP::FBCOND;
1187 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
1189 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1190 // control-flow pattern. The incoming instruction knows the destination vreg
1191 // to set, the condition code register to branch on, the true/false values to
1192 // select between, and a branch opcode to use.
1193 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1194 MachineFunction::iterator It = BB;
1201 // fallthrough --> copy0MBB
1202 MachineBasicBlock *thisMBB = BB;
1203 MachineFunction *F = BB->getParent();
1204 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1205 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1206 F->insert(It, copy0MBB);
1207 F->insert(It, sinkMBB);
1209 // Transfer the remainder of BB and its successor edges to sinkMBB.
1210 sinkMBB->splice(sinkMBB->begin(), BB,
1211 llvm::next(MachineBasicBlock::iterator(MI)),
1213 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1215 // Add the true and fallthrough blocks as its successors.
1216 BB->addSuccessor(copy0MBB);
1217 BB->addSuccessor(sinkMBB);
1219 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1222 // %FalseValue = ...
1223 // # fallthrough to sinkMBB
1226 // Update machine-CFG edges
1227 BB->addSuccessor(sinkMBB);
1230 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1233 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1234 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1235 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1237 MI->eraseFromParent(); // The pseudo instruction is gone now.
1241 //===----------------------------------------------------------------------===//
1242 // Sparc Inline Assembly Support
1243 //===----------------------------------------------------------------------===//
1245 /// getConstraintType - Given a constraint letter, return the type of
1246 /// constraint it is for this target.
1247 SparcTargetLowering::ConstraintType
1248 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1249 if (Constraint.size() == 1) {
1250 switch (Constraint[0]) {
1252 case 'r': return C_RegisterClass;
1256 return TargetLowering::getConstraintType(Constraint);
1259 std::pair<unsigned, const TargetRegisterClass*>
1260 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1262 if (Constraint.size() == 1) {
1263 switch (Constraint[0]) {
1265 return std::make_pair(0U, SP::IntRegsRegisterClass);
1269 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1273 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1274 // The Sparc target isn't yet aware of offsets.