1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef SPARC_ISELLOWERING_H
16 #define SPARC_ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
24 FIRST_NUMBER = ISD::BUILTIN_OP_END,
25 CMPICC, // Compare two GPR operands, set icc.
26 CMPFCC, // Compare two FP operands, set fcc.
27 BRICC, // Branch to dest on icc condition
28 BRFCC, // Branch to dest on fcc condition
29 SELECT_ICC, // Select between two values using the current ICC flags.
30 SELECT_FCC, // Select between two values using the current FCC flags.
32 Hi, Lo, // Hi/Lo operations, typically on a global address.
34 FTOI, // FP to Int within a FP register.
35 ITOF, // Int to FP within a FP register.
37 CALL, // A call instruction.
38 RET_FLAG, // Return with a flag operand.
39 GLOBAL_BASE_REG // Global base reg for PIC
43 class SparcTargetLowering : public TargetLowering {
44 int VarArgsFrameOffset; // Frame offset to start of varargs area.
46 SparcTargetLowering(TargetMachine &TM);
47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
49 int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
51 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
52 /// in Mask are known to be either zero or one and return them in the
53 /// KnownZero/KnownOne bitsets.
54 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
58 const SelectionDAG &DAG,
59 unsigned Depth = 0) const;
61 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
62 MachineBasicBlock *MBB,
63 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
65 virtual const char *getTargetNodeName(unsigned Opcode) const;
67 ConstraintType getConstraintType(const std::string &Constraint) const;
68 std::pair<unsigned, const TargetRegisterClass*>
69 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
71 getRegClassForInlineAsmConstraint(const std::string &Constraint,
74 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
76 /// getFunctionAlignment - Return the Log2 alignment of this function.
77 virtual unsigned getFunctionAlignment(const Function *F) const;
80 LowerFormalArguments(SDValue Chain,
81 CallingConv::ID CallConv,
83 const SmallVectorImpl<ISD::InputArg> &Ins,
84 DebugLoc dl, SelectionDAG &DAG,
85 SmallVectorImpl<SDValue> &InVals);
88 LowerCall(SDValue Chain, SDValue Callee,
89 CallingConv::ID CallConv, bool isVarArg,
91 const SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
93 DebugLoc dl, SelectionDAG &DAG,
94 SmallVectorImpl<SDValue> &InVals);
97 LowerReturn(SDValue Chain,
98 CallingConv::ID CallConv, bool isVarArg,
99 const SmallVectorImpl<ISD::OutputArg> &Outs,
100 DebugLoc dl, SelectionDAG &DAG);
102 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
103 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
105 } // end namespace llvm
107 #endif // SPARC_ISELLOWERING_H