1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
25 enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 CMPICC, // Compare two GPR operands, set icc+xcc.
28 CMPFCC, // Compare two FP operands, set fcc.
29 BRICC, // Branch to dest on icc condition
30 BRXCC, // Branch to dest on xcc condition (64-bit only).
31 BRFCC, // Branch to dest on fcc condition
32 SELECT_ICC, // Select between two values using the current ICC flags.
33 SELECT_XCC, // Select between two values using the current XCC flags.
34 SELECT_FCC, // Select between two values using the current FCC flags.
36 Hi, Lo, // Hi/Lo operations, typically on a global address.
38 FTOI, // FP to Int within a FP register.
39 ITOF, // Int to FP within a FP register.
40 FTOX, // FP to Int64 within a FP register.
41 XTOF, // Int64 to FP within a FP register.
43 CALL, // A call instruction.
44 RET_FLAG, // Return with a flag operand.
45 GLOBAL_BASE_REG, // Global base reg for PIC.
46 FLUSHW, // FLUSH register windows to stack.
48 TLS_ADD, // For Thread Local Storage (TLS).
54 class SparcTargetLowering : public TargetLowering {
55 const SparcSubtarget *Subtarget;
57 SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI);
58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
60 /// computeKnownBitsForTargetNode - Determine which of the bits specified
61 /// in Mask are known to be either zero or one and return them in the
62 /// KnownZero/KnownOne bitsets.
63 void computeKnownBitsForTargetNode(const SDValue Op,
66 const SelectionDAG &DAG,
67 unsigned Depth = 0) const override;
70 EmitInstrWithCustomInserter(MachineInstr *MI,
71 MachineBasicBlock *MBB) const override;
73 const char *getTargetNodeName(unsigned Opcode) const override;
75 ConstraintType getConstraintType(StringRef Constraint) const override;
77 getSingleConstraintMatchWeight(AsmOperandInfo &info,
78 const char *constraint) const override;
79 void LowerAsmOperandForConstraint(SDValue Op,
80 std::string &Constraint,
81 std::vector<SDValue> &Ops,
82 SelectionDAG &DAG) const override;
83 std::pair<unsigned, const TargetRegisterClass *>
84 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
85 StringRef Constraint, MVT VT) const override;
87 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
88 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
92 /// getSetCCResultType - Return the ISD::SETCC ValueType
93 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
94 EVT VT) const override;
97 LowerFormalArguments(SDValue Chain,
98 CallingConv::ID CallConv,
100 const SmallVectorImpl<ISD::InputArg> &Ins,
101 SDLoc dl, SelectionDAG &DAG,
102 SmallVectorImpl<SDValue> &InVals) const override;
103 SDValue LowerFormalArguments_32(SDValue Chain,
104 CallingConv::ID CallConv,
106 const SmallVectorImpl<ISD::InputArg> &Ins,
107 SDLoc dl, SelectionDAG &DAG,
108 SmallVectorImpl<SDValue> &InVals) const;
109 SDValue LowerFormalArguments_64(SDValue Chain,
110 CallingConv::ID CallConv,
112 const SmallVectorImpl<ISD::InputArg> &Ins,
113 SDLoc dl, SelectionDAG &DAG,
114 SmallVectorImpl<SDValue> &InVals) const;
117 LowerCall(TargetLowering::CallLoweringInfo &CLI,
118 SmallVectorImpl<SDValue> &InVals) const override;
119 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
120 SmallVectorImpl<SDValue> &InVals) const;
121 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
122 SmallVectorImpl<SDValue> &InVals) const;
125 LowerReturn(SDValue Chain,
126 CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<SDValue> &OutVals,
129 SDLoc dl, SelectionDAG &DAG) const override;
130 SDValue LowerReturn_32(SDValue Chain,
131 CallingConv::ID CallConv, bool IsVarArg,
132 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<SDValue> &OutVals,
134 SDLoc DL, SelectionDAG &DAG) const;
135 SDValue LowerReturn_64(SDValue Chain,
136 CallingConv::ID CallConv, bool IsVarArg,
137 const SmallVectorImpl<ISD::OutputArg> &Outs,
138 const SmallVectorImpl<SDValue> &OutVals,
139 SDLoc DL, SelectionDAG &DAG) const;
141 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
146 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
147 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
148 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
149 SelectionDAG &DAG) const;
150 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
153 SDValue Arg, SDLoc DL,
154 SelectionDAG &DAG) const;
155 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
156 const char *LibFuncName,
157 unsigned numArgs) const;
158 SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
161 SelectionDAG &DAG) const;
163 bool ShouldShrinkFPConstant(EVT VT) const override {
164 // Do not shrink FP constpool if VT == MVT::f128.
165 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
166 return VT != MVT::f128;
169 void ReplaceNodeResults(SDNode *N,
170 SmallVectorImpl<SDValue>& Results,
171 SelectionDAG &DAG) const override;
173 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB,
174 unsigned BROpcode) const;
175 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI,
176 MachineBasicBlock *BB,
178 unsigned CondCode = 0) const;
180 } // end namespace llvm
182 #endif // SPARC_ISELLOWERING_H