1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef SPARC_ISELLOWERING_H
16 #define SPARC_ISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 CMPICC, // Compare two GPR operands, set icc+xcc.
28 CMPFCC, // Compare two FP operands, set fcc.
29 BRICC, // Branch to dest on icc condition
30 BRXCC, // Branch to dest on xcc condition (64-bit only).
31 BRFCC, // Branch to dest on fcc condition
32 SELECT_ICC, // Select between two values using the current ICC flags.
33 SELECT_XCC, // Select between two values using the current XCC flags.
34 SELECT_FCC, // Select between two values using the current FCC flags.
36 Hi, Lo, // Hi/Lo operations, typically on a global address.
38 FTOI, // FP to Int within a FP register.
39 ITOF, // Int to FP within a FP register.
41 CALL, // A call instruction.
42 RET_FLAG, // Return with a flag operand.
43 GLOBAL_BASE_REG, // Global base reg for PIC
44 FLUSHW // FLUSH register windows to stack
48 class SparcTargetLowering : public TargetLowering {
49 const SparcSubtarget *Subtarget;
51 SparcTargetLowering(TargetMachine &TM);
52 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
54 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
55 /// in Mask are known to be either zero or one and return them in the
56 /// KnownZero/KnownOne bitsets.
57 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
60 const SelectionDAG &DAG,
61 unsigned Depth = 0) const;
63 virtual MachineBasicBlock *
64 EmitInstrWithCustomInserter(MachineInstr *MI,
65 MachineBasicBlock *MBB) const;
67 virtual const char *getTargetNodeName(unsigned Opcode) const;
69 ConstraintType getConstraintType(const std::string &Constraint) const;
70 std::pair<unsigned, const TargetRegisterClass*>
71 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
73 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
76 LowerFormalArguments(SDValue Chain,
77 CallingConv::ID CallConv,
79 const SmallVectorImpl<ISD::InputArg> &Ins,
80 DebugLoc dl, SelectionDAG &DAG,
81 SmallVectorImpl<SDValue> &InVals) const;
82 SDValue LowerFormalArguments_32(SDValue Chain,
83 CallingConv::ID CallConv,
85 const SmallVectorImpl<ISD::InputArg> &Ins,
86 DebugLoc dl, SelectionDAG &DAG,
87 SmallVectorImpl<SDValue> &InVals) const;
88 SDValue LowerFormalArguments_64(SDValue Chain,
89 CallingConv::ID CallConv,
91 const SmallVectorImpl<ISD::InputArg> &Ins,
92 DebugLoc dl, SelectionDAG &DAG,
93 SmallVectorImpl<SDValue> &InVals) const;
96 LowerCall(TargetLowering::CallLoweringInfo &CLI,
97 SmallVectorImpl<SDValue> &InVals) const;
100 LowerReturn(SDValue Chain,
101 CallingConv::ID CallConv, bool isVarArg,
102 const SmallVectorImpl<ISD::OutputArg> &Outs,
103 const SmallVectorImpl<SDValue> &OutVals,
104 DebugLoc dl, SelectionDAG &DAG) const;
106 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
109 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
111 } // end namespace llvm
113 #endif // SPARC_ISELLOWERING_H