1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef SPARC_ISELLOWERING_H
16 #define SPARC_ISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
24 FIRST_NUMBER = ISD::BUILTIN_OP_END,
25 CMPICC, // Compare two GPR operands, set icc.
26 CMPFCC, // Compare two FP operands, set fcc.
27 BRICC, // Branch to dest on icc condition
28 BRFCC, // Branch to dest on fcc condition
29 SELECT_ICC, // Select between two values using the current ICC flags.
30 SELECT_FCC, // Select between two values using the current FCC flags.
32 Hi, Lo, // Hi/Lo operations, typically on a global address.
34 FTOI, // FP to Int within a FP register.
35 ITOF, // Int to FP within a FP register.
37 CALL, // A call instruction.
38 RET_FLAG, // Return with a flag operand.
39 GLOBAL_BASE_REG, // Global base reg for PIC
40 FLUSHW // FLUSH register windows to stack
44 class SparcTargetLowering : public TargetLowering {
46 SparcTargetLowering(TargetMachine &TM);
47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
49 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
50 /// in Mask are known to be either zero or one and return them in the
51 /// KnownZero/KnownOne bitsets.
52 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
55 const SelectionDAG &DAG,
56 unsigned Depth = 0) const;
58 virtual MachineBasicBlock *
59 EmitInstrWithCustomInserter(MachineInstr *MI,
60 MachineBasicBlock *MBB) const;
62 virtual const char *getTargetNodeName(unsigned Opcode) const;
64 ConstraintType getConstraintType(const std::string &Constraint) const;
65 std::pair<unsigned, const TargetRegisterClass*>
66 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
68 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
71 LowerFormalArguments(SDValue Chain,
72 CallingConv::ID CallConv,
74 const SmallVectorImpl<ISD::InputArg> &Ins,
75 DebugLoc dl, SelectionDAG &DAG,
76 SmallVectorImpl<SDValue> &InVals) const;
79 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
80 bool isVarArg, bool doesNotRet, bool &isTailCall,
81 const SmallVectorImpl<ISD::OutputArg> &Outs,
82 const SmallVectorImpl<SDValue> &OutVals,
83 const SmallVectorImpl<ISD::InputArg> &Ins,
84 DebugLoc dl, SelectionDAG &DAG,
85 SmallVectorImpl<SDValue> &InVals) const;
88 LowerReturn(SDValue Chain,
89 CallingConv::ID CallConv, bool isVarArg,
90 const SmallVectorImpl<ISD::OutputArg> &Outs,
91 const SmallVectorImpl<SDValue> &OutVals,
92 DebugLoc dl, SelectionDAG &DAG) const;
94 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
95 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
97 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
99 } // end namespace llvm
101 #endif // SPARC_ISELLOWERING_H