1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
25 enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 CMPICC, // Compare two GPR operands, set icc+xcc.
28 CMPFCC, // Compare two FP operands, set fcc.
29 BRICC, // Branch to dest on icc condition
30 BRXCC, // Branch to dest on xcc condition (64-bit only).
31 BRFCC, // Branch to dest on fcc condition
32 SELECT_ICC, // Select between two values using the current ICC flags.
33 SELECT_XCC, // Select between two values using the current XCC flags.
34 SELECT_FCC, // Select between two values using the current FCC flags.
36 Hi, Lo, // Hi/Lo operations, typically on a global address.
38 FTOI, // FP to Int within a FP register.
39 ITOF, // Int to FP within a FP register.
40 FTOX, // FP to Int64 within a FP register.
41 XTOF, // Int64 to FP within a FP register.
43 CALL, // A call instruction.
44 RET_FLAG, // Return with a flag operand.
45 GLOBAL_BASE_REG, // Global base reg for PIC.
46 FLUSHW, // FLUSH register windows to stack.
48 TLS_ADD, // For Thread Local Storage (TLS).
54 class SparcTargetLowering : public TargetLowering {
55 const SparcSubtarget *Subtarget;
57 SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI);
58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
60 /// computeKnownBitsForTargetNode - Determine which of the bits specified
61 /// in Mask are known to be either zero or one and return them in the
62 /// KnownZero/KnownOne bitsets.
63 void computeKnownBitsForTargetNode(const SDValue Op,
66 const SelectionDAG &DAG,
67 unsigned Depth = 0) const override;
70 EmitInstrWithCustomInserter(MachineInstr *MI,
71 MachineBasicBlock *MBB) const override;
73 const char *getTargetNodeName(unsigned Opcode) const override;
75 ConstraintType getConstraintType(StringRef Constraint) const override;
77 getSingleConstraintMatchWeight(AsmOperandInfo &info,
78 const char *constraint) const override;
79 void LowerAsmOperandForConstraint(SDValue Op,
80 std::string &Constraint,
81 std::vector<SDValue> &Ops,
82 SelectionDAG &DAG) const override;
83 std::pair<unsigned, const TargetRegisterClass *>
84 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
85 StringRef Constraint, MVT VT) const override;
87 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
88 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
92 /// If a physical register, this returns the register that receives the
93 /// exception address on entry to an EH pad.
95 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
99 /// If a physical register, this returns the register that receives the
100 /// exception typeid on entry to a landing pad.
102 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
106 /// getSetCCResultType - Return the ISD::SETCC ValueType
107 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
108 EVT VT) const override;
111 LowerFormalArguments(SDValue Chain,
112 CallingConv::ID CallConv,
114 const SmallVectorImpl<ISD::InputArg> &Ins,
115 SDLoc dl, SelectionDAG &DAG,
116 SmallVectorImpl<SDValue> &InVals) const override;
117 SDValue LowerFormalArguments_32(SDValue Chain,
118 CallingConv::ID CallConv,
120 const SmallVectorImpl<ISD::InputArg> &Ins,
121 SDLoc dl, SelectionDAG &DAG,
122 SmallVectorImpl<SDValue> &InVals) const;
123 SDValue LowerFormalArguments_64(SDValue Chain,
124 CallingConv::ID CallConv,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
127 SDLoc dl, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals) const;
131 LowerCall(TargetLowering::CallLoweringInfo &CLI,
132 SmallVectorImpl<SDValue> &InVals) const override;
133 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
134 SmallVectorImpl<SDValue> &InVals) const;
135 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
136 SmallVectorImpl<SDValue> &InVals) const;
139 LowerReturn(SDValue Chain,
140 CallingConv::ID CallConv, bool isVarArg,
141 const SmallVectorImpl<ISD::OutputArg> &Outs,
142 const SmallVectorImpl<SDValue> &OutVals,
143 SDLoc dl, SelectionDAG &DAG) const override;
144 SDValue LowerReturn_32(SDValue Chain,
145 CallingConv::ID CallConv, bool IsVarArg,
146 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<SDValue> &OutVals,
148 SDLoc DL, SelectionDAG &DAG) const;
149 SDValue LowerReturn_64(SDValue Chain,
150 CallingConv::ID CallConv, bool IsVarArg,
151 const SmallVectorImpl<ISD::OutputArg> &Outs,
152 const SmallVectorImpl<SDValue> &OutVals,
153 SDLoc DL, SelectionDAG &DAG) const;
155 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
160 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
161 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
162 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
163 SelectionDAG &DAG) const;
164 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
167 SDValue Arg, SDLoc DL,
168 SelectionDAG &DAG) const;
169 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
170 const char *LibFuncName,
171 unsigned numArgs) const;
172 SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
175 SelectionDAG &DAG) const;
177 bool ShouldShrinkFPConstant(EVT VT) const override {
178 // Do not shrink FP constpool if VT == MVT::f128.
179 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
180 return VT != MVT::f128;
183 void ReplaceNodeResults(SDNode *N,
184 SmallVectorImpl<SDValue>& Results,
185 SelectionDAG &DAG) const override;
187 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB,
188 unsigned BROpcode) const;
189 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI,
190 MachineBasicBlock *BB,
192 unsigned CondCode = 0) const;
194 } // end namespace llvm
196 #endif // SPARC_ISELLOWERING_H