1 //===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction definitions and patterns needed for 64-bit
11 // code generation on SPARC v9.
13 // Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
14 // also be used in 32-bit code running on a SPARC v9 CPU.
16 //===----------------------------------------------------------------------===//
18 let Predicates = [Is64Bit] in {
19 // The same integer registers are used for i32 and i64 values.
20 // When registers hold i32 values, the high bits are don't care.
21 // This give us free trunc and anyext.
22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
25 } // Predicates = [Is64Bit]
28 //===----------------------------------------------------------------------===//
29 // 64-bit Shift Instructions.
30 //===----------------------------------------------------------------------===//
32 // The 32-bit shift instructions are still available. The left shift srl
33 // instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
35 // The srl instructions only shift the low 32 bits and clear the high 32 bits.
36 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
38 let Predicates = [Is64Bit] in {
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
46 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
47 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
48 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
50 } // Predicates = [Is64Bit]
53 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
58 // immediates may require more code. There may be a point where it is
59 // preferable to use a constant pool load instead, depending on the
62 // Single-instruction patterns.
64 // The ALU instructions want their simm13 operands as i32 immediates.
65 def as_i32imm : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
71 // Double-instruction patterns.
73 // All unsigned i32 immediates can be handled by sethi+or.
74 def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
78 // All negative i33 immediates can be handled by sethi+xor.
79 def nimm33 : PatLeaf<(imm), [{
80 int64_t Imm = N->getSExtValue();
81 return Imm < 0 && isInt<33>(Imm);
83 // Bits 10-31 inverted. Same as assembler's %hix.
84 def HIX22 : SDNodeXForm<imm, [{
85 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
86 return CurDAG->getTargetConstant(Val, MVT::i32);
88 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
89 def LOX10 : SDNodeXForm<imm, [{
90 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
92 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
95 // More possible patterns:
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
107 // (or sethi, (sllx sethi))
108 // (xnor sethi, (sllx sethi))
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
114 // (or (sllx sethi), (sllx sethi))
115 // (xnor (sllx sethi), (sllx sethi))
117 // Worst case is 6 instrs:
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
121 // Bits 42-63, same as assembler's %hh.
122 def HH22 : SDNodeXForm<imm, [{
123 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
124 return CurDAG->getTargetConstant(Val, MVT::i32);
126 // Bits 32-41, same as assembler's %hm.
127 def HM10 : SDNodeXForm<imm, [{
128 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
129 return CurDAG->getTargetConstant(Val, MVT::i32);
131 def : Pat<(i64 imm:$val),
132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
137 //===----------------------------------------------------------------------===//
138 // 64-bit Integer Arithmetic and Logic.
139 //===----------------------------------------------------------------------===//
141 let Predicates = [Is64Bit] in {
143 // Register-register instructions.
144 let isCodeGenOnly = 1 in {
145 defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
146 defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
147 defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
149 def ANDXNrr : F3_1<2, 0b000101,
150 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
152 [(set i64:$dst, (and i64:$b, (not i64:$c)))]>;
153 def ORXNrr : F3_1<2, 0b000110,
154 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
156 [(set i64:$dst, (or i64:$b, (not i64:$c)))]>;
157 def XNORXrr : F3_1<2, 0b000111,
158 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
160 [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
162 defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
163 defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
165 def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
166 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
167 "add $rs1, $rs2, $rd, $sym",
169 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
172 def LEAX_ADDri : F3_2<2, 0b000000,
173 (outs I64Regs:$dst), (ins MEMri:$addr),
174 "add ${addr:arith}, $dst",
175 [(set iPTR:$dst, ADDRri:$addr)]>;
178 def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
179 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
180 def : Pat<(ctpop i64:$src), (POPCrr $src)>;
182 } // Predicates = [Is64Bit]
185 //===----------------------------------------------------------------------===//
186 // 64-bit Integer Multiply and Divide.
187 //===----------------------------------------------------------------------===//
189 let Predicates = [Is64Bit] in {
191 def MULXrr : F3_1<2, 0b001001,
192 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
193 "mulx $rs1, $rs2, $rd",
194 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
195 def MULXri : F3_2<2, 0b001001,
196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
197 "mulx $rs1, $simm13, $rd",
198 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
200 // Division can trap.
201 let hasSideEffects = 1 in {
202 def SDIVXrr : F3_1<2, 0b101101,
203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
204 "sdivx $rs1, $rs2, $rd",
205 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
206 def SDIVXri : F3_2<2, 0b101101,
207 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
208 "sdivx $rs1, $simm13, $rd",
209 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
211 def UDIVXrr : F3_1<2, 0b001101,
212 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
213 "udivx $rs1, $rs2, $rd",
214 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
215 def UDIVXri : F3_2<2, 0b001101,
216 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
217 "udivx $rs1, $simm13, $rd",
218 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
219 } // hasSideEffects = 1
221 } // Predicates = [Is64Bit]
224 //===----------------------------------------------------------------------===//
225 // 64-bit Loads and Stores.
226 //===----------------------------------------------------------------------===//
228 // All the 32-bit loads and stores are available. The extending loads are sign
229 // or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
230 // zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
233 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
235 let Predicates = [Is64Bit] in {
238 defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>;
240 let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
241 def TLS_LDXrr : F3_1<3, 0b001011,
242 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
243 "ldx [$addr], $dst, $sym",
245 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
247 // Extending loads to i64.
248 def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
249 def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
250 def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
251 def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
253 def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
254 def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
255 def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
256 def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
257 def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
258 def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
260 def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
261 def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
262 def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
263 def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
264 def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
265 def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
267 def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
268 def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
269 def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
270 def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
272 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
273 defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
276 defm STX : Store<"stx", 0b001110, store, I64Regs, i64>;
278 // Truncating stores from i64 are identical to the i32 stores.
279 def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
280 def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
281 def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
282 def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
283 def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;
284 def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;
286 // store 0, addr -> store %g0, addr
287 def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>;
288 def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
290 } // Predicates = [Is64Bit]
293 //===----------------------------------------------------------------------===//
294 // 64-bit Conditionals.
295 //===----------------------------------------------------------------------===//
297 // Conditional branch class on %xcc:
298 class XBranchSP<dag ins, string asmstr, list<dag> pattern>
299 : F2_3<0b001, 0b10, (outs), ins, asmstr, pattern> {
301 let isTerminator = 1;
302 let hasDelaySlot = 1;
306 // Flag-setting instructions like subcc and addcc set both icc and xcc flags.
307 // The icc flags correspond to the 32-bit result, and the xcc are for the
308 // full 64-bit result.
310 // We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
311 // 64-bit compares. See LowerBR_CC.
313 let Predicates = [Is64Bit] in {
316 def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond),
317 "b$cond %xcc, $imm19",
318 [(SPbrxcc bb:$imm19, imm:$cond)]>;
320 // Conditional moves on %xcc.
321 let Uses = [ICC], Constraints = "$f = $rd" in {
323 def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
324 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
325 "mov$cond %xcc, $rs2, $rd",
327 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
328 def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
329 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
330 "mov$cond %xcc, $simm11, $rd",
332 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
335 let opf_cc = 0b110 in {
336 def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
337 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
338 "fmovs$cond %xcc, $rs2, $rd",
340 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
341 def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
342 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
343 "fmovd$cond %xcc, $rs2, $rd",
345 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
346 def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
347 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
348 "fmovq$cond %xcc, $rs2, $rd",
350 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
352 } // Uses, Constraints
354 //===----------------------------------------------------------------------===//
355 // 64-bit Floating Point Conversions.
356 //===----------------------------------------------------------------------===//
358 let Predicates = [Is64Bit] in {
360 def FXTOS : F3_3u<2, 0b110100, 0b010000100,
361 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
363 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
364 def FXTOD : F3_3u<2, 0b110100, 0b010001000,
365 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
367 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
368 def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
369 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
371 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>,
372 Requires<[HasHardQuad]>;
374 def FSTOX : F3_3u<2, 0b110100, 0b010000001,
375 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
377 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
378 def FDTOX : F3_3u<2, 0b110100, 0b010000010,
379 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
381 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>;
382 def FQTOX : F3_3u<2, 0b110100, 0b010000011,
383 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
385 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>,
386 Requires<[HasHardQuad]>;
388 } // Predicates = [Is64Bit]
390 def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
391 (MOVXCCrr $t, $f, imm:$cond)>;
392 def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
393 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
395 def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond),
396 (MOVICCrr $t, $f, imm:$cond)>;
397 def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),
398 (MOVICCri (as_i32imm $t), $f, imm:$cond)>;
400 def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),
401 (MOVFCCrr $t, $f, imm:$cond)>;
402 def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
403 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
405 } // Predicates = [Is64Bit]
409 let Predicates = [Is64Bit], isCodeGenOnly = 1 in {
410 def SETHIXi : F2_1<0b100,
411 (outs IntRegs:$rd), (ins i64imm:$imm22),
413 [(set i64:$rd, SETHIimm:$imm22)]>;
417 let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
418 def CASXrr: F3_1<3, 0b111110,
419 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
421 "casx [$rs1], $rs2, $rd",
423 (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
425 } // Predicates = [Is64Bit], Constraints = ...
427 let Predicates = [Is64Bit] in {
429 def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
431 // atomic_load_64 addr -> load addr
432 def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
433 def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>;
435 // atomic_store_64 val, addr -> store val, addr
436 def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
437 def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
439 } // Predicates = [Is64Bit]
441 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
443 multiclass AtomicRMW<SDPatternOperator op32, SDPatternOperator op64> {
445 def _32 : Pseudo<(outs IntRegs:$rd),
446 (ins ptr_rc:$addr, IntRegs:$rs2), "",
447 [(set i32:$rd, (op32 iPTR:$addr, i32:$rs2))]>;
449 let Predicates = [Is64Bit] in
450 def _64 : Pseudo<(outs I64Regs:$rd),
451 (ins ptr_rc:$addr, I64Regs:$rs2), "",
452 [(set i64:$rd, (op64 iPTR:$addr, i64:$rs2))]>;
455 defm ATOMIC_LOAD_ADD : AtomicRMW<atomic_load_add_32, atomic_load_add_64>;
456 defm ATOMIC_LOAD_SUB : AtomicRMW<atomic_load_sub_32, atomic_load_sub_64>;
457 defm ATOMIC_LOAD_AND : AtomicRMW<atomic_load_and_32, atomic_load_and_64>;
458 defm ATOMIC_LOAD_OR : AtomicRMW<atomic_load_or_32, atomic_load_or_64>;
459 defm ATOMIC_LOAD_XOR : AtomicRMW<atomic_load_xor_32, atomic_load_xor_64>;
460 defm ATOMIC_LOAD_NAND : AtomicRMW<atomic_load_nand_32, atomic_load_nand_64>;
461 defm ATOMIC_LOAD_MIN : AtomicRMW<atomic_load_min_32, atomic_load_min_64>;
462 defm ATOMIC_LOAD_MAX : AtomicRMW<atomic_load_max_32, atomic_load_max_64>;
463 defm ATOMIC_LOAD_UMIN : AtomicRMW<atomic_load_umin_32, atomic_load_umin_64>;
464 defm ATOMIC_LOAD_UMAX : AtomicRMW<atomic_load_umax_32, atomic_load_umax_64>;
466 // There is no 64-bit variant of SWAP, so use a pseudo.
467 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
468 Defs = [ICC], Predicates = [Is64Bit] in
469 def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
470 (ins ptr_rc:$addr, I64Regs:$rs2), "",
472 (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
474 // Global addresses, constant pool entries
475 let Predicates = [Is64Bit] in {
477 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
478 def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>;
479 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
480 def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>;
482 // GlobalTLS addresses
483 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
484 def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>;
485 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
486 (ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
487 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
488 (XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
491 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
492 def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>;
494 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
495 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
496 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
497 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
498 (ADDXri $r, tblockaddress:$in)>;