1 //===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction definitions and patterns needed for 64-bit
11 // code generation on SPARC v9.
13 // Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
14 // also be used in 32-bit code running on a SPARC v9 CPU.
16 //===----------------------------------------------------------------------===//
18 let Predicates = [Is64Bit] in {
19 // The same integer registers are used for i32 and i64 values.
20 // When registers hold i32 values, the high bits are don't care.
21 // This give us free trunc and anyext.
22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
25 } // Predicates = [Is64Bit]
28 //===----------------------------------------------------------------------===//
29 // 64-bit Shift Instructions.
30 //===----------------------------------------------------------------------===//
32 // The 32-bit shift instructions are still available. The left shift srl
33 // instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
35 // The srl instructions only shift the low 32 bits and clear the high 32 bits.
36 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
38 let Predicates = [Is64Bit] in {
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
46 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
47 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
48 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
50 } // Predicates = [Is64Bit]
53 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
58 // immediates may require more code. There may be a point where it is
59 // preferable to use a constant pool load instead, depending on the
62 // Single-instruction patterns.
64 // The ALU instructions want their simm13 operands as i32 immediates.
65 def as_i32imm : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
71 // Double-instruction patterns.
73 // All unsigned i32 immediates can be handled by sethi+or.
74 def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
78 // All negative i33 immediates can be handled by sethi+xor.
79 def nimm33 : PatLeaf<(imm), [{
80 int64_t Imm = N->getSExtValue();
81 return Imm < 0 && isInt<33>(Imm);
83 // Bits 10-31 inverted. Same as assembler's %hix.
84 def HIX22 : SDNodeXForm<imm, [{
85 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
86 return CurDAG->getTargetConstant(Val, MVT::i32);
88 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
89 def LOX10 : SDNodeXForm<imm, [{
90 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
92 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
95 // More possible patterns:
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
107 // (or sethi, (sllx sethi))
108 // (xnor sethi, (sllx sethi))
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
114 // (or (sllx sethi), (sllx sethi))
115 // (xnor (sllx sethi), (sllx sethi))
117 // Worst case is 6 instrs:
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
121 // Bits 42-63, same as assembler's %hh.
122 def HH22 : SDNodeXForm<imm, [{
123 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
124 return CurDAG->getTargetConstant(Val, MVT::i32);
126 // Bits 32-41, same as assembler's %hm.
127 def HM10 : SDNodeXForm<imm, [{
128 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
129 return CurDAG->getTargetConstant(Val, MVT::i32);
131 def : Pat<(i64 imm:$val),
132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
137 //===----------------------------------------------------------------------===//
138 // 64-bit Integer Arithmetic and Logic.
139 //===----------------------------------------------------------------------===//
141 let Predicates = [Is64Bit] in {
143 // Register-register instructions.
144 defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
145 defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
146 defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
148 def ANDXNrr : F3_1<2, 0b000101,
149 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
151 [(set i64:$dst, (and i64:$b, (not i64:$c)))]>;
152 def ORXNrr : F3_1<2, 0b000110,
153 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
155 [(set i64:$dst, (or i64:$b, (not i64:$c)))]>;
156 def XNORXrr : F3_1<2, 0b000111,
157 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
159 [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
161 defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
162 defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
164 def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
166 def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
167 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
168 "add $rs1, $rs2, $rd, $sym",
170 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
172 // Register-immediate instructions.
174 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
176 def : Pat<(ctpop i64:$src), (POPCrr $src)>;
179 def LEAX_ADDri : F3_2<2, 0b000000,
180 (outs I64Regs:$dst), (ins MEMri:$addr),
181 "add ${addr:arith}, $dst",
182 [(set iPTR:$dst, ADDRri:$addr)]>;
184 } // Predicates = [Is64Bit]
187 //===----------------------------------------------------------------------===//
188 // 64-bit Integer Multiply and Divide.
189 //===----------------------------------------------------------------------===//
191 let Predicates = [Is64Bit] in {
193 def MULXrr : F3_1<2, 0b001001,
194 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
195 "mulx $rs1, $rs2, $rd",
196 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
197 def MULXri : F3_2<2, 0b001001,
198 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
199 "mulx $rs1, $i, $rd",
200 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
202 // Division can trap.
203 let hasSideEffects = 1 in {
204 def SDIVXrr : F3_1<2, 0b101101,
205 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
206 "sdivx $rs1, $rs2, $rd",
207 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
208 def SDIVXri : F3_2<2, 0b101101,
209 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
210 "sdivx $rs1, $i, $rd",
211 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
213 def UDIVXrr : F3_1<2, 0b001101,
214 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
215 "udivx $rs1, $rs2, $rd",
216 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
217 def UDIVXri : F3_2<2, 0b001101,
218 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
219 "udivx $rs1, $i, $rd",
220 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
221 } // hasSideEffects = 1
223 } // Predicates = [Is64Bit]
226 //===----------------------------------------------------------------------===//
227 // 64-bit Loads and Stores.
228 //===----------------------------------------------------------------------===//
230 // All the 32-bit loads and stores are available. The extending loads are sign
231 // or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
232 // zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
235 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
237 let Predicates = [Is64Bit] in {
240 def LDXrr : F3_1<3, 0b001011,
241 (outs I64Regs:$dst), (ins MEMrr:$addr),
243 [(set i64:$dst, (load ADDRrr:$addr))]>;
244 def LDXri : F3_2<3, 0b001011,
245 (outs I64Regs:$dst), (ins MEMri:$addr),
247 [(set i64:$dst, (load ADDRri:$addr))]>;
249 def TLS_LDXrr : F3_1<3, 0b001011,
250 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
251 "ldx [$addr], $dst, $sym",
253 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
255 // Extending loads to i64.
256 def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
257 def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
258 def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
259 def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
261 def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
262 def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
263 def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
264 def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
265 def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
266 def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
268 def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
269 def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
270 def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
271 def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
272 def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
273 def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
275 def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
276 def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
277 def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
278 def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
280 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
281 def LDSWrr : F3_1<3, 0b001011,
282 (outs I64Regs:$dst), (ins MEMrr:$addr),
283 "ldsw [$addr], $dst",
284 [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
285 def LDSWri : F3_2<3, 0b001011,
286 (outs I64Regs:$dst), (ins MEMri:$addr),
287 "ldsw [$addr], $dst",
288 [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
291 def STXrr : F3_1<3, 0b001110,
292 (outs), (ins MEMrr:$addr, I64Regs:$src),
294 [(store i64:$src, ADDRrr:$addr)]>;
295 def STXri : F3_2<3, 0b001110,
296 (outs), (ins MEMri:$addr, I64Regs:$src),
298 [(store i64:$src, ADDRri:$addr)]>;
300 // Truncating stores from i64 are identical to the i32 stores.
301 def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
302 def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
303 def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
304 def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
305 def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;
306 def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;
308 // store 0, addr -> store %g0, addr
309 def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>;
310 def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
312 } // Predicates = [Is64Bit]
315 //===----------------------------------------------------------------------===//
316 // 64-bit Conditionals.
317 //===----------------------------------------------------------------------===//
319 // Flag-setting instructions like subcc and addcc set both icc and xcc flags.
320 // The icc flags correspond to the 32-bit result, and the xcc are for the
321 // full 64-bit result.
323 // We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
324 // 64-bit compares. See LowerBR_CC.
326 let Predicates = [Is64Bit] in {
329 def BPXCC : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
330 "b$cond %xcc, $imm22",
331 [(SPbrxcc bb:$imm22, imm:$cond)]>;
333 // Conditional moves on %xcc.
334 let Uses = [ICC], Constraints = "$f = $rd" in {
335 def MOVXCCrr : Pseudo<(outs IntRegs:$rd),
336 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
337 "mov$cond %xcc, $rs2, $rd",
339 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
340 def MOVXCCri : Pseudo<(outs IntRegs:$rd),
341 (ins i32imm:$i, IntRegs:$f, CCOp:$cond),
342 "mov$cond %xcc, $i, $rd",
344 (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
345 def FMOVS_XCC : Pseudo<(outs FPRegs:$rd),
346 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
347 "fmovs$cond %xcc, $rs2, $rd",
349 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
350 def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
351 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
352 "fmovd$cond %xcc, $rs2, $rd",
354 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
355 } // Uses, Constraints
357 //===----------------------------------------------------------------------===//
358 // 64-bit Floating Point Conversions.
359 //===----------------------------------------------------------------------===//
361 let Predicates = [Is64Bit] in {
363 def FXTOS : F3_3u<2, 0b110100, 0b010000100,
364 (outs FPRegs:$dst), (ins DFPRegs:$src),
366 [(set FPRegs:$dst, (SPxtof DFPRegs:$src))]>;
367 def FXTOD : F3_3u<2, 0b110100, 0b010001000,
368 (outs DFPRegs:$dst), (ins DFPRegs:$src),
370 [(set DFPRegs:$dst, (SPxtof DFPRegs:$src))]>;
371 def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
372 (outs QFPRegs:$dst), (ins DFPRegs:$src),
374 [(set QFPRegs:$dst, (SPxtof DFPRegs:$src))]>,
375 Requires<[HasHardQuad]>;
377 def FSTOX : F3_3u<2, 0b110100, 0b010000001,
378 (outs DFPRegs:$dst), (ins FPRegs:$src),
380 [(set DFPRegs:$dst, (SPftox FPRegs:$src))]>;
381 def FDTOX : F3_3u<2, 0b110100, 0b010000010,
382 (outs DFPRegs:$dst), (ins DFPRegs:$src),
384 [(set DFPRegs:$dst, (SPftox DFPRegs:$src))]>;
385 def FQTOX : F3_3u<2, 0b110100, 0b010000011,
386 (outs DFPRegs:$dst), (ins QFPRegs:$src),
388 [(set DFPRegs:$dst, (SPftox QFPRegs:$src))]>,
389 Requires<[HasHardQuad]>;
391 } // Predicates = [Is64Bit]
393 def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
394 (MOVXCCrr $t, $f, imm:$cond)>;
395 def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
396 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
398 def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond),
399 (MOVICCrr $t, $f, imm:$cond)>;
400 def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),
401 (MOVICCri (as_i32imm $t), $f, imm:$cond)>;
403 def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),
404 (MOVFCCrr $t, $f, imm:$cond)>;
405 def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
406 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
408 } // Predicates = [Is64Bit]
412 let Predicates = [Is64Bit] in {
413 def SETHIXi : F2_1<0b100,
414 (outs IntRegs:$rd), (ins i64imm:$imm22),
416 [(set i64:$rd, SETHIimm:$imm22)]>;
418 // Global addresses, constant pool entries
419 let Predicates = [Is64Bit] in {
421 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
422 def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>;
423 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
424 def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>;
426 // GlobalTLS addresses
427 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
428 def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>;
429 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
430 (ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
431 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
432 (XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
435 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
436 def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>;
438 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
439 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
440 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
441 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
442 (ADDXri $r, tblockaddress:$in)>;