1 //===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction aliases for Sparc.
11 //===----------------------------------------------------------------------===//
13 // Instruction aliases for conditional moves.
15 // mov<cond> <ccreg> rs2, rd
16 multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
17 Instruction movrr, Instruction movri,
18 Instruction fmovs, Instruction fmovd> {
20 // mov<cond> (%icc|%xcc), rs2, rd
21 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25 // mov<cond> (%icc|%xcc), simm11, rd
26 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
35 // fmovd<cond> (%icc|%xcc), $rs2, $rd
36 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
38 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
41 // mov<cond> <ccreg> rs2, rd
42 multiclass fpcond_mov_alias<string cond, int condVal,
43 Instruction movrr, Instruction movri,
44 Instruction fmovs, Instruction fmovd> {
46 // mov<cond> %fcc[0-3], rs2, rd
47 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
48 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
50 // mov<cond> %fcc[0-3], simm11, rd
51 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
52 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
54 // fmovs<cond> %fcc[0-3], $rs2, $rd
55 def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
56 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
58 // fmovd<cond> %fcc[0-3], $rs2, $rd
59 def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
60 (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
63 // Instruction aliases for integer conditional branches and moves.
64 multiclass int_cond_alias<string cond, int condVal> {
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
79 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
82 // b<cond>,a %icc, $imm
83 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
86 // b<cond>,a,pt %icc, $imm
87 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
90 // b<cond>,pn %icc, $imm
91 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
94 // b<cond>,a,pn %icc, $imm
95 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
99 def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
102 // b<cond>,pt %xcc, $imm
103 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
106 // b<cond>,a %xcc, $imm
107 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
108 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
110 // b<cond>,a,pt %xcc, $imm
111 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
112 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
114 // b<cond>,pn %xcc, $imm
115 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
116 (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
118 // b<cond>,a,pn %xcc, $imm
119 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
120 (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
123 defm : intcond_mov_alias<cond, condVal, " %icc",
125 FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
127 defm : intcond_mov_alias<cond, condVal, " %xcc",
129 FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
131 // fmovq<cond> (%icc|%xcc), $rs2, $rd
132 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
133 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
134 Requires<[HasV9, HasHardQuad]>;
135 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
136 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
137 Requires<[Is64Bit, HasHardQuad]>;
139 // t<cond> %icc, rs1 + rs2
140 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
141 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
144 // t<cond> %icc, rs => t<cond> %icc, G0 + rs
145 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
146 (TICCrr G0, IntRegs:$rs2, condVal)>,
149 // t<cond> %xcc, rs1 + rs2
150 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
151 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
154 // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
155 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
156 (TXCCrr G0, IntRegs:$rs2, condVal)>,
159 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
160 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
161 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
163 // t<cond> rs=> t<cond> %icc, G0 + rs2
164 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
165 (TICCrr G0, IntRegs:$rs2, condVal)>;
167 // t<cond> %icc, rs1 + imm
168 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
169 (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
171 // t<cond> %icc, imm => t<cond> %icc, G0 + imm
172 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
173 (TICCri G0, i32imm:$imm, condVal)>,
175 // t<cond> %xcc, rs1 + imm
176 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
177 (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
179 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
180 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
181 (TXCCri G0, i32imm:$imm, condVal)>,
184 // t<cond> rs1 + imm => t<cond> %icc, rs1 + imm
185 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
186 (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>;
188 // t<cond> imm => t<cond> %icc, G0 + imm
189 def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
190 (TICCri G0, i32imm:$imm, condVal)>;
195 // Instruction aliases for floating point conditional branches and moves.
196 multiclass fp_cond_alias<string cond, int condVal> {
199 def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
200 (FBCOND brtarget:$imm, condVal), 0>;
203 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
204 (FBCONDA brtarget:$imm, condVal), 0>;
206 // fb<cond> %fcc0, $imm
207 def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
208 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
211 // fb<cond>,pt %fcc0, $imm
212 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
213 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
216 // fb<cond>,a %fcc0, $imm
217 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
218 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
221 // fb<cond>,a,pt %fcc0, $imm
222 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
223 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
226 // fb<cond>,pn %fcc0, $imm
227 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
228 (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
231 // fb<cond>,a,pn %fcc0, $imm
232 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
233 (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
236 defm : fpcond_mov_alias<cond, condVal,
237 V9MOVFCCrr, V9MOVFCCri,
238 V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
240 // fmovq<cond> %fcc0, $rs2, $rd
241 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
242 (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
244 Requires<[HasV9, HasHardQuad]>;
247 defm : int_cond_alias<"a", 0b1000>;
248 defm : int_cond_alias<"n", 0b0000>;
249 defm : int_cond_alias<"ne", 0b1001>;
250 defm : int_cond_alias<"e", 0b0001>;
251 defm : int_cond_alias<"g", 0b1010>;
252 defm : int_cond_alias<"le", 0b0010>;
253 defm : int_cond_alias<"ge", 0b1011>;
254 defm : int_cond_alias<"l", 0b0011>;
255 defm : int_cond_alias<"gu", 0b1100>;
256 defm : int_cond_alias<"leu", 0b0100>;
257 defm : int_cond_alias<"cc", 0b1101>;
258 defm : int_cond_alias<"cs", 0b0101>;
259 defm : int_cond_alias<"pos", 0b1110>;
260 defm : int_cond_alias<"neg", 0b0110>;
261 defm : int_cond_alias<"vc", 0b1111>;
262 defm : int_cond_alias<"vs", 0b0111>;
264 defm : fp_cond_alias<"a", 0b0000>;
265 defm : fp_cond_alias<"n", 0b1000>;
266 defm : fp_cond_alias<"u", 0b0111>;
267 defm : fp_cond_alias<"g", 0b0110>;
268 defm : fp_cond_alias<"ug", 0b0101>;
269 defm : fp_cond_alias<"l", 0b0100>;
270 defm : fp_cond_alias<"ul", 0b0011>;
271 defm : fp_cond_alias<"lg", 0b0010>;
272 defm : fp_cond_alias<"ne", 0b0001>;
273 defm : fp_cond_alias<"e", 0b1001>;
274 defm : fp_cond_alias<"ue", 0b1010>;
275 defm : fp_cond_alias<"ge", 0b1011>;
276 defm : fp_cond_alias<"uge", 0b1100>;
277 defm : fp_cond_alias<"le", 0b1101>;
278 defm : fp_cond_alias<"ule", 0b1110>;
279 defm : fp_cond_alias<"o", 0b1111>;
281 // Instruction aliases for JMPL.
283 // jmp addr -> jmpl addr, %g0
284 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
285 def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
287 // call addr -> jmpl addr, %o7
288 def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
289 def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
292 def : InstAlias<"retl", (RETL 8)>;
295 def : InstAlias<"ret", (RET 8)>;
297 // mov reg, rd -> or %g0, reg, rd
298 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
300 // mov simm13, rd -> or %g0, simm13, rd
301 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
303 // restore -> restore %g0, %g0, %g0
304 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
306 def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
308 def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
309 def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
311 def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
312 def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
315 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
316 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
317 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
318 Requires<[HasHardQuad]>;
320 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
321 def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
323 def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
325 Requires<[HasHardQuad]>;