1 //===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction aliases for Sparc.
11 //===----------------------------------------------------------------------===//
13 // Instruction aliases for conditional moves.
15 // mov<cond> <ccreg> rs2, rd
16 multiclass cond_mov_alias<string cond, int condVal, string ccreg,
17 Instruction movrr, Instruction movri,
18 Instruction fmovs, Instruction fmovd> {
20 // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
21 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25 // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
26 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30 // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
31 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
35 // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
36 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
38 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
42 // Instruction aliases for integer conditional branches and moves.
43 multiclass int_cond_alias<string cond, int condVal> {
46 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
47 (BCOND brtarget:$imm, condVal)>;
50 def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
51 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
53 defm : cond_mov_alias<cond, condVal, " %icc",
55 FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
57 defm : cond_mov_alias<cond, condVal, " %xcc",
59 FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
61 // fmovq<cond> (%icc|%xcc), $rs2, $rd
62 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
63 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
64 Requires<[HasV9, HasHardQuad]>;
65 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
66 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
67 Requires<[Is64Bit, HasHardQuad]>;
72 // Instruction aliases for floating point conditional branches and moves.
73 multiclass fp_cond_alias<string cond, int condVal> {
76 def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
77 (FBCOND brtarget:$imm, condVal), 0>;
79 defm : cond_mov_alias<cond, condVal, " %fcc0",
81 FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
83 // fmovq<cond> %fcc0, $rs2, $rd
84 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
85 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
86 Requires<[HasV9, HasHardQuad]>;
89 defm : int_cond_alias<"a", 0b1000>;
90 defm : int_cond_alias<"n", 0b0000>;
91 defm : int_cond_alias<"ne", 0b1001>;
92 defm : int_cond_alias<"e", 0b0001>;
93 defm : int_cond_alias<"g", 0b1010>;
94 defm : int_cond_alias<"le", 0b0010>;
95 defm : int_cond_alias<"ge", 0b1011>;
96 defm : int_cond_alias<"l", 0b0011>;
97 defm : int_cond_alias<"gu", 0b1100>;
98 defm : int_cond_alias<"leu", 0b0100>;
99 defm : int_cond_alias<"cc", 0b1101>;
100 defm : int_cond_alias<"cs", 0b0101>;
101 defm : int_cond_alias<"pos", 0b1110>;
102 defm : int_cond_alias<"neg", 0b0110>;
103 defm : int_cond_alias<"vc", 0b1111>;
104 defm : int_cond_alias<"vs", 0b0111>;
106 defm : fp_cond_alias<"u", 0b0111>;
107 defm : fp_cond_alias<"g", 0b0110>;
108 defm : fp_cond_alias<"ug", 0b0101>;
109 defm : fp_cond_alias<"l", 0b0100>;
110 defm : fp_cond_alias<"ul", 0b0011>;
111 defm : fp_cond_alias<"lg", 0b0010>;
112 defm : fp_cond_alias<"ne", 0b0001>;
113 defm : fp_cond_alias<"e", 0b1001>;
114 defm : fp_cond_alias<"ue", 0b1010>;
115 defm : fp_cond_alias<"ge", 0b1011>;
116 defm : fp_cond_alias<"uge", 0b1100>;
117 defm : fp_cond_alias<"le", 0b1101>;
118 defm : fp_cond_alias<"ule", 0b1110>;
119 defm : fp_cond_alias<"o", 0b1111>;
122 // Instruction aliases for JMPL.
124 // jmp addr -> jmpl addr, %g0
125 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>;
126 def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>;
128 // call addr -> jmpl addr, %o7
129 def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>;
130 def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>;
133 def : InstAlias<"retl", (RETL 8)>;
136 def : InstAlias<"ret", (RET 8)>;
138 // mov reg, rd -> or %g0, reg, rd
139 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
141 // mov simm13, rd -> or %g0, simm13, rd
142 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
144 // restore -> restore %g0, %g0, %g0
145 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;