1 //===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction aliases for Sparc.
11 //===----------------------------------------------------------------------===//
13 // Instruction aliases for conditional moves.
15 // mov<cond> <ccreg> rs2, rd
16 multiclass cond_mov_alias<string cond, int condVal, string ccreg,
17 Instruction movrr, Instruction movri,
18 Instruction fmovs, Instruction fmovd> {
20 // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
21 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25 // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
26 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30 // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
31 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
35 // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
36 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
38 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
42 // Instruction aliases for integer conditional branches and moves.
43 multiclass int_cond_alias<string cond, int condVal> {
46 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
47 (BCOND brtarget:$imm, condVal)>;
50 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
51 (BCONDA brtarget:$imm, condVal)>;
54 def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
55 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
57 defm : cond_mov_alias<cond, condVal, " %icc",
59 FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
61 defm : cond_mov_alias<cond, condVal, " %xcc",
63 FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
65 // fmovq<cond> (%icc|%xcc), $rs2, $rd
66 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
67 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
68 Requires<[HasV9, HasHardQuad]>;
69 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
70 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
71 Requires<[Is64Bit, HasHardQuad]>;
76 // Instruction aliases for floating point conditional branches and moves.
77 multiclass fp_cond_alias<string cond, int condVal> {
80 def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
81 (FBCOND brtarget:$imm, condVal), 0>;
84 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
85 (FBCONDA brtarget:$imm, condVal), 0>;
87 defm : cond_mov_alias<cond, condVal, " %fcc0",
89 FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
91 // fmovq<cond> %fcc0, $rs2, $rd
92 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
93 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
94 Requires<[HasV9, HasHardQuad]>;
97 defm : int_cond_alias<"a", 0b1000>;
98 defm : int_cond_alias<"n", 0b0000>;
99 defm : int_cond_alias<"ne", 0b1001>;
100 defm : int_cond_alias<"e", 0b0001>;
101 defm : int_cond_alias<"g", 0b1010>;
102 defm : int_cond_alias<"le", 0b0010>;
103 defm : int_cond_alias<"ge", 0b1011>;
104 defm : int_cond_alias<"l", 0b0011>;
105 defm : int_cond_alias<"gu", 0b1100>;
106 defm : int_cond_alias<"leu", 0b0100>;
107 defm : int_cond_alias<"cc", 0b1101>;
108 defm : int_cond_alias<"cs", 0b0101>;
109 defm : int_cond_alias<"pos", 0b1110>;
110 defm : int_cond_alias<"neg", 0b0110>;
111 defm : int_cond_alias<"vc", 0b1111>;
112 defm : int_cond_alias<"vs", 0b0111>;
114 defm : fp_cond_alias<"u", 0b0111>;
115 defm : fp_cond_alias<"g", 0b0110>;
116 defm : fp_cond_alias<"ug", 0b0101>;
117 defm : fp_cond_alias<"l", 0b0100>;
118 defm : fp_cond_alias<"ul", 0b0011>;
119 defm : fp_cond_alias<"lg", 0b0010>;
120 defm : fp_cond_alias<"ne", 0b0001>;
121 defm : fp_cond_alias<"e", 0b1001>;
122 defm : fp_cond_alias<"ue", 0b1010>;
123 defm : fp_cond_alias<"ge", 0b1011>;
124 defm : fp_cond_alias<"uge", 0b1100>;
125 defm : fp_cond_alias<"le", 0b1101>;
126 defm : fp_cond_alias<"ule", 0b1110>;
127 defm : fp_cond_alias<"o", 0b1111>;
130 // Instruction aliases for JMPL.
132 // jmp addr -> jmpl addr, %g0
133 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>;
134 def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>;
136 // call addr -> jmpl addr, %o7
137 def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>;
138 def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>;
141 def : InstAlias<"retl", (RETL 8)>;
144 def : InstAlias<"ret", (RET 8)>;
146 // mov reg, rd -> or %g0, reg, rd
147 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
149 // mov simm13, rd -> or %g0, simm13, rd
150 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
152 // restore -> restore %g0, %g0, %g0
153 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
155 def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
156 def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
158 def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
159 def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;