1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
18 let Inst{31-30} = op; // Top two bits are the 'op' field
20 dag OutOperandList = outs;
21 dag InOperandList = ins;
22 let AsmString = asmstr;
23 let Pattern = pattern;
25 let DecoderNamespace = "Sparc";
26 field bits<32> SoftFail = 0;
29 //===----------------------------------------------------------------------===//
30 // Format #2 instruction classes in the Sparc
31 //===----------------------------------------------------------------------===//
33 // Format 2 instructions
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
39 let Inst{24-22} = op2;
40 let Inst{21-0} = imm22;
43 // Specific F2 classes: SparcV8 manual, page 44
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
60 let Inst{28-25} = cond;
63 class F2_3<bits<3> op2Val, bit annul, bit pred,
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : InstSP<outs, ins, asmstr, pattern> {
73 let Inst{28-25} = cond;
74 let Inst{24-22} = op2Val;
77 let Inst{18-0} = imm19;
80 class F2_4<bits<3> cond, bit annul, bit pred,
81 dag outs, dag ins, string asmstr, list<dag> pattern>
82 : InstSP<outs, ins, asmstr, pattern> {
90 let Inst{27-25} = cond;
91 let Inst{24-22} = 0b011;
92 let Inst{21-20} = imm16{15-14};
94 let Inst{18-14} = rs1;
95 let Inst{13-0} = imm16{13-0};
99 //===----------------------------------------------------------------------===//
100 // Format #3 instruction classes in the Sparc
101 //===----------------------------------------------------------------------===//
103 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
104 : InstSP<outs, ins, asmstr, pattern> {
108 let op{1} = 1; // Op = 2 or 3
109 let Inst{29-25} = rd;
110 let Inst{24-19} = op3;
111 let Inst{18-14} = rs1;
114 // Specific F3 classes: SparcV8 manual, page 44
116 class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
117 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
123 let Inst{13} = 0; // i field = 0
124 let Inst{12-5} = asi; // address space identifier
128 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
129 list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
132 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
133 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
139 let Inst{13} = 1; // i field = 1
140 let Inst{12-0} = simm13;
144 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
145 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
151 let Inst{13-5} = opfval; // fp opcode
155 // floating-point unary operations.
156 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
157 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
164 let Inst{13-5} = opfval; // fp opcode
168 // floating-point compares.
169 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
170 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
176 let Inst{13-5} = opfval; // fp opcode
180 // Shift by register rs2.
181 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
182 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
183 bit x = xVal; // 1 for 64-bit shifts.
189 let Inst{13} = 0; // i field = 0
190 let Inst{12} = x; // extended registers.
194 // Shift by immediate.
195 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
196 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
197 bit x = xVal; // 1 for 64-bit shifts.
198 bits<6> shcnt; // shcnt32 / shcnt64.
203 let Inst{13} = 1; // i field = 1
204 let Inst{12} = x; // extended registers.
205 let Inst{5-0} = shcnt;
208 // Define rr and ri shift instructions with patterns.
209 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
210 ValueType VT, RegisterClass RC> {
211 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
212 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
213 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
214 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
215 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
216 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
219 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
220 : InstSP<outs, ins, asmstr, pattern> {
224 let Inst{29-25} = rd;
225 let Inst{24-19} = op3;
229 class F4_1<bits<6> op3, dag outs, dag ins,
230 string asmstr, list<dag> pattern>
231 : F4<op3, outs, ins, asmstr, pattern> {
239 let Inst{12-11} = cc;
241 let Inst{17-14} = cond;
242 let Inst{18} = intcc;
246 class F4_2<bits<6> op3, dag outs, dag ins,
247 string asmstr, list<dag> pattern>
248 : F4<op3, outs, ins, asmstr, pattern> {
254 let Inst{10-0} = simm11;
255 let Inst{12-11} = cc;
257 let Inst{17-14} = cond;
258 let Inst{18} = intcc;
261 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
262 string asmstr, list<dag> pattern>
263 : F4<op3, outs, ins, asmstr, pattern> {
270 let Inst{17-14} = cond;
271 let Inst{13} = intcc;
272 let Inst{12-11} = opf_cc;
273 let Inst{10-5} = opf_low;
277 class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
278 string asmstr, list<dag> pattern>
279 : F4<op3, outs, ins, asmstr, pattern> {
282 let Inst{18-14} = rs1;
283 let Inst{13} = 0; // IsImm
284 let Inst{12-10} = rcond;
285 let Inst{9-5} = opf_low;
290 class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
291 string asmstr, list<dag> pattern>
292 : F4<op3, outs, ins, asmstr, pattern> {
295 let Inst{18-14} = rs1;
296 let Inst{13} = 1; // IsImm
297 let Inst{12-10} = rcond;
298 let Inst{9-0} = simm10;
302 class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr,
303 list<dag> pattern>: F3<outs, ins, asmstr, pattern> {
312 let Inst{13} = isimm;
313 let Inst{12-11} = cc;
317 class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr,
318 list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> {
324 class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr,
325 list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> {