1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
17 let Inst{31-30} = op; // Top two bits are the 'op' field
19 dag OutOperandList = outs;
20 dag InOperandList = ins;
21 let AsmString = asmstr;
22 let Pattern = pattern;
25 //===----------------------------------------------------------------------===//
26 // Format #2 instruction classes in the Sparc
27 //===----------------------------------------------------------------------===//
29 // Format 2 instructions
30 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
31 : InstSP<outs, ins, asmstr, pattern> {
35 let Inst{24-22} = op2;
36 let Inst{21-0} = imm22;
39 // Specific F2 classes: SparcV8 manual, page 44
41 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
42 : F2<outs, ins, asmstr, pattern> {
50 class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
51 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
53 bit annul = 0; // currently unused
59 let Inst{28-25} = cond;
62 //===----------------------------------------------------------------------===//
63 // Format #3 instruction classes in the Sparc
64 //===----------------------------------------------------------------------===//
66 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
67 : InstSP<outs, ins, asmstr, pattern> {
71 let op{1} = 1; // Op = 2 or 3
73 let Inst{24-19} = op3;
74 let Inst{18-14} = rs1;
77 // Specific F3 classes: SparcV8 manual, page 44
79 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
80 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
81 bits<8> asi = 0; // asi not currently used
87 let Inst{13} = 0; // i field = 0
88 let Inst{12-5} = asi; // address space identifier
92 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
93 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
99 let Inst{13} = 1; // i field = 1
100 let Inst{12-0} = simm13;
104 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
105 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
111 let Inst{13-5} = opfval; // fp opcode
115 // Shift by register rs2.
116 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
117 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
118 bit x = xVal; // 1 for 64-bit shifts.
124 let Inst{13} = 0; // i field = 0
125 let Inst{12} = x; // extended registers.
129 // Shift by immediate.
130 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
131 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
132 bit x = xVal; // 1 for 64-bit shifts.
133 bits<6> shcnt; // shcnt32 / shcnt64.
138 let Inst{13} = 1; // i field = 1
139 let Inst{12} = x; // extended registers.
140 let Inst{5-0} = shcnt;
143 // Define rr and ri shift instructions with patterns.
144 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
145 ValueType VT, RegisterClass RC> {
146 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
147 !strconcat(OpcStr, " $rs, $rs2, $rd"),
148 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
149 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
150 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
151 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;