1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
18 let Inst{31-30} = op; // Top two bits are the 'op' field
20 dag OutOperandList = outs;
21 dag InOperandList = ins;
22 let AsmString = asmstr;
23 let Pattern = pattern;
25 let DecoderNamespace = "Sparc";
26 field bits<32> SoftFail = 0;
29 //===----------------------------------------------------------------------===//
30 // Format #2 instruction classes in the Sparc
31 //===----------------------------------------------------------------------===//
33 // Format 2 instructions
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
39 let Inst{24-22} = op2;
40 let Inst{21-0} = imm22;
43 // Specific F2 classes: SparcV8 manual, page 44
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
60 let Inst{28-25} = cond;
63 class F2_3<bits<3> op2Val, bit annul, bit pred,
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : InstSP<outs, ins, asmstr, pattern> {
73 let Inst{28-25} = cond;
74 let Inst{24-22} = op2Val;
77 let Inst{18-0} = imm19;
80 class F2_4<bits<3> cond, bit annul, bit pred,
81 dag outs, dag ins, string asmstr, list<dag> pattern>
82 : InstSP<outs, ins, asmstr, pattern> {
90 let Inst{27-25} = cond;
91 let Inst{24-22} = 0b011;
92 let Inst{21-20} = imm16{15-14};
94 let Inst{18-14} = rs1;
95 let Inst{13-0} = imm16{13-0};
99 //===----------------------------------------------------------------------===//
100 // Format #3 instruction classes in the Sparc
101 //===----------------------------------------------------------------------===//
103 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
104 : InstSP<outs, ins, asmstr, pattern> {
108 let op{1} = 1; // Op = 2 or 3
109 let Inst{29-25} = rd;
110 let Inst{24-19} = op3;
111 let Inst{18-14} = rs1;
114 // Specific F3 classes: SparcV8 manual, page 44
116 class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
117 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
124 let Inst{13} = 0; // i field = 0
125 let Inst{12-5} = asi; // address space identifier
129 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
130 list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins,
135 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
136 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
142 let Inst{13} = 1; // i field = 1
143 let Inst{12-0} = simm13;
147 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
148 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
154 let Inst{13-5} = opfval; // fp opcode
158 // floating-point unary operations.
159 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
160 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
167 let Inst{13-5} = opfval; // fp opcode
171 // floating-point compares.
172 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
173 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
179 let Inst{13-5} = opfval; // fp opcode
183 // Shift by register rs2.
184 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
185 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
186 bit x = xVal; // 1 for 64-bit shifts.
192 let Inst{13} = 0; // i field = 0
193 let Inst{12} = x; // extended registers.
197 // Shift by immediate.
198 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
199 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
200 bit x = xVal; // 1 for 64-bit shifts.
201 bits<6> shcnt; // shcnt32 / shcnt64.
206 let Inst{13} = 1; // i field = 1
207 let Inst{12} = x; // extended registers.
208 let Inst{5-0} = shcnt;
211 // Define rr and ri shift instructions with patterns.
212 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
213 ValueType VT, RegisterClass RC> {
214 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
215 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
216 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
217 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
218 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
219 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
222 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
223 : InstSP<outs, ins, asmstr, pattern> {
227 let Inst{29-25} = rd;
228 let Inst{24-19} = op3;
232 class F4_1<bits<6> op3, dag outs, dag ins,
233 string asmstr, list<dag> pattern>
234 : F4<op3, outs, ins, asmstr, pattern> {
242 let Inst{12-11} = cc;
244 let Inst{17-14} = cond;
245 let Inst{18} = intcc;
249 class F4_2<bits<6> op3, dag outs, dag ins,
250 string asmstr, list<dag> pattern>
251 : F4<op3, outs, ins, asmstr, pattern> {
257 let Inst{10-0} = simm11;
258 let Inst{12-11} = cc;
260 let Inst{17-14} = cond;
261 let Inst{18} = intcc;
264 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
265 string asmstr, list<dag> pattern>
266 : F4<op3, outs, ins, asmstr, pattern> {
273 let Inst{17-14} = cond;
274 let Inst{13} = intcc;
275 let Inst{12-11} = opf_cc;
276 let Inst{10-5} = opf_low;
280 class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
281 string asmstr, list<dag> pattern>
282 : F4<op3, outs, ins, asmstr, pattern> {
285 let Inst{18-14} = rs1;
286 let Inst{13} = 0; // IsImm
287 let Inst{12-10} = rcond;
288 let Inst{9-5} = opf_low;
293 class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
294 string asmstr, list<dag> pattern>
295 : F4<op3, outs, ins, asmstr, pattern> {
298 let Inst{18-14} = rs1;
299 let Inst{13} = 1; // IsImm
300 let Inst{12-10} = rcond;
301 let Inst{9-0} = simm10;
305 class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr,
306 list<dag> pattern>: F3<outs, ins, asmstr, pattern> {
315 let Inst{13} = isimm;
316 let Inst{12-11} = cc;
320 class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr,
321 list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> {
327 class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr,
328 list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> {
335 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
336 // These are aliases that require C++ handling to convert to the target
337 // instruction, while InstAliases can be handled directly by tblgen.
338 class AsmPseudoInst<dag outs, dag ins, string asm>
339 : InstSP<outs, ins, asm, []> {