1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
18 let Inst{31-30} = op; // Top two bits are the 'op' field
20 dag OutOperandList = outs;
21 dag InOperandList = ins;
22 let AsmString = asmstr;
23 let Pattern = pattern;
25 let DecoderNamespace = "Sparc";
26 field bits<32> SoftFail = 0;
29 //===----------------------------------------------------------------------===//
30 // Format #2 instruction classes in the Sparc
31 //===----------------------------------------------------------------------===//
33 // Format 2 instructions
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
39 let Inst{24-22} = op2;
40 let Inst{21-0} = imm22;
43 // Specific F2 classes: SparcV8 manual, page 44
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
57 bit annul = 0; // currently unused
62 let Inst{28-25} = cond;
65 class F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr,
67 : InstSP<outs, ins, asmstr, pattern> {
75 bit annul = 0; // currently unused
76 let pred = 1; // default is predict taken
79 let Inst{28-25} = cond;
80 let Inst{24-22} = op2Val;
81 let Inst{21-20} = ccVal;
83 let Inst{18-0} = imm19;
86 //===----------------------------------------------------------------------===//
87 // Format #3 instruction classes in the Sparc
88 //===----------------------------------------------------------------------===//
90 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
91 : InstSP<outs, ins, asmstr, pattern> {
95 let op{1} = 1; // Op = 2 or 3
97 let Inst{24-19} = op3;
98 let Inst{18-14} = rs1;
101 // Specific F3 classes: SparcV8 manual, page 44
103 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
104 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
105 bits<8> asi = 0; // asi not currently used
111 let Inst{13} = 0; // i field = 0
112 let Inst{12-5} = asi; // address space identifier
116 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
117 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
123 let Inst{13} = 1; // i field = 1
124 let Inst{12-0} = simm13;
128 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
129 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
135 let Inst{13-5} = opfval; // fp opcode
139 // floating-point unary operations.
140 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
141 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
148 let Inst{13-5} = opfval; // fp opcode
152 // floating-point compares.
153 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
154 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
161 let Inst{13-5} = opfval; // fp opcode
165 // Shift by register rs2.
166 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
167 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
168 bit x = xVal; // 1 for 64-bit shifts.
174 let Inst{13} = 0; // i field = 0
175 let Inst{12} = x; // extended registers.
179 // Shift by immediate.
180 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
181 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
182 bit x = xVal; // 1 for 64-bit shifts.
183 bits<6> shcnt; // shcnt32 / shcnt64.
188 let Inst{13} = 1; // i field = 1
189 let Inst{12} = x; // extended registers.
190 let Inst{5-0} = shcnt;
193 // Define rr and ri shift instructions with patterns.
194 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
195 ValueType VT, RegisterClass RC> {
196 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
197 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
198 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
199 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
200 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
201 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
204 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
205 : InstSP<outs, ins, asmstr, pattern> {
209 let Inst{29-25} = rd;
210 let Inst{24-19} = op3;
214 class F4_1<bits<6> op3, dag outs, dag ins,
215 string asmstr, list<dag> pattern>
216 : F4<op3, outs, ins, asmstr, pattern> {
223 let Inst{11} = cc{0};
224 let Inst{12} = cc{1};
226 let Inst{17-14} = cond;
227 let Inst{18} = cc{2};
231 class F4_2<bits<6> op3, dag outs, dag ins,
232 string asmstr, list<dag> pattern>
233 : F4<op3, outs, ins, asmstr, pattern> {
238 let Inst{10-0} = simm11;
239 let Inst{11} = cc{0};
240 let Inst{12} = cc{1};
242 let Inst{17-14} = cond;
243 let Inst{18} = cc{2};
246 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
247 string asmstr, list<dag> pattern>
248 : F4<op3, outs, ins, asmstr, pattern> {
254 let Inst{17-14} = cond;
255 let Inst{13-11} = opf_cc;
256 let Inst{10-5} = opf_low;