1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
16 let Inst{31-30} = op; // Top two bits are the 'op' field
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
20 let AsmString = asmstr;
21 let Pattern = pattern;
24 //===----------------------------------------------------------------------===//
25 // Format #2 instruction classes in the Sparc
26 //===----------------------------------------------------------------------===//
28 // Format 2 instructions
29 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
30 : InstSP<outs, ins, asmstr, pattern> {
34 let Inst{24-22} = op2;
35 let Inst{21-0} = imm22;
38 // Specific F2 classes: SparcV8 manual, page 44
40 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
41 : F2<outs, ins, asmstr, pattern> {
49 class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
50 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
52 bit annul = 0; // currently unused
58 let Inst{28-25} = cond;
61 //===----------------------------------------------------------------------===//
62 // Format #3 instruction classes in the Sparc
63 //===----------------------------------------------------------------------===//
65 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
66 : InstSP<outs, ins, asmstr, pattern> {
70 let op{1} = 1; // Op = 2 or 3
72 let Inst{24-19} = op3;
73 let Inst{18-14} = rs1;
76 // Specific F3 classes: SparcV8 manual, page 44
78 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
79 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
80 bits<8> asi = 0; // asi not currently used
86 let Inst{13} = 0; // i field = 0
87 let Inst{12-5} = asi; // address space identifier
91 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
92 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
98 let Inst{13} = 1; // i field = 1
99 let Inst{12-0} = simm13;
103 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
104 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
110 let Inst{13-5} = opfval; // fp opcode
114 // Shift by register rs2.
115 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
116 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
117 bit x = xVal; // 1 for 64-bit shifts.
123 let Inst{13} = 0; // i field = 0
124 let Inst{12} = x; // extended registers.
128 // Shift by immediate.
129 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
130 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
131 bit x = xVal; // 1 for 64-bit shifts.
132 bits<6> shcnt; // shcnt32 / shcnt64.
137 let Inst{13} = 1; // i field = 1
138 let Inst{12} = x; // extended registers.
139 let Inst{5-0} = shcnt;
142 // Define rr and ri shift instructions with patterns.
143 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
144 ValueType VT, RegisterClass RC> {
145 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
146 !strconcat(OpcStr, " $rs, $rs2, $rd"),
147 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
148 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
149 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
150 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;