1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
15 #include "SparcSubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "SparcGenInstrInfo.inc"
23 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
24 : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
25 RI(ST, *this), Subtarget(ST) {
28 static bool isZeroImm(const MachineOperand &op) {
29 return op.isImm() && op.getImm() == 0;
32 /// Return true if the instruction is a register to register move and
33 /// leave the source and dest operands in the passed parameters.
35 bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
36 unsigned &SrcReg, unsigned &DstReg) const {
37 // We look for 3 kinds of patterns here:
40 // fmovs or FpMOVD (pseudo double move).
41 if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
42 if (MI.getOperand(1).getReg() == SP::G0) {
43 DstReg = MI.getOperand(0).getReg();
44 SrcReg = MI.getOperand(2).getReg();
46 } else if (MI.getOperand(2).getReg() == SP::G0) {
47 DstReg = MI.getOperand(0).getReg();
48 SrcReg = MI.getOperand(1).getReg();
51 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
52 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
53 DstReg = MI.getOperand(0).getReg();
54 SrcReg = MI.getOperand(1).getReg();
56 } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
57 MI.getOpcode() == SP::FMOVD) {
58 SrcReg = MI.getOperand(1).getReg();
59 DstReg = MI.getOperand(0).getReg();
65 /// isLoadFromStackSlot - If the specified machine instruction is a direct
66 /// load from a stack slot, return the virtual or physical register number of
67 /// the destination along with the FrameIndex of the loaded stack slot. If
68 /// not, return 0. This predicate must return 0 if the instruction has
69 /// any side effects other than loading from the stack slot.
70 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
71 int &FrameIndex) const {
72 if (MI->getOpcode() == SP::LDri ||
73 MI->getOpcode() == SP::LDFri ||
74 MI->getOpcode() == SP::LDDFri) {
75 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
76 MI->getOperand(2).getImm() == 0) {
77 FrameIndex = MI->getOperand(1).getIndex();
78 return MI->getOperand(0).getReg();
84 /// isStoreToStackSlot - If the specified machine instruction is a direct
85 /// store to a stack slot, return the virtual or physical register number of
86 /// the source reg along with the FrameIndex of the loaded stack slot. If
87 /// not, return 0. This predicate must return 0 if the instruction has
88 /// any side effects other than storing to the stack slot.
89 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
90 int &FrameIndex) const {
91 if (MI->getOpcode() == SP::STri ||
92 MI->getOpcode() == SP::STFri ||
93 MI->getOpcode() == SP::STDFri) {
94 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
95 MI->getOperand(1).getImm() == 0) {
96 FrameIndex = MI->getOperand(0).getIndex();
97 return MI->getOperand(2).getReg();
104 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
105 MachineBasicBlock *FBB,
106 const SmallVectorImpl<MachineOperand> &Cond)const{
107 // Can only insert uncond branches so far.
108 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
109 BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
113 bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator I,
115 unsigned DestReg, unsigned SrcReg,
116 const TargetRegisterClass *DestRC,
117 const TargetRegisterClass *SrcRC) const {
118 if (DestRC != SrcRC) {
119 // Not yet supported!
123 if (DestRC == SP::IntRegsRegisterClass)
124 BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
125 else if (DestRC == SP::FPRegsRegisterClass)
126 BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg);
127 else if (DestRC == SP::DFPRegsRegisterClass)
128 BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
131 // Can't copy this register
137 void SparcInstrInfo::
138 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
139 unsigned SrcReg, bool isKill, int FI,
140 const TargetRegisterClass *RC) const {
141 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
142 if (RC == SP::IntRegsRegisterClass)
143 BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0)
144 .addReg(SrcReg, false, false, isKill);
145 else if (RC == SP::FPRegsRegisterClass)
146 BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0)
147 .addReg(SrcReg, false, false, isKill);
148 else if (RC == SP::DFPRegsRegisterClass)
149 BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
150 .addReg(SrcReg, false, false, isKill);
152 assert(0 && "Can't store this register to stack slot");
155 void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
157 SmallVectorImpl<MachineOperand> &Addr,
158 const TargetRegisterClass *RC,
159 SmallVectorImpl<MachineInstr*> &NewMIs) const {
161 if (RC == SP::IntRegsRegisterClass)
163 else if (RC == SP::FPRegsRegisterClass)
165 else if (RC == SP::DFPRegsRegisterClass)
168 assert(0 && "Can't load this register");
169 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
170 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
171 MachineOperand &MO = Addr[i];
173 MIB.addReg(MO.getReg());
175 MIB.addImm(MO.getImm());
178 MIB.addFrameIndex(MO.getIndex());
181 MIB.addReg(SrcReg, false, false, isKill);
182 NewMIs.push_back(MIB);
186 void SparcInstrInfo::
187 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
188 unsigned DestReg, int FI,
189 const TargetRegisterClass *RC) const {
190 if (RC == SP::IntRegsRegisterClass)
191 BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
192 else if (RC == SP::FPRegsRegisterClass)
193 BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
194 else if (RC == SP::DFPRegsRegisterClass)
195 BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
197 assert(0 && "Can't load this register from stack slot");
200 void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
201 SmallVectorImpl<MachineOperand> &Addr,
202 const TargetRegisterClass *RC,
203 SmallVectorImpl<MachineInstr*> &NewMIs) const {
205 if (RC == SP::IntRegsRegisterClass)
207 else if (RC == SP::FPRegsRegisterClass)
209 else if (RC == SP::DFPRegsRegisterClass)
212 assert(0 && "Can't load this register");
213 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
214 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
215 MachineOperand &MO = Addr[i];
217 MIB.addReg(MO.getReg());
219 MIB.addImm(MO.getImm());
222 MIB.addFrameIndex(MO.getIndex());
225 NewMIs.push_back(MIB);
229 MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
231 const SmallVectorImpl<unsigned> &Ops,
233 if (Ops.size() != 1) return NULL;
235 unsigned OpNum = Ops[0];
236 bool isFloat = false;
237 MachineInstr *NewMI = NULL;
238 switch (MI->getOpcode()) {
240 if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
241 MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
242 if (OpNum == 0) // COPY -> STORE
243 NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
244 .addReg(MI->getOperand(2).getReg());
246 NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg())
247 .addFrameIndex(FI).addImm(0);
254 if (OpNum == 0) { // COPY -> STORE
255 unsigned SrcReg = MI->getOperand(1).getReg();
256 bool isKill = MI->getOperand(1).isKill();
257 NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri))
258 .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
259 } else { // COPY -> LOAD
260 unsigned DstReg = MI->getOperand(0).getReg();
261 bool isDead = MI->getOperand(0).isDead();
262 NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri))
263 .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);