1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
25 #define GET_INSTRINFO_CTOR
26 #include "SparcGenInstrInfo.inc"
30 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
31 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
32 RI(ST, *this), Subtarget(ST) {
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
41 int &FrameIndex) const {
42 if (MI->getOpcode() == SP::LDri ||
43 MI->getOpcode() == SP::LDXri ||
44 MI->getOpcode() == SP::LDFri ||
45 MI->getOpcode() == SP::LDDFri) {
46 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
47 MI->getOperand(2).getImm() == 0) {
48 FrameIndex = MI->getOperand(1).getIndex();
49 return MI->getOperand(0).getReg();
55 /// isStoreToStackSlot - If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
60 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
61 int &FrameIndex) const {
62 if (MI->getOpcode() == SP::STri ||
63 MI->getOpcode() == SP::STXri ||
64 MI->getOpcode() == SP::STFri ||
65 MI->getOpcode() == SP::STDFri) {
66 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
67 MI->getOperand(1).getImm() == 0) {
68 FrameIndex = MI->getOperand(0).getIndex();
69 return MI->getOperand(2).getReg();
75 static bool IsIntegerCC(unsigned CC)
77 return (CC <= SPCC::ICC_VC);
81 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
84 case SPCC::ICC_NE: return SPCC::ICC_E;
85 case SPCC::ICC_E: return SPCC::ICC_NE;
86 case SPCC::ICC_G: return SPCC::ICC_LE;
87 case SPCC::ICC_LE: return SPCC::ICC_G;
88 case SPCC::ICC_GE: return SPCC::ICC_L;
89 case SPCC::ICC_L: return SPCC::ICC_GE;
90 case SPCC::ICC_GU: return SPCC::ICC_LEU;
91 case SPCC::ICC_LEU: return SPCC::ICC_GU;
92 case SPCC::ICC_CC: return SPCC::ICC_CS;
93 case SPCC::ICC_CS: return SPCC::ICC_CC;
94 case SPCC::ICC_POS: return SPCC::ICC_NEG;
95 case SPCC::ICC_NEG: return SPCC::ICC_POS;
96 case SPCC::ICC_VC: return SPCC::ICC_VS;
97 case SPCC::ICC_VS: return SPCC::ICC_VC;
99 case SPCC::FCC_U: return SPCC::FCC_O;
100 case SPCC::FCC_O: return SPCC::FCC_U;
101 case SPCC::FCC_G: return SPCC::FCC_LE;
102 case SPCC::FCC_LE: return SPCC::FCC_G;
103 case SPCC::FCC_UG: return SPCC::FCC_ULE;
104 case SPCC::FCC_ULE: return SPCC::FCC_UG;
105 case SPCC::FCC_L: return SPCC::FCC_GE;
106 case SPCC::FCC_GE: return SPCC::FCC_L;
107 case SPCC::FCC_UL: return SPCC::FCC_UGE;
108 case SPCC::FCC_UGE: return SPCC::FCC_UL;
109 case SPCC::FCC_LG: return SPCC::FCC_UE;
110 case SPCC::FCC_UE: return SPCC::FCC_LG;
111 case SPCC::FCC_NE: return SPCC::FCC_E;
112 case SPCC::FCC_E: return SPCC::FCC_NE;
114 llvm_unreachable("Invalid cond code");
118 SparcInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
123 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
124 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
129 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
130 MachineBasicBlock *&TBB,
131 MachineBasicBlock *&FBB,
132 SmallVectorImpl<MachineOperand> &Cond,
133 bool AllowModify) const
136 MachineBasicBlock::iterator I = MBB.end();
137 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
138 while (I != MBB.begin()) {
141 if (I->isDebugValue())
144 // When we see a non-terminator, we are done.
145 if (!isUnpredicatedTerminator(I))
148 // Terminator is not a branch.
152 // Handle Unconditional branches.
153 if (I->getOpcode() == SP::BA) {
157 TBB = I->getOperand(0).getMBB();
161 while (llvm::next(I) != MBB.end())
162 llvm::next(I)->eraseFromParent();
167 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
169 I->eraseFromParent();
171 UnCondBrIter = MBB.end();
175 TBB = I->getOperand(0).getMBB();
179 unsigned Opcode = I->getOpcode();
180 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
181 return true; // Unknown Opcode.
183 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
186 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
187 if (AllowModify && UnCondBrIter != MBB.end() &&
188 MBB.isLayoutSuccessor(TargetBB)) {
190 // Transform the code
205 BranchCode = GetOppositeBranchCondition(BranchCode);
206 MachineBasicBlock::iterator OldInst = I;
207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
208 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
209 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
212 OldInst->eraseFromParent();
213 UnCondBrIter->eraseFromParent();
215 UnCondBrIter = MBB.end();
220 TBB = I->getOperand(0).getMBB();
221 Cond.push_back(MachineOperand::CreateImm(BranchCode));
224 // FIXME: Handle subsequent conditional branches.
225 // For now, we can't handle multiple conditional branches.
232 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
233 MachineBasicBlock *FBB,
234 const SmallVectorImpl<MachineOperand> &Cond,
236 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
237 assert((Cond.size() == 1 || Cond.size() == 0) &&
238 "Sparc branch conditions should have one component!");
241 assert(!FBB && "Unconditional branch with multiple successors!");
242 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
246 // Conditional branch
247 unsigned CC = Cond[0].getImm();
250 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
252 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
256 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
260 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
262 MachineBasicBlock::iterator I = MBB.end();
264 while (I != MBB.begin()) {
267 if (I->isDebugValue())
270 if (I->getOpcode() != SP::BA
271 && I->getOpcode() != SP::BCOND
272 && I->getOpcode() != SP::FBCOND)
273 break; // Not a branch
275 I->eraseFromParent();
282 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator I, DebugLoc DL,
284 unsigned DestReg, unsigned SrcReg,
285 bool KillSrc) const {
286 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
287 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
288 .addReg(SrcReg, getKillRegState(KillSrc));
289 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
290 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
291 .addReg(SrcReg, getKillRegState(KillSrc));
292 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
293 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
294 .addReg(SrcReg, getKillRegState(KillSrc));
296 llvm_unreachable("Impossible reg-to-reg copy");
299 void SparcInstrInfo::
300 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
301 unsigned SrcReg, bool isKill, int FI,
302 const TargetRegisterClass *RC,
303 const TargetRegisterInfo *TRI) const {
305 if (I != MBB.end()) DL = I->getDebugLoc();
307 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
308 if (RC == &SP::I64RegsRegClass)
309 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
310 .addReg(SrcReg, getKillRegState(isKill));
311 else if (RC == &SP::IntRegsRegClass)
312 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
313 .addReg(SrcReg, getKillRegState(isKill));
314 else if (RC == &SP::FPRegsRegClass)
315 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
316 .addReg(SrcReg, getKillRegState(isKill));
317 else if (RC == &SP::DFPRegsRegClass)
318 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
319 .addReg(SrcReg, getKillRegState(isKill));
321 llvm_unreachable("Can't store this register to stack slot");
324 void SparcInstrInfo::
325 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
326 unsigned DestReg, int FI,
327 const TargetRegisterClass *RC,
328 const TargetRegisterInfo *TRI) const {
330 if (I != MBB.end()) DL = I->getDebugLoc();
332 if (RC == &SP::I64RegsRegClass)
333 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0);
334 else if (RC == &SP::IntRegsRegClass)
335 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
336 else if (RC == &SP::FPRegsRegClass)
337 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
338 else if (RC == &SP::DFPRegsRegClass)
339 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
341 llvm_unreachable("Can't load this register from stack slot");
344 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
346 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
347 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
348 if (GlobalBaseReg != 0)
349 return GlobalBaseReg;
351 // Insert the set of GlobalBaseReg into the first MBB of the function
352 MachineBasicBlock &FirstMBB = MF->front();
353 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
354 MachineRegisterInfo &RegInfo = MF->getRegInfo();
356 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
361 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
362 SparcFI->setGlobalBaseReg(GlobalBaseReg);
363 return GlobalBaseReg;