1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
15 #include "SparcSubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "SparcGenInstrInfo.inc"
23 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
24 : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
25 RI(ST, *this), Subtarget(ST) {
28 static bool isZeroImm(const MachineOperand &op) {
29 return op.isImm() && op.getImm() == 0;
32 /// Return true if the instruction is a register to register move and
33 /// leave the source and dest operands in the passed parameters.
35 bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
36 unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSR, unsigned &DstSR) const {
38 SrcSR = DstSR = 0; // No sub-registers.
40 // We look for 3 kinds of patterns here:
43 // fmovs or FpMOVD (pseudo double move).
44 if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
45 if (MI.getOperand(1).getReg() == SP::G0) {
46 DstReg = MI.getOperand(0).getReg();
47 SrcReg = MI.getOperand(2).getReg();
49 } else if (MI.getOperand(2).getReg() == SP::G0) {
50 DstReg = MI.getOperand(0).getReg();
51 SrcReg = MI.getOperand(1).getReg();
54 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
55 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
56 DstReg = MI.getOperand(0).getReg();
57 SrcReg = MI.getOperand(1).getReg();
59 } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
60 MI.getOpcode() == SP::FMOVD) {
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
75 if (MI->getOpcode() == SP::LDri ||
76 MI->getOpcode() == SP::LDFri ||
77 MI->getOpcode() == SP::LDDFri) {
78 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
79 MI->getOperand(2).getImm() == 0) {
80 FrameIndex = MI->getOperand(1).getIndex();
81 return MI->getOperand(0).getReg();
87 /// isStoreToStackSlot - If the specified machine instruction is a direct
88 /// store to a stack slot, return the virtual or physical register number of
89 /// the source reg along with the FrameIndex of the loaded stack slot. If
90 /// not, return 0. This predicate must return 0 if the instruction has
91 /// any side effects other than storing to the stack slot.
92 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
93 int &FrameIndex) const {
94 if (MI->getOpcode() == SP::STri ||
95 MI->getOpcode() == SP::STFri ||
96 MI->getOpcode() == SP::STDFri) {
97 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
98 MI->getOperand(1).getImm() == 0) {
99 FrameIndex = MI->getOperand(0).getIndex();
100 return MI->getOperand(2).getReg();
107 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
108 MachineBasicBlock *FBB,
109 const SmallVectorImpl<MachineOperand> &Cond)const{
110 // Can only insert uncond branches so far.
111 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
112 BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
116 bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator I,
118 unsigned DestReg, unsigned SrcReg,
119 const TargetRegisterClass *DestRC,
120 const TargetRegisterClass *SrcRC) const {
121 if (DestRC != SrcRC) {
122 // Not yet supported!
126 DebugLoc DL = DebugLoc::getUnknownLoc();
127 if (I != MBB.end()) DL = I->getDebugLoc();
129 if (DestRC == SP::IntRegsRegisterClass)
130 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
131 else if (DestRC == SP::FPRegsRegisterClass)
132 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
133 else if (DestRC == SP::DFPRegsRegisterClass)
134 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
137 // Can't copy this register
143 void SparcInstrInfo::
144 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
145 unsigned SrcReg, bool isKill, int FI,
146 const TargetRegisterClass *RC) const {
147 DebugLoc DL = DebugLoc::getUnknownLoc();
148 if (I != MBB.end()) DL = I->getDebugLoc();
150 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
151 if (RC == SP::IntRegsRegisterClass)
152 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
153 .addReg(SrcReg, false, false, isKill);
154 else if (RC == SP::FPRegsRegisterClass)
155 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
156 .addReg(SrcReg, false, false, isKill);
157 else if (RC == SP::DFPRegsRegisterClass)
158 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
159 .addReg(SrcReg, false, false, isKill);
161 assert(0 && "Can't store this register to stack slot");
164 void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
166 SmallVectorImpl<MachineOperand> &Addr,
167 const TargetRegisterClass *RC,
168 SmallVectorImpl<MachineInstr*> &NewMIs) const {
170 DebugLoc DL = DebugLoc::getUnknownLoc();
171 if (RC == SP::IntRegsRegisterClass)
173 else if (RC == SP::FPRegsRegisterClass)
175 else if (RC == SP::DFPRegsRegisterClass)
178 assert(0 && "Can't load this register");
179 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
180 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
181 MachineOperand &MO = Addr[i];
183 MIB.addReg(MO.getReg());
185 MIB.addImm(MO.getImm());
188 MIB.addFrameIndex(MO.getIndex());
191 MIB.addReg(SrcReg, false, false, isKill);
192 NewMIs.push_back(MIB);
196 void SparcInstrInfo::
197 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
198 unsigned DestReg, int FI,
199 const TargetRegisterClass *RC) const {
200 DebugLoc DL = DebugLoc::getUnknownLoc();
201 if (I != MBB.end()) DL = I->getDebugLoc();
203 if (RC == SP::IntRegsRegisterClass)
204 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
205 else if (RC == SP::FPRegsRegisterClass)
206 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
207 else if (RC == SP::DFPRegsRegisterClass)
208 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
210 assert(0 && "Can't load this register from stack slot");
213 void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
214 SmallVectorImpl<MachineOperand> &Addr,
215 const TargetRegisterClass *RC,
216 SmallVectorImpl<MachineInstr*> &NewMIs) const {
218 if (RC == SP::IntRegsRegisterClass)
220 else if (RC == SP::FPRegsRegisterClass)
222 else if (RC == SP::DFPRegsRegisterClass)
225 assert(0 && "Can't load this register");
226 DebugLoc DL = DebugLoc::getUnknownLoc();
227 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
228 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
229 MachineOperand &MO = Addr[i];
231 MIB.addReg(MO.getReg());
233 MIB.addImm(MO.getImm());
236 MIB.addFrameIndex(MO.getIndex());
239 NewMIs.push_back(MIB);
243 MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
245 const SmallVectorImpl<unsigned> &Ops,
247 if (Ops.size() != 1) return NULL;
249 unsigned OpNum = Ops[0];
250 bool isFloat = false;
251 MachineInstr *NewMI = NULL;
252 switch (MI->getOpcode()) {
254 if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
255 MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
256 if (OpNum == 0) // COPY -> STORE
257 NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
260 .addReg(MI->getOperand(2).getReg());
262 NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
263 MI->getOperand(0).getReg())
272 if (OpNum == 0) { // COPY -> STORE
273 unsigned SrcReg = MI->getOperand(1).getReg();
274 bool isKill = MI->getOperand(1).isKill();
275 NewMI = BuildMI(MF, MI->getDebugLoc(),
276 get(isFloat ? SP::STFri : SP::STDFri))
279 .addReg(SrcReg, false, false, isKill);
280 } else { // COPY -> LOAD
281 unsigned DstReg = MI->getOperand(0).getReg();
282 bool isDead = MI->getOperand(0).isDead();
283 NewMI = BuildMI(MF, MI->getDebugLoc(),
284 get(isFloat ? SP::LDFri : SP::LDDFri))
285 .addReg(DstReg, true, false, false, isDead)