1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
25 #define GET_INSTRINFO_CTOR
26 #include "SparcGenInstrInfo.inc"
30 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
31 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
32 RI(ST, *this), Subtarget(ST) {
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
41 int &FrameIndex) const {
42 if (MI->getOpcode() == SP::LDri ||
43 MI->getOpcode() == SP::LDFri ||
44 MI->getOpcode() == SP::LDDFri) {
45 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
46 MI->getOperand(2).getImm() == 0) {
47 FrameIndex = MI->getOperand(1).getIndex();
48 return MI->getOperand(0).getReg();
54 /// isStoreToStackSlot - If the specified machine instruction is a direct
55 /// store to a stack slot, return the virtual or physical register number of
56 /// the source reg along with the FrameIndex of the loaded stack slot. If
57 /// not, return 0. This predicate must return 0 if the instruction has
58 /// any side effects other than storing to the stack slot.
59 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
60 int &FrameIndex) const {
61 if (MI->getOpcode() == SP::STri ||
62 MI->getOpcode() == SP::STFri ||
63 MI->getOpcode() == SP::STDFri) {
64 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
65 MI->getOperand(1).getImm() == 0) {
66 FrameIndex = MI->getOperand(0).getIndex();
67 return MI->getOperand(2).getReg();
73 static bool IsIntegerCC(unsigned CC)
75 return (CC <= SPCC::ICC_VC);
79 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
82 case SPCC::ICC_NE: return SPCC::ICC_E;
83 case SPCC::ICC_E: return SPCC::ICC_NE;
84 case SPCC::ICC_G: return SPCC::ICC_LE;
85 case SPCC::ICC_LE: return SPCC::ICC_G;
86 case SPCC::ICC_GE: return SPCC::ICC_L;
87 case SPCC::ICC_L: return SPCC::ICC_GE;
88 case SPCC::ICC_GU: return SPCC::ICC_LEU;
89 case SPCC::ICC_LEU: return SPCC::ICC_GU;
90 case SPCC::ICC_CC: return SPCC::ICC_CS;
91 case SPCC::ICC_CS: return SPCC::ICC_CC;
92 case SPCC::ICC_POS: return SPCC::ICC_NEG;
93 case SPCC::ICC_NEG: return SPCC::ICC_POS;
94 case SPCC::ICC_VC: return SPCC::ICC_VS;
95 case SPCC::ICC_VS: return SPCC::ICC_VC;
97 case SPCC::FCC_U: return SPCC::FCC_O;
98 case SPCC::FCC_O: return SPCC::FCC_U;
99 case SPCC::FCC_G: return SPCC::FCC_LE;
100 case SPCC::FCC_LE: return SPCC::FCC_G;
101 case SPCC::FCC_UG: return SPCC::FCC_ULE;
102 case SPCC::FCC_ULE: return SPCC::FCC_UG;
103 case SPCC::FCC_L: return SPCC::FCC_GE;
104 case SPCC::FCC_GE: return SPCC::FCC_L;
105 case SPCC::FCC_UL: return SPCC::FCC_UGE;
106 case SPCC::FCC_UGE: return SPCC::FCC_UL;
107 case SPCC::FCC_LG: return SPCC::FCC_UE;
108 case SPCC::FCC_UE: return SPCC::FCC_LG;
109 case SPCC::FCC_NE: return SPCC::FCC_E;
110 case SPCC::FCC_E: return SPCC::FCC_NE;
115 SparcInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
120 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
121 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
126 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
127 MachineBasicBlock *&TBB,
128 MachineBasicBlock *&FBB,
129 SmallVectorImpl<MachineOperand> &Cond,
130 bool AllowModify) const
133 MachineBasicBlock::iterator I = MBB.end();
134 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
135 while (I != MBB.begin()) {
138 if (I->isDebugValue())
141 //When we see a non-terminator, we are done
142 if (!isUnpredicatedTerminator(I))
145 //Terminator is not a branch
149 //Handle Unconditional branches
150 if (I->getOpcode() == SP::BA) {
154 TBB = I->getOperand(0).getMBB();
158 while (llvm::next(I) != MBB.end())
159 llvm::next(I)->eraseFromParent();
164 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
166 I->eraseFromParent();
168 UnCondBrIter = MBB.end();
172 TBB = I->getOperand(0).getMBB();
176 unsigned Opcode = I->getOpcode();
177 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
178 return true; //Unknown Opcode
180 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
183 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
184 if (AllowModify && UnCondBrIter != MBB.end() &&
185 MBB.isLayoutSuccessor(TargetBB)) {
202 BranchCode = GetOppositeBranchCondition(BranchCode);
203 MachineBasicBlock::iterator OldInst = I;
204 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
205 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
206 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
209 OldInst->eraseFromParent();
210 UnCondBrIter->eraseFromParent();
212 UnCondBrIter = MBB.end();
217 TBB = I->getOperand(0).getMBB();
218 Cond.push_back(MachineOperand::CreateImm(BranchCode));
221 //FIXME: Handle subsequent conditional branches
222 //For now, we can't handle multiple conditional branches
229 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
230 MachineBasicBlock *FBB,
231 const SmallVectorImpl<MachineOperand> &Cond,
233 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
234 assert((Cond.size() == 1 || Cond.size() == 0) &&
235 "Sparc branch conditions should have one component!");
238 assert(!FBB && "Unconditional branch with multiple successors!");
239 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
244 unsigned CC = Cond[0].getImm();
247 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
249 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
253 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
257 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
259 MachineBasicBlock::iterator I = MBB.end();
261 while (I != MBB.begin()) {
264 if (I->isDebugValue())
267 if (I->getOpcode() != SP::BA
268 && I->getOpcode() != SP::BCOND
269 && I->getOpcode() != SP::FBCOND)
270 break; // Not a branch
272 I->eraseFromParent();
279 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator I, DebugLoc DL,
281 unsigned DestReg, unsigned SrcReg,
282 bool KillSrc) const {
283 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
284 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
285 .addReg(SrcReg, getKillRegState(KillSrc));
286 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
287 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
288 .addReg(SrcReg, getKillRegState(KillSrc));
289 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
290 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
291 .addReg(SrcReg, getKillRegState(KillSrc));
293 llvm_unreachable("Impossible reg-to-reg copy");
296 void SparcInstrInfo::
297 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
298 unsigned SrcReg, bool isKill, int FI,
299 const TargetRegisterClass *RC,
300 const TargetRegisterInfo *TRI) const {
302 if (I != MBB.end()) DL = I->getDebugLoc();
304 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
305 if (RC == SP::IntRegsRegisterClass)
306 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
307 .addReg(SrcReg, getKillRegState(isKill));
308 else if (RC == SP::FPRegsRegisterClass)
309 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
310 .addReg(SrcReg, getKillRegState(isKill));
311 else if (RC == SP::DFPRegsRegisterClass)
312 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
313 .addReg(SrcReg, getKillRegState(isKill));
315 llvm_unreachable("Can't store this register to stack slot");
318 void SparcInstrInfo::
319 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
320 unsigned DestReg, int FI,
321 const TargetRegisterClass *RC,
322 const TargetRegisterInfo *TRI) const {
324 if (I != MBB.end()) DL = I->getDebugLoc();
326 if (RC == SP::IntRegsRegisterClass)
327 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
328 else if (RC == SP::FPRegsRegisterClass)
329 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
330 else if (RC == SP::DFPRegsRegisterClass)
331 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
333 llvm_unreachable("Can't load this register from stack slot");
336 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
338 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
339 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
340 if (GlobalBaseReg != 0)
341 return GlobalBaseReg;
343 // Insert the set of GlobalBaseReg into the first MBB of the function
344 MachineBasicBlock &FirstMBB = MF->front();
345 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
346 MachineRegisterInfo &RegInfo = MF->getRegInfo();
348 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
353 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
354 SparcFI->setGlobalBaseReg(GlobalBaseReg);
355 return GlobalBaseReg;